* [PATCH 0/4] x86: assorted bug fixes
@ 2021-03-24 9:21 Jan Beulich
2021-03-24 9:22 ` [PATCH 1/4] x86-64: limit breakage from gcc movdir64b et al workaround Jan Beulich
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Jan Beulich @ 2021-03-24 9:21 UTC (permalink / raw)
To: Binutils
1: limit breakage from gcc movdir64b et al workaround
2: fix AMD Zen3 insns
3: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear
4: flag bad S/G insn operand combinations
Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] x86-64: limit breakage from gcc movdir64b et al workaround
2021-03-24 9:21 [PATCH 0/4] x86: assorted bug fixes Jan Beulich
@ 2021-03-24 9:22 ` Jan Beulich
2021-03-24 9:23 ` [PATCH 2/4] x86: fix AMD Zen3 insns Jan Beulich
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2021-03-24 9:22 UTC (permalink / raw)
To: Binutils
This is only a partial fix for PR/gas 27419, in that it limits the bad
behavior of accepting mismatched operands to just x32 mode. The full fix
would be to revert commits 27f134698ac5 and b3a3496f83a1, and to address
the issue in gcc instead.
gas/
2021-03-XX Jan Beulich <jbeulich@suse.com>
PR/gas 27419
* config/tc-i386.c (process_suffix): Restrict (%rip) -> (%eip)
conversion to x32 mode.
* testsuite/gas/i386/ilp32/enqcmd.s,
testsuite/gas/i386/ilp32/enqcmd.d,
testsuite/gas/i386/ilp32/movdir.s,
testsuite/gas/i386/ilp32/movdir.d: New.
* testsuite/gas/i386/x86-64-enqcmd.s,
testsuite/gas/i386/x86-64-movdir.s: Drop mismatched operand
cases.
* testsuite/gas/i386/x86-64-enqcmd-inval.s: Add (%rip) and
(%eip) cases.
* testsuite/gas/i386/x86-64-movdir64b-reg.s Add (%eip) case.
* testsuite/gas/i386/x86-64-enqcmd.d,
testsuite/gas/i386/x86-64-enqcmd-intel.d,
testsuite/gas/i386/x86-64-enqcmd-inval.l,
testsuite/gas/i386/x86-64-movdir.d,
testsuite/gas/i386/x86-64-movdir-intel.d,
testsuite/gas/i386/x86-64-movdir64b-reg.l: Adjust expectations.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7169,7 +7169,7 @@ process_suffix (void)
/* Check the register operand for the address size prefix if
the memory operand has no real registers, like symbol, DISP
- or symbol(%rip). */
+ or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
if (i.mem_operands == 1
&& i.reg_operands == 1
&& i.operands == 2
@@ -7178,9 +7178,14 @@ process_suffix (void)
? i.op[1].regs->reg_type.bitfield.word
: i.op[1].regs->reg_type.bitfield.dword)
&& ((i.base_reg == NULL && i.index_reg == NULL)
- || (i.base_reg
+#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
+ || (x86_elf_abi == X86_64_X32_ABI
+ && i.base_reg
&& i.base_reg->reg_num == RegIP
&& i.base_reg->reg_type.bitfield.qword))
+#else
+ || 0)
+#endif
&& !add_prefix (ADDR_PREFIX_OPCODE))
return 0;
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/enqcmd.d
@@ -0,0 +1,38 @@
+#objdump: -dw
+#name: ilp32 ENQCMD[S] insns
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+ +[a-f0-9]+: f2 0f 38 f8 01 enqcmd \(%rcx\),%rax
+ +[a-f0-9]+: 67 f2 0f 38 f8 01 enqcmd \(%ecx\),%eax
+ +[a-f0-9]+: f3 0f 38 f8 01 enqcmds \(%rcx\),%rax
+ +[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds \(%ecx\),%eax
+ +[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%rip\),%rcx #.*
+ +[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%rip\),%rcx #.*
+ +[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd 0x0\(,%eiz,1\),%ecx
+ +[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd 0x12345678\(,%eiz,1\),%ecx
+ +[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds 0x0\(,%eiz,1\),%ecx
+ +[a-f0-9]+: 67 f3 0f 38 f8 0c 25 78 56 34 12 enqcmds 0x12345678\(,%eiz,1\),%ecx
+ +[a-f0-9]+: f2 0f 38 f8 01 enqcmd \(%rcx\),%rax
+ +[a-f0-9]+: 67 f2 0f 38 f8 01 enqcmd \(%ecx\),%eax
+ +[a-f0-9]+: f3 0f 38 f8 01 enqcmds \(%rcx\),%rax
+ +[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds \(%ecx\),%eax
+ +[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%rip\),%rcx #.*
+ +[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%rip\),%rcx #.*
+ +[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd 0x0\(,%eiz,1\),%ecx
+ +[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd 0x12345678\(,%eiz,1\),%ecx
+ +[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds 0x0\(,%eiz,1\),%ecx
+ +[a-f0-9]+: 67 f3 0f 38 f8 0c 25 78 56 34 12 enqcmds 0x12345678\(,%eiz,1\),%ecx
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/enqcmd.s
@@ -0,0 +1,35 @@
+# Check ENQCMD[S] 64-bit instructions in x32 mode
+
+ .allow_index_reg
+ .text
+_start:
+ enqcmd (%rcx),%rax
+ enqcmd (%ecx),%eax
+ enqcmds (%rcx),%rax
+ enqcmds (%ecx),%eax
+ enqcmd foo(%rip),%rcx
+ enqcmd foo(%rip),%ecx
+ enqcmd foo(%eip),%ecx
+ enqcmds foo(%rip),%rcx
+ enqcmds foo(%rip),%ecx
+ enqcmds foo(%eip),%ecx
+ enqcmd foo, %ecx
+ enqcmd 0x12345678, %ecx
+ enqcmds foo, %ecx
+ enqcmds 0x12345678, %ecx
+
+ .intel_syntax noprefix
+ enqcmd rax,[rcx]
+ enqcmd eax,[ecx]
+ enqcmds rax,[rcx]
+ enqcmds eax,[ecx]
+ enqcmd rcx,[rip+foo]
+ enqcmd ecx,[rip+foo]
+ enqcmd ecx,[eip+foo]
+ enqcmds rcx,[rip+foo]
+ enqcmds ecx,[rip+foo]
+ enqcmds ecx,[eip+foo]
+ enqcmd ecx,ds:foo
+ enqcmd ecx,ds:0x12345678
+ enqcmds ecx,ds:foo
+ enqcmds ecx,ds:0x12345678
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/movdir.d
@@ -0,0 +1,29 @@
+#objdump: -dw
+#name: ilp32 MOVDIR[I,64B] insns
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+ +[a-f0-9]+: 48 0f 38 f9 01 movdiri %rax,\(%rcx\)
+ +[a-f0-9]+: 66 0f 38 f8 01 movdir64b \(%rcx\),%rax
+ +[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b \(%ecx\),%eax
+ +[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%rip\),%rcx #.*
+ +[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b 0x0\(,%eiz,1\),%ecx
+ +[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b 0x12345678\(,%eiz,1\),%ecx
+ +[a-f0-9]+: 0f 38 f9 01 movdiri %eax,\(%rcx\)
+ +[a-f0-9]+: 48 0f 38 f9 01 movdiri %rax,\(%rcx\)
+ +[a-f0-9]+: 0f 38 f9 01 movdiri %eax,\(%rcx\)
+ +[a-f0-9]+: 48 0f 38 f9 01 movdiri %rax,\(%rcx\)
+ +[a-f0-9]+: 66 0f 38 f8 01 movdir64b \(%rcx\),%rax
+ +[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b \(%ecx\),%eax
+ +[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%rip\),%rcx #.*
+ +[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
+ +[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b 0x0\(,%eiz,1\),%ecx
+ +[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b 0x12345678\(,%eiz,1\),%ecx
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/movdir.s
@@ -0,0 +1,26 @@
+# Check MOVDIR[I,64B] 64-bit instructions in x32 mode
+
+ .allow_index_reg
+ .text
+_start:
+ movdiri %rax, (%rcx)
+ movdir64b (%rcx),%rax
+ movdir64b (%ecx),%eax
+ movdir64b foo(%rip),%rcx
+ movdir64b foo(%rip),%ecx
+ movdir64b foo(%eip),%ecx
+ movdir64b foo, %ecx
+ movdir64b 0x12345678, %ecx
+
+ .intel_syntax noprefix
+ movdiri [rcx],eax
+ movdiri [rcx],rax
+ movdiri dword ptr [rcx],eax
+ movdiri qword ptr [rcx],rax
+ movdir64b rax,[rcx]
+ movdir64b eax,[ecx]
+ movdir64b rcx,[rip+foo]
+ movdir64b ecx,[rip+foo]
+ movdir64b ecx,[eip+foo]
+ movdir64b ecx,ds:foo
+ movdir64b ecx,ds:0x12345678
--- a/gas/testsuite/gas/i386/x86-64-enqcmd-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-enqcmd-intel.d
@@ -1,4 +1,3 @@
-#as:
#objdump: -dw -Mintel
#name: x86_64 ENQCMD[S] insns (Intel disassembly)
#source: x86-64-enqcmd.s
@@ -15,10 +14,8 @@ Disassembly of section \.text:
+[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds eax,\[ecx\]
+[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd rcx,\[rip\+0x0\] #.*
+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd ecx,\[eip\+0x0\] #.*
- +[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd ecx,\[eip\+0x0\] #.*
+[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds rcx,\[rip\+0x0\] #.*
+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds ecx,\[eip\+0x0\] #.*
- +[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds ecx,\[eip\+0x0\] #.*
+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd ecx,\[eiz\*1\+0x0\]
+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd ecx,\[eiz\*1\+0x12345678\]
+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds ecx,\[eiz\*1\+0x0\]
@@ -29,10 +26,8 @@ Disassembly of section \.text:
+[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds eax,\[ecx\]
+[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd rcx,\[rip\+0x0\] #.*
+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd ecx,\[eip\+0x0\] #.*
- +[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd ecx,\[eip\+0x0\] #.*
+[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds rcx,\[rip\+0x0\] #.*
+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds ecx,\[eip\+0x0\] #.*
- +[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds ecx,\[eip\+0x0\] #.*
+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd ecx,\[eiz\*1\+0x0\]
+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd ecx,\[eiz\*1\+0x12345678\]
+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds ecx,\[eiz\*1\+0x0\]
--- a/gas/testsuite/gas/i386/x86-64-enqcmd-inval.l
+++ b/gas/testsuite/gas/i386/x86-64-enqcmd-inval.l
@@ -1,9 +1,13 @@
.* Assembler messages:
.*6: Error: invalid register operand size for `enqcmd'
.*7: Error: invalid register operand size for `enqcmd'
-.*8: Error: invalid register operand size for `enqcmds'
-.*9: Error: invalid register operand size for `enqcmds'
-.*12: Error: invalid register operand size for `enqcmd'
-.*13: Error: invalid register operand size for `enqcmd'
-.*14: Error: invalid register operand size for `enqcmds'
-.*15: Error: invalid register operand size for `enqcmds'
+.*8: Error: invalid register operand size for `enqcmd'
+.*9: Error: invalid register operand size for `enqcmd'
+.*10: Error: invalid register operand size for `enqcmds'
+.*11: Error: invalid register operand size for `enqcmds'
+.*12: Error: invalid register operand size for `enqcmds'
+.*13: Error: invalid register operand size for `enqcmds'
+.*16: Error: invalid register operand size for `enqcmd'
+.*17: Error: invalid register operand size for `enqcmd'
+.*18: Error: invalid register operand size for `enqcmds'
+.*19: Error: invalid register operand size for `enqcmds'
--- a/gas/testsuite/gas/i386/x86-64-enqcmd-inval.s
+++ b/gas/testsuite/gas/i386/x86-64-enqcmd-inval.s
@@ -1,12 +1,16 @@
-# Check error for ENQCMD[S] 32-bit instructions
+# Check error for ENQCMD[S] 64-bit instructions
.allow_index_reg
.text
_start:
enqcmd (%esi),%rax
+ enqcmd (%eip),%rax
enqcmd (%rsi),%eax
+ enqcmd (%rip),%eax
enqcmds (%esi),%rax
+ enqcmds (%eip),%rax
enqcmds (%rsi),%eax
+ enqcmds (%rip),%eax
.intel_syntax noprefix
enqcmd rax,[esi]
--- a/gas/testsuite/gas/i386/x86-64-enqcmd.d
+++ b/gas/testsuite/gas/i386/x86-64-enqcmd.d
@@ -1,7 +1,5 @@
-#as:
#objdump: -dw
#name: x86_64 ENQCMD[S] insns
-#source: x86-64-enqcmd.s
.*: +file format .*
@@ -15,10 +13,8 @@ Disassembly of section \.text:
+[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds \(%ecx\),%eax
+[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%rip\),%rcx #.*
+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
- +[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
+[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%rip\),%rcx #.*
+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
- +[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd 0x0\(,%eiz,1\),%ecx
+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd 0x12345678\(,%eiz,1\),%ecx
+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds 0x0\(,%eiz,1\),%ecx
@@ -29,10 +25,8 @@ Disassembly of section \.text:
+[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds \(%ecx\),%eax
+[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%rip\),%rcx #.*
+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
- +[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
+[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%rip\),%rcx #.*
+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
- +[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd 0x0\(,%eiz,1\),%ecx
+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd 0x12345678\(,%eiz,1\),%ecx
+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds 0x0\(,%eiz,1\),%ecx
--- a/gas/testsuite/gas/i386/x86-64-enqcmd.s
+++ b/gas/testsuite/gas/i386/x86-64-enqcmd.s
@@ -8,10 +8,8 @@ _start:
enqcmds (%rcx),%rax
enqcmds (%ecx),%eax
enqcmd foo(%rip),%rcx
- enqcmd foo(%rip),%ecx
enqcmd foo(%eip),%ecx
enqcmds foo(%rip),%rcx
- enqcmds foo(%rip),%ecx
enqcmds foo(%eip),%ecx
enqcmd foo, %ecx
enqcmd 0x12345678, %ecx
@@ -24,10 +22,8 @@ _start:
enqcmds rax,[rcx]
enqcmds eax,[ecx]
enqcmd rcx,[rip+foo]
- enqcmd ecx,[rip+foo]
enqcmd ecx,[eip+foo]
enqcmds rcx,[rip+foo]
- enqcmds ecx,[rip+foo]
enqcmds ecx,[eip+foo]
enqcmd ecx,ds:foo
enqcmd ecx,ds:0x12345678
--- a/gas/testsuite/gas/i386/x86-64-movdir-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-movdir-intel.d
@@ -1,4 +1,3 @@
-#as:
#objdump: -dw -Mintel
#name: x86_64 MOVDIR[I,64B] insns (Intel disassembly)
#source: x86-64-movdir.s
@@ -14,7 +13,6 @@ Disassembly of section \.text:
+[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b eax,\[ecx\]
+[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b rcx,\[rip\+0x0\] #.*
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b ecx,\[eip\+0x0\] #.*
- +[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b ecx,\[eip\+0x0\] #.*
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b ecx,\[eiz\*1\+0x0\]
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b ecx,\[eiz\*1\+0x12345678\]
+[a-f0-9]+: 0f 38 f9 01 movdiri DWORD PTR \[rcx\],eax
@@ -25,7 +23,6 @@ Disassembly of section \.text:
+[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b eax,\[ecx\]
+[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b rcx,\[rip\+0x0\] #.*
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b ecx,\[eip\+0x0\] #.*
- +[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b ecx,\[eip\+0x0\] #.*
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b ecx,\[eiz\*1\+0x0\]
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b ecx,\[eiz\*1\+0x12345678\]
#pass
--- a/gas/testsuite/gas/i386/x86-64-movdir.d
+++ b/gas/testsuite/gas/i386/x86-64-movdir.d
@@ -1,7 +1,5 @@
-#as:
#objdump: -dw
#name: x86_64 MOVDIR[I,64B] insns
-#source: x86-64-movdir.s
.*: +file format .*
@@ -14,7 +12,6 @@ Disassembly of section \.text:
+[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b \(%ecx\),%eax
+[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%rip\),%rcx #.*
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
- +[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b 0x0\(,%eiz,1\),%ecx
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b 0x12345678\(,%eiz,1\),%ecx
+[a-f0-9]+: 0f 38 f9 01 movdiri %eax,\(%rcx\)
@@ -25,7 +22,6 @@ Disassembly of section \.text:
+[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b \(%ecx\),%eax
+[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%rip\),%rcx #.*
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
- +[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b 0x0\(,%eiz,1\),%ecx
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b 0x12345678\(,%eiz,1\),%ecx
#pass
--- a/gas/testsuite/gas/i386/x86-64-movdir.s
+++ b/gas/testsuite/gas/i386/x86-64-movdir.s
@@ -7,7 +7,6 @@ _start:
movdir64b (%rcx),%rax
movdir64b (%ecx),%eax
movdir64b foo(%rip),%rcx
- movdir64b foo(%rip),%ecx
movdir64b foo(%eip),%ecx
movdir64b foo, %ecx
movdir64b 0x12345678, %ecx
@@ -20,7 +19,6 @@ _start:
movdir64b rax,[rcx]
movdir64b eax,[ecx]
movdir64b rcx,[rip+foo]
- movdir64b ecx,[rip+foo]
movdir64b ecx,[eip+foo]
movdir64b ecx,ds:foo
movdir64b ecx,ds:0x12345678
--- a/gas/testsuite/gas/i386/x86-64-movdir64b-reg.l
+++ b/gas/testsuite/gas/i386/x86-64-movdir64b-reg.l
@@ -1,5 +1,7 @@
.*: Assembler messages:
.*:6: Error: invalid register operand size for `movdir64b'
.*:7: Error: invalid register operand size for `movdir64b'
-.*:10: Error: invalid register operand size for `movdir64b'
-.*:11: Error: invalid register operand size for `movdir64b'
+.*:8: Error: invalid register operand size for `movdir64b'
+.*:9: Error: invalid register operand size for `movdir64b'
+.*:12: Error: invalid register operand size for `movdir64b'
+.*:13: Error: invalid register operand size for `movdir64b'
--- a/gas/testsuite/gas/i386/x86-64-movdir64b-reg.s
+++ b/gas/testsuite/gas/i386/x86-64-movdir64b-reg.s
@@ -4,7 +4,9 @@
.text
_start:
movdir64b (%esi),%rax
+ movdir64b (%eip),%rax
movdir64b (%rsi),%eax
+ movdir64b (%rip),%eax
.intel_syntax noprefix
movdir64b rax,[esi]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/4] x86: fix AMD Zen3 insns
2021-03-24 9:21 [PATCH 0/4] x86: assorted bug fixes Jan Beulich
2021-03-24 9:22 ` [PATCH 1/4] x86-64: limit breakage from gcc movdir64b et al workaround Jan Beulich
@ 2021-03-24 9:23 ` Jan Beulich
2021-03-24 9:24 ` [PATCH 3/4] x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear Jan Beulich
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2021-03-24 9:23 UTC (permalink / raw)
To: Binutils
For INVLPGB the operand count was wrong (besides %edx there's also %ecx
which is an input to the insn). In this case I see little sense in
retaining the bogus 2-operand template. Plus swapping of the operands
wasn't properly suppressed for Intel syntax.
For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates
were specified. These get retained, as the address operand is the only
one really needed to expressed non-default address size, but only for
compatibility reasons. Proper multi-operand insn get introduced and the
testcases get adjusted / extended accordingly.
While at it also drop the redundant definition of __amd64__ - we already
have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
gas/
2021-03-XX Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Widen set of insns to avoid
swapping operands for.
* testsuite/gas/i386/invlpgb.s: Fix, re-arrange, and add Intel
syntax tests.
* testsuite/gas/i386/snp.s: Re-arrange and add multi-operand as
well as Intel syntax tests.
* testsuite/gas/i386/invlpgb.d, testsuite/gas/i386/snp.d: Adjust
expectations.
* testsuite/gas/i386/invlpgb64.d, testsuite/gas/i386/snp64.d:
Likewise. Drop passing --def-sym to as.
opcodes/
2021-03-XX Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (invlpgb): Fix multi-operand form.
(pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
single-operand forms as deprecated.
* i386-tbl.h: Re-generate.
---
I'd be happy to drop the single-operand PVALIDATE, RMPADJUST, and
RMPUPDATE templates.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4679,16 +4679,18 @@ md_assemble (char *line)
operands at hand. */
/* All Intel opcodes have reversed operands except for "bound", "enter",
- "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
- intersegment "jmp" and "call" instructions with 2 immediate operands so
- that the immediate segment precedes the offset, as it does when in AT&T
- mode. */
+ "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
+ "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp"
+ and "call" instructions with 2 immediate operands so that the immediate
+ segment precedes the offset consistently in Intel and AT&T modes. */
if (intel_syntax
&& i.operands > 1
&& (strcmp (mnemonic, "bound") != 0)
- && (strcmp (mnemonic, "invlpga") != 0)
+ && (strncmp (mnemonic, "invlpg", 6) != 0)
&& (strncmp (mnemonic, "monitor", 7) != 0)
&& (strncmp (mnemonic, "mwait", 5) != 0)
+ && (strcmp (mnemonic, "pvalidate") != 0)
+ && (strncmp (mnemonic, "rmp", 3) != 0)
&& (strcmp (mnemonic, "tpause") != 0)
&& (strcmp (mnemonic, "umwait") != 0)
&& !(operand_type_check (i.types[0], imm)
--- a/gas/testsuite/gas/i386/invlpgb.d
+++ b/gas/testsuite/gas/i386/invlpgb.d
@@ -11,4 +11,8 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
[0-9a-f]+ <att16>:
[ ]*[a-f0-9]+:[ ]+67 0f 01 fe[ ]+addr16 invlpgb[ ]*
+[0-9a-f]+ <intel32>:
+[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
+[0-9a-f]+ <intel16>:
+[ ]*[a-f0-9]+:[ ]+67 0f 01 fe[ ]+addr16 invlpgb[ ]*
#pass
--- a/gas/testsuite/gas/i386/invlpgb.s
+++ b/gas/testsuite/gas/i386/invlpgb.s
@@ -3,13 +3,25 @@
.text
_start:
invlpgb
-.ifdef __amd64__
+.ifdef x86_64
att64:
- invlpgb %rax, %edx
+ invlpgb %rax, %ecx, %edx
.endif
att32:
- invlpgb %eax, %edx
-.ifndef __amd64__
+ invlpgb %eax, %ecx, %edx
+.ifndef x86_64
att16:
- invlpgb %ax, %edx
+ invlpgb %ax, %ecx, %edx
+.endif
+
+ .intel_syntax noprefix
+.ifdef x86_64
+intel64:
+ invlpgb rax, ecx, edx
+.endif
+intel32:
+ invlpgb eax, ecx, edx
+.ifndef x86_64
+intel16:
+ invlpgb ax, ecx, edx
.endif
--- a/gas/testsuite/gas/i386/invlpgb64.d
+++ b/gas/testsuite/gas/i386/invlpgb64.d
@@ -1,4 +1,3 @@
-#as: --defsym __amd64__=1
#objdump: -dw
#name: 64-bit INVLPGB insn
#source: invlpgb.s
@@ -13,4 +12,8 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
[0-9a-f]+ <att32>:
[ ]*[a-f0-9]+:[ ]+67 0f 01 fe[ ]+addr32 invlpgb[ ]*
+[0-9a-f]+ <intel64>:
+[ ]*[a-f0-9]+:[ ]+0f 01 fe[ ]+invlpgb[ ]*
+[0-9a-f]+ <intel32>:
+[ ]*[a-f0-9]+:[ ]+67 0f 01 fe[ ]+addr32 invlpgb[ ]*
#pass
--- a/gas/testsuite/gas/i386/snp.d
+++ b/gas/testsuite/gas/i386/snp.d
@@ -6,7 +6,12 @@
Disassembly of section \.text:
-00000000 <att32>:
+0+ <att>:
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 ff[ ]+addr16 pvalidate[ ]*
+
+[0-9a-f]+ <intel>:
[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 ff[ ]+addr16 pvalidate[ ]*
--- a/gas/testsuite/gas/i386/snp.s
+++ b/gas/testsuite/gas/i386/snp.s
@@ -1,23 +1,39 @@
# Check SNP instructions
.text
-.ifdef __amd64__
-att64:
- psmash %rax
+att:
+ pvalidate
+ pvalidate %eax, %ecx, %edx
+.ifdef x86_64
+ pvalidate %rax, %ecx, %edx
psmash
- psmash %eax
- pvalidate %rax
- pvalidate %eax
- rmpupdate %rax
+ psmash %rax
+ psmash %eax
rmpupdate
- rmpupdate %eax
- rmpadjust %rax
+ rmpupdate %rax, %rcx
+ rmpupdate %eax, %rcx
rmpadjust
- rmpadjust %eax
+ rmpadjust %rax, %rcx, %rdx
+ rmpadjust %eax, %rcx, %rdx
+.else
+ pvalidate %ax, %ecx, %edx
.endif
-.ifndef __amd64__
-att32:
+
+ .intel_syntax noprefix
+intel:
pvalidate
- pvalidate %eax
- pvalidate %ax
+ pvalidate eax, ecx, edx
+.ifdef x86_64
+ pvalidate rax, ecx, edx
+ psmash
+ psmash rax
+ psmash eax
+ rmpupdate
+ rmpupdate rax, rcx
+ rmpupdate eax, rcx
+ rmpadjust
+ rmpadjust rax, rcx, rdx
+ rmpadjust eax, rcx, rdx
+.else
+ pvalidate ax, ecx, edx
.endif
--- a/gas/testsuite/gas/i386/snp64.d
+++ b/gas/testsuite/gas/i386/snp64.d
@@ -1,4 +1,3 @@
-#as: --defsym __amd64__=1
#objdump: -dw
#name: 64-bit SNP insn
#source: snp.s
@@ -8,12 +7,27 @@
Disassembly of section \.text:
-0+000 <att64>:
+0+ <att>:
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 ff[ ]+addr32 pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
[ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash[ ]*
[ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash[ ]*
[ ]*[a-f0-9]+:[ ]+67 f3 0f 01 ff[ ]+addr32 psmash[ ]*
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate[ ]*
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate[ ]*
+[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fe[ ]+addr32 rmpupdate[ ]*
+[ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust[ ]*
+[ ]*[a-f0-9]+:[ ]+f3 0f 01 fe[ ]+rmpadjust[ ]*
+[ ]*[a-f0-9]+:[ ]+67 f3 0f 01 fe[ ]+addr32 rmpadjust[ ]*
+
+[0-9a-f]+ <intel>:
[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 ff[ ]+addr32 pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+f2 0f 01 ff[ ]+pvalidate[ ]*
+[ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash[ ]*
+[ ]*[a-f0-9]+:[ ]+f3 0f 01 ff[ ]+psmash[ ]*
+[ ]*[a-f0-9]+:[ ]+67 f3 0f 01 ff[ ]+addr32 psmash[ ]*
[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate[ ]*
[ ]*[a-f0-9]+:[ ]+f2 0f 01 fe[ ]+rmpupdate[ ]*
[ ]*[a-f0-9]+:[ ]+67 f2 0f 01 fe[ ]+addr32 rmpupdate[ ]*
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3979,7 +3979,7 @@ vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQ
// INVLPGB instructions
invlpgb, 0xf01fe, None, CpuINVLPGB, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
-invlpgb, 0xf01fe, None, CpuINVLPGB, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegD|Dword }
+invlpgb, 0xf01fe, None, CpuINVLPGB, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
// INVLPGB instructions end
@@ -4126,10 +4126,14 @@ mcommit, 0x0f01fa, None, CpuMCOMMIT, Pre
psmash, 0xf01ff, None, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
psmash, 0xf01ff, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
pvalidate, 0xf01ff, None, CpuSNP, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
-pvalidate, 0xf01ff, None, CpuSNP, AddrPrefixOpReg|Prefix_0XF2, { Acc|Word|Dword|Qword }
+pvalidate, 0xf01ff, None, CpuSNP, AddrPrefixOpReg|Prefix_0XF2, { Acc|Word|Dword|Qword, RegC|Dword, RegD|Dword }
rmpupdate, 0xf01fe, None, CpuSNP|Cpu64, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
-rmpupdate, 0xf01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF2, { Acc|Dword|Qword }
+rmpupdate, 0xf01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF2, { Acc|Dword|Qword, RegC|Qword }
rmpadjust, 0xf01fe, None, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
+rmpadjust, 0xf01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword, RegC|Qword, RegD|Qword }
+// The single-operand forms exist only for compatibility with older gas.
+pvalidate, 0xf01ff, None, CpuSNP, AddrPrefixOpReg|Prefix_0XF2, { Acc|Word|Dword|Qword }
+rmpupdate, 0xf01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF2, { Acc|Dword|Qword }
rmpadjust, 0xf01fe, None, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
// SNP instructions end
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/4] x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear
2021-03-24 9:21 [PATCH 0/4] x86: assorted bug fixes Jan Beulich
2021-03-24 9:22 ` [PATCH 1/4] x86-64: limit breakage from gcc movdir64b et al workaround Jan Beulich
2021-03-24 9:23 ` [PATCH 2/4] x86: fix AMD Zen3 insns Jan Beulich
@ 2021-03-24 9:24 ` Jan Beulich
2021-03-24 9:24 ` [PATCH 4/4] x86: flag bad S/G insn operand combinations Jan Beulich
2021-03-24 14:02 ` [PATCH 0/4] x86: assorted bug fixes H.J. Lu
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2021-03-24 9:24 UTC (permalink / raw)
To: Binutils
This combination makes no sense and is documented to cause #UD.
gas/
2021-03-XX Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512f-nondef.s: Add case for EVEX.z
without mask register.
* testsuite/gas/i386/avx512f-nondef.d: Adjust expectations.
opcodes/
2021-03-XX Jan Beulich <jbeulich@suse.com>
* i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
zeroing-masking without masking.
---
Alternatively we could append "/(bad)" to the destination operand.
--- a/gas/testsuite/gas/i386/avx512f-nondef.d
+++ b/gas/testsuite/gas/i386/avx512f-nondef.d
@@ -1,6 +1,6 @@
#as:
#objdump: -dw
-#name: i386 AVX512F insns with nondefault values in ignored bits
+#name: i386 AVX512F insns with nondefault values in ignored / reserved bits
.*: +file format .*
@@ -16,4 +16,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 vpmovdb %zmm6,\(bad\)
[ ]*[a-f0-9]+: f2 7e 58 bnd jle (0x7d|7d <.text\+0x7d>)
[ ]*[a-f0-9]+: 31 72 7f xor %esi,0x7f\(%edx\)
+[ ]*[a-f0-9]+: 62 f1 7c 88 58 \(bad\)
+[ ]*[a-f0-9]+: c3 ret *
#pass
--- a/gas/testsuite/gas/i386/avx512f-nondef.s
+++ b/gas/testsuite/gas/i386/avx512f-nondef.s
@@ -13,3 +13,5 @@
.byte 0x62, 0xf2, 0x7e, 0x48, 0x31, 0x72, 0x7f
# vpmovdb %zmm6, 2032(%rdx) # with set EVEX.B bit - we should get (bad) operand
.byte 0x62, 0xf2, 0x7e, 0x58, 0x31, 0x72, 0x7f
+# vaddps xmm0, xmm0, xmm3 # with EVEX.z set
+.byte 0x62, 0xf1, 0x7c, 0x88, 0x58, 0xc3
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -9739,6 +9739,13 @@ print_insn (bfd_vma pc, disassemble_info
return end_codep - priv.the_buffer;
}
+ /* If EVEX.z is set, there must be an actual mask register in use. */
+ if (vex.zeroing && vex.mask_register_specifier == 0)
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return end_codep - priv.the_buffer;
+ }
+
switch (dp->prefix_requirement)
{
case PREFIX_DATA:
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/4] x86: flag bad S/G insn operand combinations
2021-03-24 9:21 [PATCH 0/4] x86: assorted bug fixes Jan Beulich
` (2 preceding siblings ...)
2021-03-24 9:24 ` [PATCH 3/4] x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear Jan Beulich
@ 2021-03-24 9:24 ` Jan Beulich
2021-03-24 14:02 ` [PATCH 0/4] x86: assorted bug fixes H.J. Lu
4 siblings, 0 replies; 6+ messages in thread
From: Jan Beulich @ 2021-03-24 9:24 UTC (permalink / raw)
To: Binutils
For VEX-encoded ones, all three involved vector registers have to be
distinct. For EVEX-encoded ones an actual mask register has to be in use
and zeroing-masking cannot be used (violation of either will #UD).
Additionally both involved vector registers have to be distinct for
EVEX-encoded gathers.
gas/
2021-03-XX Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512f-nondef.s: Add vgather cases.
* testsuite/gas/i386/x86-64-vgather-check.s: Add cases with
colliding registers in the upper half of the space.
* testsuite/gas/i386/avx512f-nondef.d,
testsuite/gas/i386/vgather-check.d,
testsuite/gas/i386/x86-64-vgather-check.d,
testsuite/gas/i386/x86-64-vgather-check-error.l,
testsuite/gas/i386/x86-64-vgather-check-warn.e: Adjust
expecations.
* testsuite/gas/i386/vgather-check-none.d,
testsuite/gas/i386/vgather-check-warn.d,
testsuite/gas/i386/x86-64-vgather-check-none.d,
testsuite/gas/i386/x86-64-vgather-check-warn.d: Refer to "base"
tests for expected dump output.
opcodes/
2021-03-XX Jan Beulich <jbeulich@suse.com>
* i386-dis.c (XMGatherD, VexGatherD): New.
(vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
(print_insn): Check masking for S/G insns.
(OP_E_memory): New local variable check_gather. Extend mandatory
SIB check. Check register conflicts for (EVEX-encoded) gathers.
Extend check for disallowed 16-bit addressing.
(OP_VEX): New local variables modrm_reg and sib_index. Convert
if()s to switch(). Check register conflicts for (VEX-encoded)
gathers. Drop no longer reachable cases.
* i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
vgatherdp*.
---
Of course there's a wider issue here - there are more insns not allowing
zeroing-masking. And there are also a number of insns not allowing
masking at all. I'm considering whether to express this via an insn name
macro expanding to nothing, but flagging the issue (such that "/(bad)"
can be appended to the destination operand after having appended the
masking notation, effectively generalizing what the patch here does for
this specific case).
--- a/gas/testsuite/gas/i386/avx512f-nondef.d
+++ b/gas/testsuite/gas/i386/avx512f-nondef.d
@@ -18,4 +18,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 31 72 7f xor %esi,0x7f\(%edx\)
[ ]*[a-f0-9]+: 62 f1 7c 88 58 \(bad\)
[ ]*[a-f0-9]+: c3 ret *
+[ ]*[a-f0-9]+: 62 f2 7d 4f 92 01 vgatherdps \(bad\),%zmm0\{%k7\}
+[ ]*[a-f0-9]+: 67 62 f2 7d 4f 92 01 addr16 vgatherdps \(bad\),%zmm0\{%k7\}
+[ ]*[a-f0-9]+: 62 f2 7d cf 92 04 08 vgatherdps \(%eax,%zmm1(,1)?\),%zmm0\{%k7\}\{z\}/\(bad\)
+[ ]*[a-f0-9]+: 62 f2 7d 48 92 04 08 vgatherdps \(%eax,%zmm1(,1)?\),%zmm0/\(bad\)
#pass
--- a/gas/testsuite/gas/i386/avx512f-nondef.s
+++ b/gas/testsuite/gas/i386/avx512f-nondef.s
@@ -15,3 +15,11 @@
.byte 0x62, 0xf2, 0x7e, 0x58, 0x31, 0x72, 0x7f
# vaddps xmm0, xmm0, xmm3 # with EVEX.z set
.byte 0x62, 0xf1, 0x7c, 0x88, 0x58, 0xc3
+# vgatherdps (%ecx), %zmm0{%k7} # without SIB / index register
+.byte 0x62, 0xf2, 0x7d, 0x4f, 0x92, 0x01
+# vgatherdps (%bx,%xmm?), %zmm0{%k7} # with 16-bit addressing
+.byte 0x67, 0x62, 0xf2, 0x7d, 0x4f, 0x92, 0x01
+# vgatherdps (%eax,%zmm1), %zmm0{%k7}{z} # with set EVEX.z
+.byte 0x62, 0xf2, 0x7d, 0xcf, 0x92, 0x04, 0x08
+# vgatherdps (%eax,%zmm1), %zmm0 # without actual mask register
+.byte 0x62, 0xf2, 0x7d, 0x48, 0x92, 0x04, 0x08
--- a/gas/testsuite/gas/i386/vgather-check-none.d
+++ b/gas/testsuite/gas/i386/vgather-check-none.d
@@ -1,34 +1,4 @@
#as: -moperand-check=error -I${srcdir}/$subdir
#objdump: -dw
#name: i386 vgather check (.operand_check none)
-
-.*: file format .*
-
-Disassembly of section .text:
-
-0+ <vgather>:
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 04 08[ ]+vgatherdps %xmm2,\(%eax,%xmm1,1\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2,\(%eax,%xmm1,2\),%xmm2
-[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1,\(%eax,%xmm1,4\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%eax,%xmm1,8\),%xmm1
-
-00000018 <avx512vgather>:
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 fd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 f5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 fd 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 f5 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 fd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 f5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 fd 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 f5 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 29 91 b4 fd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%ymm7,8\),%xmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 29 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%ymm6,8\),%xmm6\{%k1\}
-#pass
+#dump: vgather-check.d
--- a/gas/testsuite/gas/i386/vgather-check-warn.d
+++ b/gas/testsuite/gas/i386/vgather-check-warn.d
@@ -1,35 +1,4 @@
#source: vgather-check.s
#warning_output: vgather-check-warn.e
#objdump: -dw
-#name: i386 vgather check (warning)
-
-.*: file format .*
-
-Disassembly of section .text:
-
-0+ <vgather>:
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 04 08[ ]+vgatherdps %xmm2,\(%eax,%xmm1,1\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2,\(%eax,%xmm1,2\),%xmm2
-[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1,\(%eax,%xmm1,4\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%eax,%xmm1,8\),%xmm1
-
-00000018 <avx512vgather>:
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 fd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 f5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 fd 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 f5 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 fd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 f5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 fd 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 f5 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 29 91 b4 fd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%ymm7,8\),%xmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 29 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%ymm6,8\),%xmm6\{%k1\}
-#pass
+#dump: vgather-check.d
--- a/gas/testsuite/gas/i386/vgather-check.d
+++ b/gas/testsuite/gas/i386/vgather-check.d
@@ -8,27 +8,27 @@ Disassembly of section .text:
0+ <vgather>:
[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 04 08[ ]+vgatherdps %xmm2,\(%eax,%xmm1,1\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2,\(%eax,%xmm1,2\),%xmm2
-[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1,\(%eax,%xmm1,4\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%eax,%xmm1,8\),%xmm1
+[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2/\(bad\),\(%eax,%xmm1,2\),%xmm2/\(bad\)
+[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1/\(bad\),\(%eax,%xmm1,4\)/\(bad\),%xmm0
+[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%eax,%xmm1,8\)/\(bad\),%xmm1/\(bad\)
00000018 <avx512vgather>:
[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 fd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 f5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 f5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm6,8\)/\(bad\),%zmm6\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 fd 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 f5 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 f5 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm6,8\)/\(bad\),%zmm6\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 fd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 f5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 f5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm6,8\)/\(bad\),%zmm6\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 fd 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 f5 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 f5 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm6,8\)/\(bad\),%ymm6\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm6,8\)/\(bad\),%zmm6\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm6,8\)/\(bad\),%zmm6\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm6,8\)/\(bad\),%ymm6\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm6,8\)/\(bad\),%zmm6\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 f2 7d 29 91 b4 fd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%ymm7,8\),%xmm6\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 f2 7d 29 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%ymm6,8\),%xmm6\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 f2 7d 29 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%ymm6,8\)/\(bad\),%xmm6\{%k1\}
#pass
--- a/gas/testsuite/gas/i386/x86-64-vgather-check-error.l
+++ b/gas/testsuite/gas/i386/x86-64-vgather-check-error.l
@@ -1,13 +1,16 @@
.*: Assembler messages:
.*:6: Error: .*
.*:8: Error: .*
-.*:10: Error: .*
-.*:15: Error: .*
-.*:17: Error: .*
-.*:19: Error: .*
-.*:21: Error: .*
-.*:23: Error: .*
-.*:25: Error: .*
-.*:27: Error: .*
-.*:29: Error: .*
-.*:31: Error: .*
+.*:9: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:14: Error: .*
+.*:18: Error: .*
+.*:20: Error: .*
+.*:22: Error: .*
+.*:24: Error: .*
+.*:26: Error: .*
+.*:28: Error: .*
+.*:30: Error: .*
+.*:32: Error: .*
+.*:34: Error: .*
--- a/gas/testsuite/gas/i386/x86-64-vgather-check-none.d
+++ b/gas/testsuite/gas/i386/x86-64-vgather-check-none.d
@@ -1,37 +1,4 @@
#as: -moperand-check=error -I${srcdir}/$subdir
#objdump: -dw
#name: x86-64 vgather check (.operand_check none)
-
-.*: file format .*
-
-Disassembly of section .text:
-
-0+ <vgather>:
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 04 08[ ]+vgatherdps %xmm2,\(%rax,%xmm1,1\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2,\(%rax,%xmm1,2\),%xmm2
-[ ]*[a-f0-9]+:[ ]+c4 62 69 92 14 48[ ]+vgatherdps %xmm2,\(%rax,%xmm1,2\),%xmm10
-[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1,\(%rax,%xmm1,4\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 31 92 04 88[ ]+vgatherdps %xmm9,\(%rax,%xmm1,4\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm1
-[ ]*[a-f0-9]+:[ ]+c4 62 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm9
-
-000000000000002a <avx512vgather>:
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 cd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 c5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 cd 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 c5 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 cd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 c5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 cd 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 c5 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 cd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 c5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 cd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 c5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 cd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 cd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 c5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 21 91 84 cd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%ymm17,8\),%xmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 21 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%ymm16,8\),%xmm16\{%k1\}
-#pass
+#dump: x86-64-vgather-check.d
--- a/gas/testsuite/gas/i386/x86-64-vgather-check-warn.d
+++ b/gas/testsuite/gas/i386/x86-64-vgather-check-warn.d
@@ -2,37 +2,4 @@
#warning_output: x86-64-vgather-check-warn.e
#objdump: -dw
#name: x86-64 vgather check (warning)
-
-.*: file format .*
-
-Disassembly of section .text:
-
-0+ <vgather>:
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 04 08[ ]+vgatherdps %xmm2,\(%rax,%xmm1,1\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2,\(%rax,%xmm1,2\),%xmm2
-[ ]*[a-f0-9]+:[ ]+c4 62 69 92 14 48[ ]+vgatherdps %xmm2,\(%rax,%xmm1,2\),%xmm10
-[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1,\(%rax,%xmm1,4\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 31 92 04 88[ ]+vgatherdps %xmm9,\(%rax,%xmm1,4\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm1
-[ ]*[a-f0-9]+:[ ]+c4 62 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm9
-
-000000000000002a <avx512vgather>:
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 cd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 c5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 cd 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 c5 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 cd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 c5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 cd 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 c5 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 cd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 c5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 cd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 c5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 cd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 cd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 c5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 21 91 84 cd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%ymm17,8\),%xmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 21 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%ymm16,8\),%xmm16\{%k1\}
-#pass
+#dump: x86-64-vgather-check.d
--- a/gas/testsuite/gas/i386/x86-64-vgather-check-warn.e
+++ b/gas/testsuite/gas/i386/x86-64-vgather-check-warn.e
@@ -1,13 +1,16 @@
.*: Assembler messages:
.*:6: Warning: .*
.*:8: Warning: .*
-.*:10: Warning: .*
-.*:15: Warning: .*
-.*:17: Warning: .*
-.*:19: Warning: .*
-.*:21: Warning: .*
-.*:23: Warning: .*
-.*:25: Warning: .*
-.*:27: Warning: .*
-.*:29: Warning: .*
-.*:31: Warning: .*
+.*:9: Warning: .*
+.*:11: Warning: .*
+.*:12: Warning: .*
+.*:14: Warning: .*
+.*:18: Warning: .*
+.*:20: Warning: .*
+.*:22: Warning: .*
+.*:24: Warning: .*
+.*:26: Warning: .*
+.*:28: Warning: .*
+.*:30: Warning: .*
+.*:32: Warning: .*
+.*:34: Warning: .*
--- a/gas/testsuite/gas/i386/x86-64-vgather-check.d
+++ b/gas/testsuite/gas/i386/x86-64-vgather-check.d
@@ -8,30 +8,33 @@ Disassembly of section .text:
0+ <vgather>:
[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 04 08[ ]+vgatherdps %xmm2,\(%rax,%xmm1,1\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2,\(%rax,%xmm1,2\),%xmm2
+[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2/\(bad\),\(%rax,%xmm1,2\),%xmm2/\(bad\)
[ ]*[a-f0-9]+:[ ]+c4 62 69 92 14 48[ ]+vgatherdps %xmm2,\(%rax,%xmm1,2\),%xmm10
-[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1,\(%rax,%xmm1,4\),%xmm0
+[ ]*[a-f0-9]+:[ ]+c4 62 29 92 14 48[ ]+vgatherdps %xmm10/\(bad\),\(%rax,%xmm1,2\),%xmm10/\(bad\)
+[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1/\(bad\),\(%rax,%xmm1,4\)/\(bad\),%xmm0
[ ]*[a-f0-9]+:[ ]+c4 e2 31 92 04 88[ ]+vgatherdps %xmm9,\(%rax,%xmm1,4\),%xmm0
-[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm1
+[ ]*[a-f0-9]+:[ ]+c4 a2 31 92 04 88[ ]+vgatherdps %xmm9/\(bad\),\(%rax,%xmm9,4\)/\(bad\),%xmm0
+[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\)/\(bad\),%xmm1/\(bad\)
[ ]*[a-f0-9]+:[ ]+c4 62 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm9
+[ ]*[a-f0-9]+:[ ]+c4 22 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm9,8\)/\(bad\),%xmm9/\(bad\)
-000000000000002a <avx512vgather>:
+[0-9a-f]+ <avx512vgather>:
[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 cd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 c5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 c5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm16,8\)/\(bad\),%zmm16\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 cd 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 c5 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 c5 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm16,8\)/\(bad\),%zmm16\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 cd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 c5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 c5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm16,8\)/\(bad\),%zmm16\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 cd 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 c5 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 c5 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm16,8\)/\(bad\),%ymm16\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 cd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 c5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 c5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm16,8\)/\(bad\),%zmm16\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 cd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 c5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 c5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm16,8\)/\(bad\),%zmm16\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 cd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm16,8\)/\(bad\),%ymm16\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 cd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 c5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 c5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm16,8\)/\(bad\),%zmm16\{%k1\}
[ ]+[a-f0-9]+:[ ]+62 e2 7d 21 91 84 cd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%ymm17,8\),%xmm16\{%k1\}
-[ ]+[a-f0-9]+:[ ]+62 e2 7d 21 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%ymm16,8\),%xmm16\{%k1\}
+[ ]+[a-f0-9]+:[ ]+62 e2 7d 21 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%ymm16,8\)/\(bad\),%xmm16\{%k1\}
#pass
--- a/gas/testsuite/gas/i386/x86-64-vgather-check.s
+++ b/gas/testsuite/gas/i386/x86-64-vgather-check.s
@@ -5,10 +5,13 @@ vgather:
vgatherdps %xmm2,(%rax,%xmm1,1),%xmm0
vgatherdps %xmm2,(%rax,%xmm1,2),%xmm2
vgatherdps %xmm2,(%rax,%xmm1,2),%xmm10
+ vgatherdps %xmm10,(%rax,%xmm1,2),%xmm10
vgatherdps %xmm1,(%rax,%xmm1,4),%xmm0
vgatherdps %xmm9,(%rax,%xmm1,4),%xmm0
+ vgatherdps %xmm9,(%rax,%xmm9,4),%xmm0
vgatherdps %xmm2,(%rax,%xmm1,8),%xmm1
vgatherdps %xmm2,(%rax,%xmm1,8),%xmm9
+ vgatherdps %xmm2,(%rax,%xmm9,8),%xmm9
avx512vgather:
vgatherdpd 123(%rbp,%ymm17,8), %zmm16{%k1}
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -455,9 +455,9 @@ static const struct dis386 evex_table[][
{ Bad_Opcode },
{ "vpshufbitqmb", { XMask, Vex, EXx }, PREFIX_DATA },
/* 90 */
- { "vpgatherd%DQ", { XM, MVexVSIBDWpX }, PREFIX_DATA },
+ { "vpgatherd%DQ", { XMGatherD, MVexVSIBDWpX }, PREFIX_DATA },
{ "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
- { "vgatherdp%XW", { XM, MVexVSIBDWpX}, PREFIX_DATA },
+ { "vgatherdp%XW", { XMGatherD, MVexVSIBDWpX }, PREFIX_DATA },
{ "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -345,6 +345,7 @@ fetch_data (struct disassemble_info *inf
#define MX { OP_MMX, 0 }
#define XM { OP_XMM, 0 }
#define XMScalar { OP_XMM, scalar_mode }
+#define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
#define XMM { OP_XMM, xmm_mode }
#define TMM { OP_XMM, tmm_mode }
@@ -390,6 +391,7 @@ fetch_data (struct disassemble_info *inf
#define VexW { OP_VexW, vex_mode }
#define VexScalar { OP_VEX, vex_scalar_mode }
#define VexScalarR { OP_VexR, vex_scalar_mode }
+#define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
#define VexGdq { OP_VEX, dq_mode }
#define VexTmm { OP_VEX, tmm_mode }
@@ -6309,9 +6311,9 @@ static const struct dis386 vex_table[][2
{ MOD_TABLE (MOD_VEX_0F388E) },
{ Bad_Opcode },
/* 90 */
- { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
+ { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
{ "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
- { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
+ { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
{ "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -9682,6 +9684,13 @@ print_insn (bfd_vma pc, disassemble_info
}
if (vex.zeroing)
oappend ("{z}");
+
+ /* S/G insns require a mask and don't allow
+ zeroing-masking. */
+ if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
+ || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
+ && (vex.mask_register_specifier == 0 || vex.zeroing))
+ oappend ("/(bad)");
}
}
}
@@ -11539,6 +11548,7 @@ OP_E_memory (int bytemode, int sizeflag)
|| bytemode == v_bndmk_mode
|| bytemode == bnd_mode
|| bytemode == bnd_swap_mode);
+ bfd_boolean check_gather = FALSE;
const char **indexes64 = names64;
const char **indexes32 = names32;
@@ -11564,6 +11574,7 @@ OP_E_memory (int bytemode, int sizeflag)
{
if (!vex.v)
vindex += 16;
+ check_gather = obufp == op_out[1];
}
haveindex = 1;
@@ -11600,8 +11611,10 @@ OP_E_memory (int bytemode, int sizeflag)
}
else
{
- /* mandatory non-vector SIB must have sib */
- if (bytemode == vex_sibmem_mode)
+ /* Check for mandatory SIB. */
+ if (bytemode == vex_vsib_d_w_dq_mode
+ || bytemode == vex_vsib_q_w_dq_mode
+ || bytemode == vex_sibmem_mode)
{
oappend ("(bad)");
return;
@@ -11754,6 +11767,19 @@ OP_E_memory (int bytemode, int sizeflag)
*obufp++ = close_char;
*obufp = '\0';
+
+ if (check_gather)
+ {
+ /* Both XMM/YMM/ZMM registers must be distinct. */
+ int modrm_reg = modrm.reg;
+
+ if (rex & REX_R)
+ modrm_reg += 8;
+ if (!vex.r)
+ modrm_reg += 16;
+ if (vindex == modrm_reg)
+ oappend ("/(bad)");
+ }
}
else if (intel_syntax)
{
@@ -11772,7 +11798,9 @@ OP_E_memory (int bytemode, int sizeflag)
else if (bytemode == v_bnd_mode
|| bytemode == v_bndmk_mode
|| bytemode == bnd_mode
- || bytemode == bnd_swap_mode)
+ || bytemode == bnd_swap_mode
+ || bytemode == vex_vsib_d_w_dq_mode
+ || bytemode == vex_vsib_q_w_dq_mode)
{
oappend ("(bad)");
return;
@@ -13308,7 +13336,7 @@ FXSAVE_Fixup (int bytemode, int sizeflag
static void
OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- int reg;
+ int reg, modrm_reg, sib_index = -1;
const char **names;
if (!need_vex)
@@ -13321,14 +13349,46 @@ OP_VEX (int bytemode, int sizeflag ATTRI
else if (vex.evex && !vex.v)
reg += 16;
- if (bytemode == vex_scalar_mode)
+ switch (bytemode)
{
+ case vex_scalar_mode:
oappend (names_xmm[reg]);
return;
- }
- if (bytemode == tmm_mode)
- {
+ case vex_vsib_d_w_dq_mode:
+ case vex_vsib_q_w_dq_mode:
+ /* This must be the 3rd operand. */
+ if (obufp != op_out[2])
+ abort ();
+ if (vex.length == 128
+ || (bytemode != vex_vsib_d_w_dq_mode
+ && !vex.w))
+ oappend (names_xmm[reg]);
+ else
+ oappend (names_ymm[reg]);
+
+ /* All 3 XMM/YMM registers must be distinct. */
+ modrm_reg = modrm.reg;
+ if (rex & REX_R)
+ modrm_reg += 8;
+
+ if (modrm.rm == 4)
+ {
+ sib_index = sib.index;
+ if (rex & REX_X)
+ sib_index += 8;
+ }
+
+ if (reg == modrm_reg || reg == sib_index)
+ strcpy (obufp, "/(bad)");
+ if (modrm_reg == sib_index || modrm_reg == reg)
+ strcat (op_out[0], "/(bad)");
+ if (sib_index == modrm_reg || sib_index == reg)
+ strcat (op_out[1], "/(bad)");
+
+ return;
+
+ case tmm_mode:
/* All 3 TMM registers must be distinct. */
if (reg >= 8)
oappend ("(bad)");
@@ -13361,7 +13421,6 @@ OP_VEX (int bytemode, int sizeflag ATTRI
switch (bytemode)
{
case vex_mode:
- case vex_vsib_q_w_dq_mode:
names = names_xmm;
break;
case dq_mode:
@@ -13390,9 +13449,6 @@ OP_VEX (int bytemode, int sizeflag ATTRI
case vex_mode:
names = names_ymm;
break;
- case vex_vsib_q_w_dq_mode:
- names = vex.w ? names_ymm : names_xmm;
- break;
case mask_bd_mode:
case mask_mode:
if (reg > 0x7)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/4] x86: assorted bug fixes
2021-03-24 9:21 [PATCH 0/4] x86: assorted bug fixes Jan Beulich
` (3 preceding siblings ...)
2021-03-24 9:24 ` [PATCH 4/4] x86: flag bad S/G insn operand combinations Jan Beulich
@ 2021-03-24 14:02 ` H.J. Lu
4 siblings, 0 replies; 6+ messages in thread
From: H.J. Lu @ 2021-03-24 14:02 UTC (permalink / raw)
To: Jan Beulich; +Cc: Binutils
On Wed, Mar 24, 2021 at 2:21 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> 1: limit breakage from gcc movdir64b et al workaround
> 2: fix AMD Zen3 insns
> 3: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear
> 4: flag bad S/G insn operand combinations
>
OK for all.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-03-24 14:03 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-24 9:21 [PATCH 0/4] x86: assorted bug fixes Jan Beulich
2021-03-24 9:22 ` [PATCH 1/4] x86-64: limit breakage from gcc movdir64b et al workaround Jan Beulich
2021-03-24 9:23 ` [PATCH 2/4] x86: fix AMD Zen3 insns Jan Beulich
2021-03-24 9:24 ` [PATCH 3/4] x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear Jan Beulich
2021-03-24 9:24 ` [PATCH 4/4] x86: flag bad S/G insn operand combinations Jan Beulich
2021-03-24 14:02 ` [PATCH 0/4] x86: assorted bug fixes H.J. Lu
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