From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 85F353858297; Tue, 4 Oct 2022 09:46:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 85F353858297 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id C9F41300089; Tue, 4 Oct 2022 09:46:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1664876781; bh=ORE6MwU/WXwXXj2EPipdnDlfxgTJztsz5Pf/z3YDIA8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=POfM9iTybEPw89soHB1sFlrhDKIBd+OGrvO2aU8GcDU4bShyX4eT3pGx2+6LAdUut jcg6Jksfxp95VOZWOtCwaWdsmaUpoAGs59CQkyErAfzO77ULNL0mKoOBu9ehQumKbV GTxO/aoSgVoWwFh1lgA9bmyRmZzKMZEGGyN3k4rw= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt , Andrew Burgess , Jan Beulich , Andreas Schwab Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v2 2/2] gdb/riscv: Partial support for instructions up to 176-bits Date: Tue, 4 Oct 2022 09:45:50 +0000 Message-Id: <4eb6e59ae2e790dbbf2bc92477edd281648d8814.1664876744.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,KAM_MANYTO,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Because riscv_insn_length started to support instructions up to 176-bit, we need to increase packet buffer size to 176-bit in size. Also, that would break an assumption in riscv_insn::decode so this commit fixes it. --- gdb/riscv-tdep.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 47d8f9e601b..433311e1024 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -1770,7 +1770,7 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr, int *len) { enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); - gdb_byte buf[8]; + gdb_byte buf[RISCV_MAX_INSN_LEN]; int instlen, status; /* All insns are at least 16 bits. */ @@ -1933,9 +1933,10 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) } else { - /* This must be a 6 or 8 byte instruction, we don't currently decode - any of these, so just ignore it. */ - gdb_assert (m_length == 6 || m_length == 8); + /* 6 - 22 bytes instruction. If the length is larger than 8, we don't + have full instruction bits in ival. At least, such long instructions + are not defined yet, so just ignore it. */ + gdb_assert (m_length > 0 && m_length % 2 == 0); m_opcode = OTHER; } } -- 2.34.1