From: "Jan Beulich" <JBeulich@suse.com>
To: <binutils@sourceware.org>
Subject: [PATCH] x86: don't allow invalid operand combinations for VGATHER
Date: Tue, 24 Jul 2012 14:19:00 -0000 [thread overview]
Message-ID: <500ECADF0200007800090386@nat28.tlf.novell.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 2841 bytes --]
The VGATHER group of instructions requires that all three involved
xmm/ymm registers are distinct. This patch adds code to check for this,
and at once eliminates a superfluous check for not using PC-relative
addressing for these instructions (the fact that an index register is
required here already excludes valid PC-relative addresses).
Note that this patch depends on the introduction of register_number(),
which is being done by the patch at
http://www.sourceware.org/ml/binutils/2012-07/msg00168.html.
2012-07-24 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (enum i386_error): New enumerator
'invalid_vector_register_set'.
(match_template): Handle it.
(check_VecOperands): Don't special case RIP addressing. Check
that vSIB operands use distinct vector registers.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -221,6 +221,7 @@ enum i386_error
unsupported_syntax,
unsupported,
invalid_vsib_address,
+ invalid_vector_register_set,
unsupported_vector_index_register
};
@@ -3958,18 +3959,32 @@ check_VecOperands (const insn_template *
return 1;
}
- /* For VSIB byte, we need a vector register for index and no PC
- relative addressing is allowed. */
- if (t->opcode_modifier.vecsib
- && (!i.index_reg
+ /* For VSIB byte, we need a vector register for index, and all vector
+ registers must be distinct. */
+ if (t->opcode_modifier.vecsib)
+ {
+ if (!i.index_reg
|| !((t->opcode_modifier.vecsib == VecSIB128
&& i.index_reg->reg_type.bitfield.regxmm)
|| (t->opcode_modifier.vecsib == VecSIB256
- && i.index_reg->reg_type.bitfield.regymm))
- || (i.base_reg && i.base_reg->reg_num == RegRip)))
- {
- i.error = invalid_vsib_address;
- return 1;
+ && i.index_reg->reg_type.bitfield.regymm)))
+ {
+ i.error = invalid_vsib_address;
+ return 1;
+ }
+
+ gas_assert (i.reg_operands == 2);
+ gas_assert (i.types[0].bitfield.regxmm
+ || i.types[0].bitfield.regymm);
+ gas_assert (i.types[2].bitfield.regxmm
+ || i.types[2].bitfield.regymm);
+ if (register_number (i.op[0].regs) == register_number (i.index_reg)
+ || register_number (i.op[2].regs) == register_number (i.index_reg)
+ || register_number (i.op[0].regs) == register_number (i.op[2].regs))
+ {
+ i.error = invalid_vector_register_set;
+ return 1;
+ }
}
return 0;
@@ -4365,6 +4380,9 @@ check_reverse:
case invalid_vsib_address:
err_msg = _("invalid VSIB address");
break;
+ case invalid_vector_register_set:
+ err_msg = _("mask, index, and destination registers must be distinct");
+ break;
case unsupported_vector_index_register:
err_msg = _("unsupported vector index register");
break;
[-- Attachment #2: binutils-mainline-x86-vgather-distinct-regs.patch --]
[-- Type: text/plain, Size: 2835 bytes --]
The VGATHER group of instructions requires that all three involved
xmm/ymm registers are distinct. This patch adds code to check for this,
and at once eliminates a superfluous check for not using PC-relative
addressing for these instructions (the fact that an index register is
required here already excludes valid PC-relative addresses).
Note that this patch depends on the introduction of register_number(),
which is being done by the patch at
http://www.sourceware.org/ml/binutils/2012-07/msg00168.html.
2012-07-24 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (enum i386_error): New enumerator
'invalid_vector_register_set'.
(match_template): Handle it.
(check_VecOperands): Don't special case RIP addressing. Check
that vSIB operands use distinct vector registers.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -221,6 +221,7 @@ enum i386_error
unsupported_syntax,
unsupported,
invalid_vsib_address,
+ invalid_vector_register_set,
unsupported_vector_index_register
};
@@ -3958,18 +3959,32 @@ check_VecOperands (const insn_template *
return 1;
}
- /* For VSIB byte, we need a vector register for index and no PC
- relative addressing is allowed. */
- if (t->opcode_modifier.vecsib
- && (!i.index_reg
+ /* For VSIB byte, we need a vector register for index, and all vector
+ registers must be distinct. */
+ if (t->opcode_modifier.vecsib)
+ {
+ if (!i.index_reg
|| !((t->opcode_modifier.vecsib == VecSIB128
&& i.index_reg->reg_type.bitfield.regxmm)
|| (t->opcode_modifier.vecsib == VecSIB256
- && i.index_reg->reg_type.bitfield.regymm))
- || (i.base_reg && i.base_reg->reg_num == RegRip)))
- {
- i.error = invalid_vsib_address;
- return 1;
+ && i.index_reg->reg_type.bitfield.regymm)))
+ {
+ i.error = invalid_vsib_address;
+ return 1;
+ }
+
+ gas_assert (i.reg_operands == 2);
+ gas_assert (i.types[0].bitfield.regxmm
+ || i.types[0].bitfield.regymm);
+ gas_assert (i.types[2].bitfield.regxmm
+ || i.types[2].bitfield.regymm);
+ if (register_number (i.op[0].regs) == register_number (i.index_reg)
+ || register_number (i.op[2].regs) == register_number (i.index_reg)
+ || register_number (i.op[0].regs) == register_number (i.op[2].regs))
+ {
+ i.error = invalid_vector_register_set;
+ return 1;
+ }
}
return 0;
@@ -4365,6 +4380,9 @@ check_reverse:
case invalid_vsib_address:
err_msg = _("invalid VSIB address");
break;
+ case invalid_vector_register_set:
+ err_msg = _("mask, index, and destination registers must be distinct");
+ break;
case unsupported_vector_index_register:
err_msg = _("unsupported vector index register");
break;
next reply other threads:[~2012-07-24 14:19 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-24 14:19 Jan Beulich [this message]
2012-07-30 16:10 ` H.J. Lu
2012-07-31 7:49 ` Jan Beulich
2012-07-31 15:44 ` H.J. Lu
2012-07-31 16:24 ` Jan Beulich
2012-08-07 10:32 ` [PATCH, v2] gas/x86: " Jan Beulich
2012-08-07 13:25 ` H.J. Lu
2012-08-07 13:44 ` Jan Beulich
2012-08-07 14:07 ` H.J. Lu
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