From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27661 invoked by alias); 24 Jul 2012 14:19:09 -0000 Received: (qmail 27650 invoked by uid 22791); 24 Jul 2012 14:19:07 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from nat28.tlf.novell.com (HELO nat28.tlf.novell.com) (130.57.49.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 24 Jul 2012 14:18:43 +0000 Received: from EMEA1-MTA by nat28.tlf.novell.com with Novell_GroupWise; Tue, 24 Jul 2012 15:18:42 +0100 Message-Id: <500ECADF0200007800090386@nat28.tlf.novell.com> Date: Tue, 24 Jul 2012 14:19:00 -0000 From: "Jan Beulich" To: Subject: [PATCH] x86: don't allow invalid operand combinations for VGATHER Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part370664AF.0__=" Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org X-SW-Source: 2012-07/txt/msg00169.txt.bz2 This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part370664AF.0__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Content-length: 2808 The VGATHER group of instructions requires that all three involved xmm/ymm registers are distinct. This patch adds code to check for this, and at once eliminates a superfluous check for not using PC-relative addressing for these instructions (the fact that an index register is required here already excludes valid PC-relative addresses). Note that this patch depends on the introduction of register_number(), which is being done by the patch at http://www.sourceware.org/ml/binutils/2012-07/msg00168.html. 2012-07-24 Jan Beulich * config/tc-i386.c (enum i386_error): New enumerator 'invalid_vector_register_set'. (match_template): Handle it. (check_VecOperands): Don't special case RIP addressing. Check that vSIB operands use distinct vector registers. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -221,6 +221,7 @@ enum i386_error unsupported_syntax, unsupported, invalid_vsib_address, + invalid_vector_register_set, unsupported_vector_index_register }; =20 @@ -3958,18 +3959,32 @@ check_VecOperands (const insn_template * return 1; } =20 - /* For VSIB byte, we need a vector register for index and no PC - relative addressing is allowed. */ - if (t->opcode_modifier.vecsib - && (!i.index_reg + /* For VSIB byte, we need a vector register for index, and all vector + registers must be distinct. */ + if (t->opcode_modifier.vecsib) + { + if (!i.index_reg || !((t->opcode_modifier.vecsib =3D=3D VecSIB128 && i.index_reg->reg_type.bitfield.regxmm) || (t->opcode_modifier.vecsib =3D=3D VecSIB256 - && i.index_reg->reg_type.bitfield.regymm)) - || (i.base_reg && i.base_reg->reg_num =3D=3D RegRip))) - { - i.error =3D invalid_vsib_address; - return 1; + && i.index_reg->reg_type.bitfield.regymm))) + { + i.error =3D invalid_vsib_address; + return 1; + } + + gas_assert (i.reg_operands =3D=3D 2); + gas_assert (i.types[0].bitfield.regxmm + || i.types[0].bitfield.regymm); + gas_assert (i.types[2].bitfield.regxmm + || i.types[2].bitfield.regymm); + if (register_number (i.op[0].regs) =3D=3D register_number (i.index_r= eg) + || register_number (i.op[2].regs) =3D=3D register_number (i.index_reg) + || register_number (i.op[0].regs) =3D=3D register_number (i.op[2].regs)) + { + i.error =3D invalid_vector_register_set; + return 1; + } } =20 return 0; @@ -4365,6 +4380,9 @@ check_reverse: case invalid_vsib_address: err_msg =3D _("invalid VSIB address"); break; + case invalid_vector_register_set: + err_msg =3D _("mask, index, and destination registers must be distinct"= ); + break; case unsupported_vector_index_register: err_msg =3D _("unsupported vector index register"); break; --=__Part370664AF.0__= Content-Type: text/plain; name="binutils-mainline-x86-vgather-distinct-regs.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="binutils-mainline-x86-vgather-distinct-regs.patch" Content-length: 2805 The VGATHER group of instructions requires that all three involved xmm/ymm registers are distinct. This patch adds code to check for this, and at once eliminates a superfluous check for not using PC-relative addressing for these instructions (the fact that an index register is required here already excludes valid PC-relative addresses). Note that this patch depends on the introduction of register_number(), which is being done by the patch at http://www.sourceware.org/ml/binutils/2012-07/msg00168.html. 2012-07-24 Jan Beulich * config/tc-i386.c (enum i386_error): New enumerator 'invalid_vector_register_set'. (match_template): Handle it. (check_VecOperands): Don't special case RIP addressing. Check that vSIB operands use distinct vector registers. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -221,6 +221,7 @@ enum i386_error unsupported_syntax, unsupported, invalid_vsib_address, + invalid_vector_register_set, unsupported_vector_index_register }; =20 @@ -3958,18 +3959,32 @@ check_VecOperands (const insn_template * return 1; } =20 - /* For VSIB byte, we need a vector register for index and no PC - relative addressing is allowed. */ - if (t->opcode_modifier.vecsib - && (!i.index_reg + /* For VSIB byte, we need a vector register for index, and all vector + registers must be distinct. */ + if (t->opcode_modifier.vecsib) + { + if (!i.index_reg || !((t->opcode_modifier.vecsib =3D=3D VecSIB128 && i.index_reg->reg_type.bitfield.regxmm) || (t->opcode_modifier.vecsib =3D=3D VecSIB256 - && i.index_reg->reg_type.bitfield.regymm)) - || (i.base_reg && i.base_reg->reg_num =3D=3D RegRip))) - { - i.error =3D invalid_vsib_address; - return 1; + && i.index_reg->reg_type.bitfield.regymm))) + { + i.error =3D invalid_vsib_address; + return 1; + } + + gas_assert (i.reg_operands =3D=3D 2); + gas_assert (i.types[0].bitfield.regxmm + || i.types[0].bitfield.regymm); + gas_assert (i.types[2].bitfield.regxmm + || i.types[2].bitfield.regymm); + if (register_number (i.op[0].regs) =3D=3D register_number (i.index_r= eg) + || register_number (i.op[2].regs) =3D=3D register_number (i.index_reg) + || register_number (i.op[0].regs) =3D=3D register_number (i.op[2].regs)) + { + i.error =3D invalid_vector_register_set; + return 1; + } } =20 return 0; @@ -4365,6 +4380,9 @@ check_reverse: case invalid_vsib_address: err_msg =3D _("invalid VSIB address"); break; + case invalid_vector_register_set: + err_msg =3D _("mask, index, and destination registers must be distinct"= ); + break; case unsupported_vector_index_register: err_msg =3D _("unsupported vector index register"); break; --=__Part370664AF.0__=--