* [PATCH] x86/Intel: relax requirements for memory operands
@ 2012-07-24 14:48 Jan Beulich
2012-07-30 15:59 ` H.J. Lu
2012-07-30 16:01 ` H.J. Lu
0 siblings, 2 replies; 6+ messages in thread
From: Jan Beulich @ 2012-07-24 14:48 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1503 bytes --]
MASM accepts ESP/RSP being specified second in a memory address
operand, by silently making it the base register despite not being
specified first.
Consequently, we also permit an xmm/ymm index to be specified first
(possibly alone), nevertheless putting it in as index register.
2012-07-24 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_simplify_register): Handle
xmm/ymm index register being specified first as well as esp/rsp
base register being specified last in a memory operand.
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -278,10 +278,24 @@ i386_intel_simplify_register (expression
}
i.op[this_operand].regs = i386_regtab + reg_num;
}
+ else if (!intel_state.index
+ && (i386_regtab[reg_num].reg_type.bitfield.regxmm
+ || i386_regtab[reg_num].reg_type.bitfield.regymm))
+ intel_state.index = i386_regtab + reg_num;
else if (!intel_state.base && !intel_state.in_scale)
intel_state.base = i386_regtab + reg_num;
else if (!intel_state.index)
- intel_state.index = i386_regtab + reg_num;
+ {
+ if (intel_state.in_scale
+ || i386_regtab[reg_num].reg_type.bitfield.baseindex)
+ intel_state.index = i386_regtab + reg_num;
+ else
+ {
+ /* Convert base to index and make ESP/RSP the base. */
+ intel_state.index = intel_state.base;
+ intel_state.base = i386_regtab + reg_num;
+ }
+ }
else
{
/* esp is invalid as index */
[-- Attachment #2: binutils-mainline-x86-intel-index-base.patch --]
[-- Type: text/plain, Size: 1497 bytes --]
MASM accepts ESP/RSP being specified second in a memory address
operand, by silently making it the base register despite not being
specified first.
Consequently, we also permit an xmm/ymm index to be specified first
(possibly alone), nevertheless putting it in as index register.
2012-07-24 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_simplify_register): Handle
xmm/ymm index register being specified first as well as esp/rsp
base register being specified last in a memory operand.
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -278,10 +278,24 @@ i386_intel_simplify_register (expression
}
i.op[this_operand].regs = i386_regtab + reg_num;
}
+ else if (!intel_state.index
+ && (i386_regtab[reg_num].reg_type.bitfield.regxmm
+ || i386_regtab[reg_num].reg_type.bitfield.regymm))
+ intel_state.index = i386_regtab + reg_num;
else if (!intel_state.base && !intel_state.in_scale)
intel_state.base = i386_regtab + reg_num;
else if (!intel_state.index)
- intel_state.index = i386_regtab + reg_num;
+ {
+ if (intel_state.in_scale
+ || i386_regtab[reg_num].reg_type.bitfield.baseindex)
+ intel_state.index = i386_regtab + reg_num;
+ else
+ {
+ /* Convert base to index and make ESP/RSP the base. */
+ intel_state.index = intel_state.base;
+ intel_state.base = i386_regtab + reg_num;
+ }
+ }
else
{
/* esp is invalid as index */
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] x86/Intel: relax requirements for memory operands
2012-07-24 14:48 [PATCH] x86/Intel: relax requirements for memory operands Jan Beulich
@ 2012-07-30 15:59 ` H.J. Lu
2012-07-31 6:28 ` Jan Beulich
2012-07-30 16:01 ` H.J. Lu
1 sibling, 1 reply; 6+ messages in thread
From: H.J. Lu @ 2012-07-30 15:59 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Tue, Jul 24, 2012 at 7:48 AM, Jan Beulich <JBeulich@suse.com> wrote:
> MASM accepts ESP/RSP being specified second in a memory address
> operand, by silently making it the base register despite not being
> specified first.
>
> Consequently, we also permit an xmm/ymm index to be specified first
> (possibly alone), nevertheless putting it in as index register.
>
> 2012-07-24 Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386-intel.c (i386_intel_simplify_register): Handle
> xmm/ymm index register being specified first as well as esp/rsp
> base register being specified last in a memory operand.
>
This caused:
FAIL: i386 inval-equ-2
on Linux/x86.
--
H.J.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] x86/Intel: relax requirements for memory operands
2012-07-24 14:48 [PATCH] x86/Intel: relax requirements for memory operands Jan Beulich
2012-07-30 15:59 ` H.J. Lu
@ 2012-07-30 16:01 ` H.J. Lu
2012-07-30 17:13 ` H.J. Lu
1 sibling, 1 reply; 6+ messages in thread
From: H.J. Lu @ 2012-07-30 16:01 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Tue, Jul 24, 2012 at 7:48 AM, Jan Beulich <JBeulich@suse.com> wrote:
> MASM accepts ESP/RSP being specified second in a memory address
> operand, by silently making it the base register despite not being
> specified first.
>
> Consequently, we also permit an xmm/ymm index to be specified first
> (possibly alone), nevertheless putting it in as index register.
>
> 2012-07-24 Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386-intel.c (i386_intel_simplify_register): Handle
> xmm/ymm index register being specified first as well as esp/rsp
> base register being specified last in a memory operand.
>
Please add a testcase for each change and fix
FAIL: i386 inval-equ-2
--
H.J.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] x86/Intel: relax requirements for memory operands
2012-07-30 16:01 ` H.J. Lu
@ 2012-07-30 17:13 ` H.J. Lu
0 siblings, 0 replies; 6+ messages in thread
From: H.J. Lu @ 2012-07-30 17:13 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Mon, Jul 30, 2012 at 9:00 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Tue, Jul 24, 2012 at 7:48 AM, Jan Beulich <JBeulich@suse.com> wrote:
>> MASM accepts ESP/RSP being specified second in a memory address
>> operand, by silently making it the base register despite not being
>> specified first.
>>
>> Consequently, we also permit an xmm/ymm index to be specified first
>> (possibly alone), nevertheless putting it in as index register.
>>
>> 2012-07-24 Jan Beulich <jbeulich@suse.com>
>>
>> * config/tc-i386-intel.c (i386_intel_simplify_register): Handle
>> xmm/ymm index register being specified first as well as esp/rsp
>> base register being specified last in a memory operand.
>>
>
> Please add a testcase for each change and fix
>
> FAIL: i386 inval-equ-2
>
It was caused by a different patch. I checked in this
to fix it.
--
H.J.
--
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 85968f8..caa3ccb 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2012-07-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/inval-equ-2.l: Updated.
+
2012-07-24 Sandra Loosemore <sandra@codesourcery.com>
Jie Zhang <jzhang918@gmail.com>
diff --git a/gas/testsuite/gas/i386/inval-equ-2.l
b/gas/testsuite/gas/i386/inval-equ-2.l
index aed89b4..7a4f483 100644
--- a/gas/testsuite/gas/i386/inval-equ-2.l
+++ b/gas/testsuite/gas/i386/inval-equ-2.l
@@ -15,5 +15,7 @@ GAS LISTING .*
[ ]*6[ ]+\.globl bar2
[ ]*7[ ]+\.set bar3,\(%eax\+1\)
[ ]*8[ ]+\?\?\?\? A12A0000 mov bar3,%eax
+\*\*\*\* Error:can't make global register symbol `bar1'
+\*\*\*\* Error:can't make global register symbol `bar2'
\*\*\*\* Error:can't make global register symbol `bar3'
[ ]*8[ ]+00
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] x86/Intel: relax requirements for memory operands
2012-07-30 15:59 ` H.J. Lu
@ 2012-07-31 6:28 ` Jan Beulich
2012-07-31 15:48 ` H.J. Lu
0 siblings, 1 reply; 6+ messages in thread
From: Jan Beulich @ 2012-07-31 6:28 UTC (permalink / raw)
To: H.J. Lu; +Cc: binutils
>>> On 30.07.12 at 17:59, "H.J. Lu" <hjl.tools@gmail.com> wrote:
> On Tue, Jul 24, 2012 at 7:48 AM, Jan Beulich <JBeulich@suse.com> wrote:
>> MASM accepts ESP/RSP being specified second in a memory address
>> operand, by silently making it the base register despite not being
>> specified first.
>>
>> Consequently, we also permit an xmm/ymm index to be specified first
>> (possibly alone), nevertheless putting it in as index register.
>>
>> 2012-07-24 Jan Beulich <jbeulich@suse.com>
>>
>> * config/tc-i386-intel.c (i386_intel_simplify_register): Handle
>> xmm/ymm index register being specified first as well as esp/rsp
>> base register being specified last in a memory operand.
>>
>
> This caused:
>
> FAIL: i386 inval-equ-2
>
> on Linux/x86.
No for me, neither on 32- nor on 64-bit host. I also don't see
how it could - the test case doesn't use Intel syntax, so is
entirely unaffected by this change. Consequently I have no
way of fixing this. Please double check that the failure is really
caused by this change.
Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] x86/Intel: relax requirements for memory operands
2012-07-31 6:28 ` Jan Beulich
@ 2012-07-31 15:48 ` H.J. Lu
0 siblings, 0 replies; 6+ messages in thread
From: H.J. Lu @ 2012-07-31 15:48 UTC (permalink / raw)
To: Jan Beulich; +Cc: binutils
On Mon, Jul 30, 2012 at 11:29 PM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 30.07.12 at 17:59, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> On Tue, Jul 24, 2012 at 7:48 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>> MASM accepts ESP/RSP being specified second in a memory address
>>> operand, by silently making it the base register despite not being
>>> specified first.
>>>
>>> Consequently, we also permit an xmm/ymm index to be specified first
>>> (possibly alone), nevertheless putting it in as index register.
>>>
>>> 2012-07-24 Jan Beulich <jbeulich@suse.com>
>>>
>>> * config/tc-i386-intel.c (i386_intel_simplify_register): Handle
>>> xmm/ymm index register being specified first as well as esp/rsp
>>> base register being specified last in a memory operand.
>>>
>>
>> This caused:
>>
>> FAIL: i386 inval-equ-2
>>
>> on Linux/x86.
>
> No for me, neither on 32- nor on 64-bit host. I also don't see
> how it could - the test case doesn't use Intel syntax, so is
> entirely unaffected by this change. Consequently I have no
> way of fixing this. Please double check that the failure is really
> caused by this change.
>
I have checked in a fix. Please add some testcases to
verify each of your changes.
Thanks.
--
H.J.
^ permalink raw reply [flat|nested] 6+ messages in thread
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2012-07-24 14:48 [PATCH] x86/Intel: relax requirements for memory operands Jan Beulich
2012-07-30 15:59 ` H.J. Lu
2012-07-31 6:28 ` Jan Beulich
2012-07-31 15:48 ` H.J. Lu
2012-07-30 16:01 ` H.J. Lu
2012-07-30 17:13 ` H.J. Lu
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