* [RFA/ARM 01/21] Add command line and object file support for ARMv8-A
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
@ 2012-08-23 14:55 ` Matthew Gretton-Dann
2012-08-23 16:28 ` Richard Earnshaw
2012-08-23 14:56 ` [RFA/ARM 03/21] Warn on deprecated Co-processor register accesses Matthew Gretton-Dann
` (19 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 14:55 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 3448 bytes --]
This patch adds the basic infrastructure to support ARMv8 A32/T32
instruction sets in binutils. It also contains the necessary changes to
output the correct attributes.
A new architecture is added: -march=armv8-a.
New architecture extensions are added:
+crypto (Crypto extensions implies +fp+simd)
+fp (FP)
+simd (Advanced SIMD Extensions implies +fp)
We also update the attributes emitted by the tools to support these new
features.
The ABI adds new values to Tag_CPU_arch, Tag_FP_arch, and
Tag_Advanced_SIMD_arch for ARMv8. It also changes the meaning of
Tag_FP_HP_extension so that for VFPv4/SIMDv2 the appropriate value is
now 0 instead of 1.
OK?
bfd/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* elf32-arm.c (v8): New array.
(tag_cpu_arch_combine): Add support for ARMv8 attributes.
(elf32_arm_merge_eabi_attributes): Likewise.
(VFP_VERSION_COUNT): New define.
binutils/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* readelf.c (arm_attr_tag_CPU_arch): Update for ARMv8.
(arm_attr_tag_FP_arch): Likewise.
(arm_attr_tag_Advanced_SIMD_arch): Likewise.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.h (arm_ext_v8): New variable.
(fpu_vfp_ext_armv8): Likewise.
(fpu_neon_ext_armv8): Likewise.
(fpu_crypto_ext_armv8): Likewise.
(arm_archs): Add armv8-a.
(arm_extensions): Add crypto, fp, and simd.
(arm_fpus): Add fp-armv8, neon-fp-armv8, crypto-neon-fp-armv8.
(cpu_arch_ver): Add support for ARMv8.
(aeabi_set_public_sttributes): Likewise.
* doc/c-arm.texi (ARM Options): Document new architecture and
extension options for ARMv8.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/attr-march-all.d: Update for change in expected
output.
* gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
* gas/arm/attr-mfpu-vfpv4.d: Likewise.
* gas/arm/attr-march-armv8-a+crypto.d: New testcase.
* gas/arm/attr-march-armv8-a+fp.d: Likewise.
* gas/arm/attr-march-armv8-a+simd.d: Likewise.
* gas/arm/attr-march-armv8-a.d: Likewise.
include/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* elf/arm.h (TAG_CPU_ARCH_V8): New define.
(MAX_TAG_CPU_ARCH): Update.
* opcode/arm.h (ARM_EXT_V8): New define.
(FPU_VFP_EXT_ARMV8): Likewise.
(FPU_NEON_EXT_ARMV8): Likewise.
(FPU_CRYPTO_EXT_ARMV8): Likewise.
(ARM_AEXT_V8A): Likewise.
(FPU_VFP_ARMV8): Likwise.
(FPU_NEON_ARMV8): Likewise.
(FPU_CRYPTO_ARMV8): Likewise.
(FPU_ARCH_VFP_ARMV8): Likewise.
(FPU_ARCH_NEON_VFP_ARMV8): Likewise.
(FPU_ARCH_CRYPTO_NEON_VFP_ARMV8): Likewise.
(ARM_ARCH_V8A): Likwise.
(ARM_ARCH_V8A_FP): Likewise.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTO): Likewise.
ld/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* ld-arm/arm-elf.exp: Add new testcases.
* ld-arm/attr-merge-vfp-3.d: Update for change in expected
output.
* ld-arm/attr-merge-vfp-3r.d: Likewise.
* ld-arm/attr-merge-vfp-4.d: Likewise.
* ld-arm/attr-merge-vfp-4r.d: Likewise.
* ld-arm/attr-merge-vfp-5.d: Likewise.
* ld-arm/attr-merge-vfp-5r.d: Likewise.
* ld-arm/attr-merge-vfp-7.d: New testcase.
* ld-arm/attr-merge-vfp-7r.d: Likewise.
* ld-arm/attr-merge-vfp-armv8-hard.s: Likewise.
* ld-arm/attr-merge-vfp-armv8.s: Likewise.
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[-- Type: text/x-patch, Size: 26536 bytes --]
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 4f2d00e..a287fbb 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -11327,6 +11327,24 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
T(V7E_M), /* V6S_M. */
T(V7E_M) /* V7E_M. */
};
+ const int v8[] =
+ {
+ T(V8), /* PRE_V4. */
+ T(V8), /* V4. */
+ T(V8), /* V4T. */
+ T(V8), /* V5T. */
+ T(V8), /* V5TE. */
+ T(V8), /* V5TEJ. */
+ T(V8), /* V6. */
+ T(V8), /* V6KZ. */
+ T(V8), /* V6T2. */
+ T(V8), /* V6K. */
+ T(V8), /* V7. */
+ T(V8), /* V6_M. */
+ T(V8), /* V6S_M. */
+ T(V8), /* V7E_M. */
+ T(V8) /* V8. */
+ };
const int v4t_plus_v6_m[] =
{
-1, /* PRE_V4. */
@@ -11343,6 +11361,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
T(V6_M), /* V6_M. */
T(V6S_M), /* V6S_M. */
T(V7E_M), /* V7E_M. */
+ T(V8), /* V8. */
T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
};
const int *comb[] =
@@ -11353,6 +11372,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
v6_m,
v6s_m,
v7e_m,
+ v8,
/* Pseudo-architecture. */
v4t_plus_v6_m
};
@@ -11554,7 +11574,8 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
"ARM v6K",
"ARM v7",
"ARM v6-M",
- "ARM v6S-M"
+ "ARM v6S-M",
+ "ARM v8"
};
/* Merge Tag_CPU_arch and Tag_also_compatible_with. */
@@ -11699,11 +11720,12 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
when it's 0. It might mean absence of FP hardware if
Tag_FP_arch is zero, otherwise it is effectively SP + DP. */
+#define VFP_VERSION_COUNT 8
static const struct
{
int ver;
int regs;
- } vfp_versions[7] =
+ } vfp_versions[VFP_VERSION_COUNT] =
{
{0, 0},
{1, 16},
@@ -11711,7 +11733,8 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
{3, 32},
{3, 16},
{4, 32},
- {4, 16}
+ {4, 16},
+ {8, 32}
};
int ver;
int regs;
@@ -11751,9 +11774,10 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
/* Now we can handle Tag_FP_arch. */
- /* Values greater than 6 aren't defined, so just pick the
- biggest */
- if (in_attr[i].i > 6 && in_attr[i].i > out_attr[i].i)
+ /* Values of VFP_VERSION_COUNT or more aren't defined, so just
+ pick the biggest. */
+ if (in_attr[i].i >= VFP_VERSION_COUNT
+ && in_attr[i].i > out_attr[i].i)
{
out_attr[i] = in_attr[i];
break;
@@ -11768,7 +11792,7 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
regs = vfp_versions[out_attr[i].i].regs;
/* This assumes all possible supersets are also a valid
options. */
- for (newval = 6; newval > 0; newval--)
+ for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
{
if (regs == vfp_versions[newval].regs
&& ver == vfp_versions[newval].ver)
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 5423c7f..89cff24 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -10868,15 +10868,16 @@ typedef struct
static const char * arm_attr_tag_CPU_arch[] =
{"Pre-v4", "v4", "v4T", "v5T", "v5TE", "v5TEJ", "v6", "v6KZ", "v6T2",
- "v6K", "v7", "v6-M", "v6S-M", "v7E-M"};
+ "v6K", "v7", "v6-M", "v6S-M", "v7E-M", "v8"};
static const char * arm_attr_tag_ARM_ISA_use[] = {"No", "Yes"};
static const char * arm_attr_tag_THUMB_ISA_use[] =
{"No", "Thumb-1", "Thumb-2"};
static const char * arm_attr_tag_FP_arch[] =
- {"No", "VFPv1", "VFPv2", "VFPv3", "VFPv3-D16", "VFPv4", "VFPv4-D16"};
+ {"No", "VFPv1", "VFPv2", "VFPv3", "VFPv3-D16", "VFPv4", "VFPv4-D16",
+ "FP for ARMv8"};
static const char * arm_attr_tag_WMMX_arch[] = {"No", "WMMXv1", "WMMXv2"};
static const char * arm_attr_tag_Advanced_SIMD_arch[] =
- {"No", "NEONv1", "NEONv1 with Fused-MAC"};
+ {"No", "NEONv1", "NEONv1 with Fused-MAC", "NEON for ARMv8"};
static const char * arm_attr_tag_PCS_config[] =
{"None", "Bare platform", "Linux application", "Linux DSO", "PalmOS 2004",
"PalmOS (reserved)", "SymbianOS 2004", "SymbianOS (reserved)"};
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 795a1b5..101f86b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -195,6 +195,7 @@ static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
+static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
static const arm_feature_set arm_ext_m =
ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
@@ -233,6 +234,12 @@ static const arm_feature_set fpu_vfp_v3_or_neon_ext =
static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
+static const arm_feature_set fpu_vfp_ext_armv8 =
+ ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
+static const arm_feature_set fpu_neon_ext_armv8 =
+ ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
+static const arm_feature_set fpu_crypto_ext_armv8 =
+ ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
static int mfloat_abi_opt = -1;
/* Record user cpu selection for object attributes. */
@@ -23188,6 +23195,7 @@ static const struct arm_arch_option_table arm_archs[] =
ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
+ ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
@@ -23209,6 +23217,10 @@ struct arm_option_extension_value_table
#define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
static const struct arm_option_extension_value_table arm_extensions[] =
{
+ ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+ ARM_FEATURE (ARM_EXT_V8, 0)),
+ ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
+ ARM_FEATURE (ARM_EXT_V8, 0)),
ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
@@ -23218,6 +23230,8 @@ static const struct arm_option_extension_value_table arm_extensions[] =
ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
+ ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
+ ARM_FEATURE (ARM_EXT_V8, 0)),
ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
ARM_FEATURE (ARM_EXT_V6M, 0)),
ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
@@ -23275,6 +23289,10 @@ static const struct arm_option_fpu_value_table arm_fpus[] =
{"vfpv4-d16", FPU_ARCH_VFP_V4D16},
{"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
{"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
+ {"fp-armv8", FPU_ARCH_VFP_ARMV8},
+ {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
+ {"crypto-neon-fp-armv8",
+ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
{NULL, ARM_ARCH_NONE}
};
@@ -23749,9 +23767,10 @@ static const cpu_arch_ver_table cpu_arch_ver[] =
{11, ARM_ARCH_V6M},
{12, ARM_ARCH_V6SM},
{8, ARM_ARCH_V6T2},
- {10, ARM_ARCH_V7A},
+ {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
{10, ARM_ARCH_V7R},
{10, ARM_ARCH_V7M},
+ {14, ARM_ARCH_V8A},
{0, ARM_ARCH_NONE}
};
@@ -23781,6 +23800,7 @@ aeabi_set_public_attributes (void)
int arch;
char profile;
int virt_sec = 0;
+ int fp16_optional = 0;
arm_feature_set flags;
arm_feature_set tmp;
const cpu_arch_ver_table *p;
@@ -23880,14 +23900,22 @@ aeabi_set_public_attributes (void)
ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
/* Tag_VFP_arch. */
- if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
+ if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
+ aeabi_set_attribute_int (Tag_VFP_arch, 7);
+ else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
aeabi_set_attribute_int (Tag_VFP_arch,
ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
? 5 : 6);
else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
- aeabi_set_attribute_int (Tag_VFP_arch, 3);
+ {
+ fp16_optional = 1;
+ aeabi_set_attribute_int (Tag_VFP_arch, 3);
+ }
else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
- aeabi_set_attribute_int (Tag_VFP_arch, 4);
+ {
+ aeabi_set_attribute_int (Tag_VFP_arch, 4);
+ fp16_optional = 1;
+ }
else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
aeabi_set_attribute_int (Tag_VFP_arch, 2);
else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
@@ -23906,13 +23934,23 @@ aeabi_set_public_attributes (void)
aeabi_set_attribute_int (Tag_WMMX_arch, 1);
/* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
- if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
- aeabi_set_attribute_int
- (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
- ? 2 : 1));
+ if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
+ aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
+ else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
+ {
+ if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
+ {
+ aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
+ }
+ else
+ {
+ aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
+ fp16_optional = 1;
+ }
+ }
/* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
- if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
+ if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
/* Tag_DIV_use.
@@ -23921,12 +23959,17 @@ aeabi_set_public_attributes (void)
in ARM state, or when Thumb integer divide instructions have been used,
but we have no architecture profile set, nor have we any ARM instructions.
+ For ARMv8 we set the tag to 0 as integer divide is implied by the base
+ architecture.
+
For new architectures we will have to check these tests. */
- gas_assert (arch <= TAG_CPU_ARCH_V7E_M);
- if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
- || (profile == '\0'
- && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
- && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
+ gas_assert (arch <= TAG_CPU_ARCH_V8);
+ if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
+ aeabi_set_attribute_int (Tag_DIV_use, 0);
+ else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
+ || (profile == '\0'
+ && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
+ && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
aeabi_set_attribute_int (Tag_DIV_use, 2);
/* Tag_MP_extension_use. */
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index ae6c488..7d622ef 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -154,13 +154,16 @@ been added, again in ascending alphabetical order. For example,
The following extensions are currently supported:
-@code{idiv}, (Integer Divide Extensions for v7-A and v7-R architectures),
+@code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
+@code{fp} (Floating Point Extensions for v8-A architecture),
+@code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
@code{iwmmxt},
@code{iwmmxt2},
@code{maverick},
@code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
@code{os} (Operating System for v6M architecture),
@code{sec} (Security Extensions for v6K and v7-A architectures),
+@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
@code{virt} (Virtualization Extensions for v7-A architecture, implies
@code{idiv}),
and
@@ -199,6 +202,7 @@ names are recognized:
@code{armv7-r},
@code{armv7-m},
@code{armv7e-m},
+@code{armv8-a},
@code{iwmmxt}
and
@code{xscale}.
@@ -241,13 +245,16 @@ The following format options are recognized:
@code{vfpv4},
@code{vfpv4-d16},
@code{fpv4-sp-d16},
+@code{fp-armv8},
@code{arm1020t},
@code{arm1020e},
@code{arm1136jf-s},
@code{maverick},
@code{neon},
+@code{neon-vfpv4},
+@code{neon-fp-armv8},
and
-@code{neon-vfpv4}.
+@code{crypto-neon-fp-armv8}.
In addition to determining which instructions are assembled, this option
also affects the way in which the @code{.double} assembler directive behaves
diff --git a/gas/testsuite/gas/arm/attr-march-all.d b/gas/testsuite/gas/arm/attr-march-all.d
index ed4d652..4a80d2f 100644
--- a/gas/testsuite/gas/arm/attr-march-all.d
+++ b/gas/testsuite/gas/arm/attr-march-all.d
@@ -8,10 +8,9 @@
Attribute Section: aeabi
File Attributes
Tag_CPU_name: "all"
- Tag_CPU_arch: v7
+ Tag_CPU_arch: v8
Tag_CPU_arch_profile: Application
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-2
Tag_MPextension_use: Allowed
- Tag_DIV_use: Allowed in v7-A with integer division extension
Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d b/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d
new file mode 100644
index 0000000..f1d9cf4
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d
@@ -0,0 +1,18 @@
+# name: attributes for -march=armv8-a+crypto
+# source: blank.s
+# as: -march=armv8-a+crypto
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "8-A"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d b/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d
new file mode 100644
index 0000000..54d472f
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d
@@ -0,0 +1,17 @@
+# name: attributes for -march=armv8-a+fp
+# source: blank.s
+# as: -march=armv8-a+fp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "8-A"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d b/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d
new file mode 100644
index 0000000..e8e6af9
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d
@@ -0,0 +1,18 @@
+# name: attributes for -march=armv8-a+simd
+# source: blank.s
+# as: -march=armv8-a+simd
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "8-A"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_FP_arch: FP for ARMv8
+ Tag_Advanced_SIMD_arch: NEON for ARMv8
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-march-armv8-a.d b/gas/testsuite/gas/arm/attr-march-armv8-a.d
new file mode 100644
index 0000000..d02bc65
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-march-armv8-a.d
@@ -0,0 +1,16 @@
+# name: attributes for -march=armv8-a
+# source: blank.s
+# as: -march=armv8-a
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "8-A"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Application
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d b/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d
index 1b0e297..fd71a93 100644
--- a/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d
+++ b/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d
@@ -10,4 +10,3 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_FP_arch: VFPv4-D16
- Tag_FP_HP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d b/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d
index 1be3048..2a3edf7 100644
--- a/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d
+++ b/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d
@@ -10,4 +10,3 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_FP_arch: VFPv4
- Tag_FP_HP_extension: Allowed
diff --git a/include/elf/arm.h b/include/elf/arm.h
index 860fdf7..8ea3fe8 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -101,7 +101,8 @@
#define TAG_CPU_ARCH_V6_M 11
#define TAG_CPU_ARCH_V6S_M 12
#define TAG_CPU_ARCH_V7E_M 13
-#define MAX_TAG_CPU_ARCH 13
+#define TAG_CPU_ARCH_V8 14
+#define MAX_TAG_CPU_ARCH 14
/* Pseudo-architecture to allow objects to be compatible with the subset of
armv4t and armv6-m. This value should never be stored in object files. */
#define TAG_CPU_ARCH_V4T_PLUS_V6_M (MAX_TAG_CPU_ARCH + 1)
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 86e3d67..1c350c8 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -34,6 +34,7 @@
#define ARM_EXT_V6 0x00001000 /* ARM V6. */
#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
/* 0x00004000 Was ARM V6Z. */
+#define ARM_EXT_V8 0x00004000 /* is now ARMv8. */
#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
#define ARM_EXT_DIV 0x00010000 /* Integer division. */
/* The 'M' in Arm V7M stands for Microcontroller.
@@ -77,6 +78,9 @@
#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */
#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */
#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */
+#define FPU_VFP_EXT_ARMV8 0x00020000 /* FP for ARMv8. */
+#define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */
+#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */
/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
@@ -126,6 +130,9 @@
#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
#define ARM_AEXT_V7EM \
(ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP)
+#define ARM_AEXT_V8A \
+ (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \
+ | ARM_EXT_VIRT | ARM_EXT_V8)
/* Processors with specific extensions in the co-processor space. */
#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
@@ -143,6 +150,9 @@
#define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
+#define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8)
+#define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8)
+#define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8)
#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
| FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \
| FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
@@ -175,6 +185,10 @@
#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16)
#define FPU_ARCH_NEON_VFP_V4 \
ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)
+#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8)
+#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE(0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
+#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
+ ARM_FEATURE(0, FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
@@ -211,6 +225,7 @@
#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0)
#define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0)
+#define ARM_ARCH_V8A ARM_FEATURE (ARM_AEXT_V8A, 0)
/* Some useful combinations: */
#define ARM_ARCH_NONE ARM_FEATURE (0, 0)
@@ -233,6 +248,14 @@
#define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0)
/* Features that are present in v6M and v6S-M but not other v6 cores. */
#define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0)
+/* v8-a+fp. */
+#define ARM_ARCH_V8A_FP ARM_FEATURE (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8)
+/* v8-a+simd (implies fp). */
+#define ARM_ARCH_V8A_SIMD ARM_FEATURE (ARM_AEXT_V8A, \
+ FPU_ARCH_NEON_VFP_ARMV8)
+/* v8-a+crypto (implies simd+fp). */
+#define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, \
+ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8)
/* There are too many feature bits to fit in a single word, so use a
structure. For simplicity we put all core features in one word and
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 3f2bf92..8e15ffe 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -767,6 +767,8 @@ run_dump_test "attr-merge-vfp-5"
run_dump_test "attr-merge-vfp-5r"
run_dump_test "attr-merge-vfp-6"
run_dump_test "attr-merge-vfp-6r"
+run_dump_test "attr-merge-vfp-7"
+run_dump_test "attr-merge-vfp-7r"
run_dump_test "attr-merge-incompatible"
run_dump_test "unresolved-1"
if { ![istarget "arm*-*-nacl*"] } {
diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-3.d b/ld/testsuite/ld-arm/attr-merge-vfp-3.d
index ee89384..8f9d2e7 100644
--- a/ld/testsuite/ld-arm/attr-merge-vfp-3.d
+++ b/ld/testsuite/ld-arm/attr-merge-vfp-3.d
@@ -11,4 +11,3 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_FP_arch: VFPv4-D16
- Tag_FP_HP_extension: Allowed
diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-3r.d b/ld/testsuite/ld-arm/attr-merge-vfp-3r.d
index d06bd27..ab0ff33 100644
--- a/ld/testsuite/ld-arm/attr-merge-vfp-3r.d
+++ b/ld/testsuite/ld-arm/attr-merge-vfp-3r.d
@@ -11,4 +11,3 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_FP_arch: VFPv4-D16
- Tag_FP_HP_extension: Allowed
diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-4.d b/ld/testsuite/ld-arm/attr-merge-vfp-4.d
index c18d672..e51a41b 100644
--- a/ld/testsuite/ld-arm/attr-merge-vfp-4.d
+++ b/ld/testsuite/ld-arm/attr-merge-vfp-4.d
@@ -11,4 +11,3 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_FP_arch: VFPv4
- Tag_FP_HP_extension: Allowed
diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-4r.d b/ld/testsuite/ld-arm/attr-merge-vfp-4r.d
index 327e0c3..6d19a60 100644
--- a/ld/testsuite/ld-arm/attr-merge-vfp-4r.d
+++ b/ld/testsuite/ld-arm/attr-merge-vfp-4r.d
@@ -11,4 +11,3 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_FP_arch: VFPv4
- Tag_FP_HP_extension: Allowed
diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-5.d b/ld/testsuite/ld-arm/attr-merge-vfp-5.d
index cd55a86..650b264 100644
--- a/ld/testsuite/ld-arm/attr-merge-vfp-5.d
+++ b/ld/testsuite/ld-arm/attr-merge-vfp-5.d
@@ -11,4 +11,3 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_FP_arch: VFPv4
- Tag_FP_HP_extension: Allowed
diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-5r.d b/ld/testsuite/ld-arm/attr-merge-vfp-5r.d
index 505c31b..f5fb7d7 100644
--- a/ld/testsuite/ld-arm/attr-merge-vfp-5r.d
+++ b/ld/testsuite/ld-arm/attr-merge-vfp-5r.d
@@ -11,4 +11,3 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-1
Tag_FP_arch: VFPv4
- Tag_FP_HP_extension: Allowed
diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-7.d b/ld/testsuite/ld-arm/attr-merge-vfp-7.d
new file mode 100644
index 0000000..6b1f9c9
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-vfp-7.d
@@ -0,0 +1,14 @@
+#source: attr-merge-vfp-armv8.s
+#source: attr-merge-vfp-armv8-hard.s
+#as:
+#ld: -r
+#readelf: -A
+# This test is only valid on ELF based ports.
+# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-1
+ Tag_FP_arch: FP for ARMv8
+ Tag_ABI_HardFP_use: SP and DP
diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-7r.d b/ld/testsuite/ld-arm/attr-merge-vfp-7r.d
new file mode 100644
index 0000000..6b1f9c9
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-vfp-7r.d
@@ -0,0 +1,14 @@
+#source: attr-merge-vfp-armv8.s
+#source: attr-merge-vfp-armv8-hard.s
+#as:
+#ld: -r
+#readelf: -A
+# This test is only valid on ELF based ports.
+# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-1
+ Tag_FP_arch: FP for ARMv8
+ Tag_ABI_HardFP_use: SP and DP
diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-armv8-hard.s b/ld/testsuite/ld-arm/attr-merge-vfp-armv8-hard.s
new file mode 100644
index 0000000..6457974
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-vfp-armv8-hard.s
@@ -0,0 +1,2 @@
+.fpu fp-armv8
+.eabi_attribute Tag_ABI_HardFP_use, 3
diff --git a/ld/testsuite/ld-arm/attr-merge-vfp-armv8.s b/ld/testsuite/ld-arm/attr-merge-vfp-armv8.s
new file mode 100644
index 0000000..a7679cd
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-vfp-armv8.s
@@ -0,0 +1,2 @@
+.fpu fp-armv8
+
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 03/21] Warn on deprecated Co-processor register accesses
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
2012-08-23 14:55 ` [RFA/ARM 01/21] Add command line and object file support for ARMv8-A Matthew Gretton-Dann
@ 2012-08-23 14:56 ` Matthew Gretton-Dann
2012-08-23 16:30 ` Richard Earnshaw
2012-08-23 14:56 ` [RFA/ARM 02/21] Mark SWP as obsolete Matthew Gretton-Dann
` (18 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 14:56 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 623 bytes --]
ARMv8 deprecates some cp15 and cp14 coprocessor register accesses.
This patch causes the assembler to warn when these registers are
accessed.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (deprecated_coproc_regs_s): New structure.
(deprecated_coproc_regs): New variable.
(deprecated_coproc_reg_count): Likewise.
(do_co_reg): Error on obsolete & warn on deprecated registers.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a-bad.l: Update testcase.
* gas/arm/armv8-a-bad.s: Likewise.
[-- Attachment #2: 0003-Warn-on-deprecated-Co-processor-register-accesses.txt --]
[-- Type: text/x-patch, Size: 3479 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index af4a1e5..02e843d 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7710,10 +7710,52 @@ do_cmp (void)
No special properties. */
+struct deprecated_coproc_regs_s
+{
+ unsigned cp;
+ int opc1;
+ unsigned crn;
+ unsigned crm;
+ int opc2;
+ arm_feature_set deprecated;
+ arm_feature_set obsoleted;
+ const char *dep_msg;
+ const char *obs_msg;
+};
+
+#define DEPR_ACCESS_V8 \
+ N_("This coprocessor register access is deprecated in ARMv8")
+
+/* Table of all deprecated coprocessor registers. */
+static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
+{
+ {15, 0, 7, 10, 5, /* CP15DMB. */
+ ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
+ DEPR_ACCESS_V8, NULL},
+ {15, 0, 7, 10, 4, /* CP15DSB. */
+ ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
+ DEPR_ACCESS_V8, NULL},
+ {15, 0, 7, 5, 4, /* CP15ISB. */
+ ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
+ DEPR_ACCESS_V8, NULL},
+ {14, 6, 1, 0, 0, /* TEEHBR. */
+ ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
+ DEPR_ACCESS_V8, NULL},
+ {14, 6, 0, 0, 0, /* TEECR. */
+ ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
+ DEPR_ACCESS_V8, NULL},
+};
+
+#undef DEPR_ACCESS_V8
+
+static const size_t deprecated_coproc_reg_count =
+ sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
+
static void
do_co_reg (void)
{
unsigned Rd;
+ size_t i;
Rd = inst.operands[2].reg;
if (thumb_mode)
@@ -7733,6 +7775,23 @@ do_co_reg (void)
constraint (Rd == REG_PC, BAD_PC);
}
+ for (i = 0; i < deprecated_coproc_reg_count; ++i)
+ {
+ const struct deprecated_coproc_regs_s *r =
+ deprecated_coproc_regs + i;
+
+ if (inst.operands[0].reg == r->cp
+ && inst.operands[1].imm == r->opc1
+ && inst.operands[3].reg == r->crn
+ && inst.operands[4].reg == r->crm
+ && inst.operands[5].imm == r->opc2)
+ {
+ if (!check_obsolete (&r->obsoleted, r->obs_msg)
+ && warn_on_deprecated
+ && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
+ as_warn ("%s", r->dep_msg);
+ }
+ }
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].imm << 21;
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.l b/gas/testsuite/gas/arm/armv8-a-bad.l
index 2c9a147..cde1bba 100644
--- a/gas/testsuite/gas/arm/armv8-a-bad.l
+++ b/gas/testsuite/gas/arm/armv8-a-bad.l
@@ -1,2 +1,7 @@
.*: Assembler messages:
.*:7: Error: swp{b} use is obsoleted for ARMv8 and later
+.*:10: Warning: This coprocessor register access is deprecated in ARMv8
+.*:11: Warning: This coprocessor register access is deprecated in ARMv8
+.*:12: Warning: This coprocessor register access is deprecated in ARMv8
+.*:13: Warning: This coprocessor register access is deprecated in ARMv8
+.*:14: Warning: This coprocessor register access is deprecated in ARMv8
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.s b/gas/testsuite/gas/arm/armv8-a-bad.s
index a6d55c7..af08639 100644
--- a/gas/testsuite/gas/arm/armv8-a-bad.s
+++ b/gas/testsuite/gas/arm/armv8-a-bad.s
@@ -5,3 +5,10 @@
// SWP
.arm
swp r0, r1, [r2]
+
+ // deprecated MCRs
+ mcr p15, 0, r0, c7, c5, 4
+ mcr p15, 0, r1, c7, c10, 4
+ mcr p15, 0, r2, c7, c10, 5
+ mrc p14, 6, r1, c0, c0, 0
+ mrc p14, 6, r0, c1, c0, 0
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 02/21] Mark SWP as obsolete.
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
2012-08-23 14:55 ` [RFA/ARM 01/21] Add command line and object file support for ARMv8-A Matthew Gretton-Dann
2012-08-23 14:56 ` [RFA/ARM 03/21] Warn on deprecated Co-processor register accesses Matthew Gretton-Dann
@ 2012-08-23 14:56 ` Matthew Gretton-Dann
2012-08-23 16:29 ` Richard Earnshaw
2012-08-23 14:57 ` [RFA/ARM 04/21] Warn on deprecated IT blocks Matthew Gretton-Dann
` (17 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 14:56 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 740 bytes --]
ARMv8 obsoletes the SWP{B} instructions.
This patch updates the assembler to error in this case.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (check_obsolete): New function.
(do_rd_rm_rn): Check swp{b} for obsoletion.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a-bad.d: New testcase.
* gas/arm/armv8-a-bad.l: Likewise.
* gas/arm/armv8-a-bad.s: Likewise.
* gas/arm/depr-swp.l: Update for change in expected output.
* gas/arm/depr-swp.s: Add additional test.
include/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* opcode/arm.h (ARM_CPU_IS_ANY): New define.
[-- Attachment #2: 0002-Mark-SWP-as-obsolete.txt --]
[-- Type: text/x-patch, Size: 3704 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 101f86b..af4a1e5 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7373,6 +7373,23 @@ do_rn_rd (void)
inst.instruction |= inst.operands[1].reg << 12;
}
+static bfd_boolean
+check_obsolete (const arm_feature_set *feature, const char *msg)
+{
+ if (ARM_CPU_IS_ANY (cpu_variant))
+ {
+ as_warn ("%s", msg);
+ return TRUE;
+ }
+ else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
+ {
+ as_bad ("%s", msg);
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
static void
do_rd_rm_rn (void)
{
@@ -7383,12 +7400,15 @@ do_rd_rm_rn (void)
constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
_("Rn must not overlap other operands"));
- /* SWP{b} is deprecated for ARMv6* and ARMv7. */
- if (warn_on_deprecated
- && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
- as_warn (_("swp{b} use is deprecated for this architecture"));
-
+ /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
+ */
+ if (!check_obsolete (&arm_ext_v8,
+ _("swp{b} use is obsoleted for ARMv8 and later"))
+ && warn_on_deprecated
+ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
+ as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
}
+
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg;
inst.instruction |= Rn << 16;
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.d b/gas/testsuite/gas/arm/armv8-a-bad.d
new file mode 100644
index 0000000..94e130c
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a-bad.d
@@ -0,0 +1,2 @@
+#name: Invalid v8-a
+#error-output: armv8-a-bad.l
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.l b/gas/testsuite/gas/arm/armv8-a-bad.l
new file mode 100644
index 0000000..2c9a147
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a-bad.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*:7: Error: swp{b} use is obsoleted for ARMv8 and later
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.s b/gas/testsuite/gas/arm/armv8-a-bad.s
new file mode 100644
index 0000000..a6d55c7
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a-bad.s
@@ -0,0 +1,7 @@
+ .syntax unified
+ .text
+ .arch armv8-a
+
+ // SWP
+ .arm
+ swp r0, r1, [r2]
diff --git a/gas/testsuite/gas/arm/depr-swp.l b/gas/testsuite/gas/arm/depr-swp.l
index e5052a7..830f13b 100644
--- a/gas/testsuite/gas/arm/depr-swp.l
+++ b/gas/testsuite/gas/arm/depr-swp.l
@@ -1,3 +1,4 @@
[^:]*: Assembler messages:
-[^:]*:5: Warning: swp{b} use is deprecated for this architecture
-[^:]*:7: Warning: swp{b} use is deprecated for this architecture
+[^:]*:2: Warning: swp{b} use is obsoleted for ARMv8 and later
+[^:]*:6: Warning: swp{b} use is deprecated for ARMv6 and ARMv7
+[^:]*:8: Warning: swp{b} use is deprecated for ARMv6 and ARMv7
diff --git a/gas/testsuite/gas/arm/depr-swp.s b/gas/testsuite/gas/arm/depr-swp.s
index e5c1df3..ceb7d41 100644
--- a/gas/testsuite/gas/arm/depr-swp.s
+++ b/gas/testsuite/gas/arm/depr-swp.s
@@ -1,4 +1,5 @@
.syntax unified
+swp r0, r1, [r2]
.arch armv4
swp r0, r1, [r2]
.arch armv6
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 1c350c8..1ac38a0 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -269,6 +269,9 @@ typedef struct
#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
(((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0)
+#define ARM_CPU_IS_ANY(CPU) \
+ ((CPU).core == ((arm_feature_set)ARM_ANY).core)
+
#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
do { \
(TARG).core = (F1).core | (F2).core; \
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 04/21] Warn on deprecated IT blocks.
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (2 preceding siblings ...)
2012-08-23 14:56 ` [RFA/ARM 02/21] Mark SWP as obsolete Matthew Gretton-Dann
@ 2012-08-23 14:57 ` Matthew Gretton-Dann
2012-08-23 16:31 ` Richard Earnshaw
2012-08-23 14:57 ` [RFA/ARM 05/21] Warn that SETEND is deprecated Matthew Gretton-Dann
` (16 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 14:57 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1353 bytes --]
ARMv8 deprecates various forms of IT blocks. This patch adds warnings
for these cases.
The IT block forms deprecated are:
* Those with more than one instruction in the IT block
* Those with a 32-bit instruction in the IT block
* Various 16-bit instructions (mostly involving PC).
This patch does not change the handling of automatic IT block generation.
This is to be done in a later patch.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (do_t_it): Fully initialise now_it.
(new_automatic_it_block): Likewise.
(handle_it_block): Record whether current instruction is
conditionally executed.
* config/tc-arm.c (depr_insn_mask): New structure.
(depr_it_insns): New variable.
(it_fsm_post_encode): Warn on deprecated uses.
* config/tc-arm.h (current_it): Add new fields.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a-it-bad.d: New testcase.
* gas/arm/armv8-a-it-bad.l: Likewise.
* gas/arm/armv8-a-it-bad.s: Likewise.
* gas/arm/ldr-t-bad.s: Update testcase.
* gas/arm/ldr-t.d: Likewise.
* gas/arm/ldr-t.s: Likewise.
* gas/arm/neon-cond-bad-inc.s: Likewise.
* gas/arm/sp-pc-validations-bad-t: Likewise.
* gas/arm/vfp-fma-inc.s: Likewise.
* gas/arm/vfp-neon-syntax-inc.s: Likewise.
[-- Attachment #2: 0004-Warn-on-deprecated-IT-blocks.txt --]
[-- Type: text/x-patch, Size: 11033 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 02e843d..d9cf3d3 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10356,6 +10356,7 @@ do_t_it (void)
set_it_insn_type (IT_INSN);
now_it.mask = (inst.instruction & 0xf) | 0x10;
now_it.cc = cond;
+ now_it.warn_deprecated = FALSE;
/* If the condition is a negative condition, invert the mask. */
if ((cond & 0x1) == 0x0)
@@ -10363,13 +10364,25 @@ do_t_it (void)
unsigned int mask = inst.instruction & 0x000f;
if ((mask & 0x7) == 0)
- /* no conversion needed */;
+ {
+ /* No conversion needed. */
+ now_it.block_length = 1;
+ }
else if ((mask & 0x3) == 0)
- mask ^= 0x8;
+ {
+ mask ^= 0x8;
+ now_it.block_length = 2;
+ }
else if ((mask & 0x1) == 0)
- mask ^= 0xC;
+ {
+ mask ^= 0xC;
+ now_it.block_length = 3;
+ }
else
- mask ^= 0xE;
+ {
+ mask ^= 0xE;
+ now_it.block_length = 4;
+ }
inst.instruction &= 0xfff0;
inst.instruction |= mask;
@@ -16187,6 +16200,8 @@ new_automatic_it_block (int cond)
now_it.block_length = 1;
mapping_state (MAP_THUMB);
now_it.insn = output_it_inst (cond, now_it.mask, NULL);
+ now_it.warn_deprecated = FALSE;
+ now_it.insn_cond = TRUE;
}
/* Close an automatic IT block.
@@ -16294,6 +16309,7 @@ static int
handle_it_state (void)
{
now_it.state_handled = 1;
+ now_it.insn_cond = FALSE;
switch (now_it.state)
{
@@ -16371,6 +16387,7 @@ handle_it_state (void)
}
else
{
+ now_it.insn_cond = TRUE;
now_it_add_mask (inst.cond);
}
@@ -16382,6 +16399,7 @@ handle_it_state (void)
case NEUTRAL_IT_INSN:
now_it.block_length++;
+ now_it.insn_cond = TRUE;
if (now_it.block_length > 4)
force_automatic_it_block_close ();
@@ -16404,6 +16422,7 @@ handle_it_state (void)
now_it.mask <<= 1;
now_it.mask &= 0x1f;
is_last = (now_it.mask == 0x10);
+ now_it.insn_cond = TRUE;
switch (inst.it_insn_type)
{
@@ -16448,6 +16467,25 @@ handle_it_state (void)
return SUCCESS;
}
+struct depr_insn_mask
+{
+ unsigned long pattern;
+ unsigned long mask;
+ const char* description;
+};
+
+/* List of 16-bit instruction patterns deprecated in an IT block in
+ ARMv8. */
+static const struct depr_insn_mask depr_it_insns[] = {
+ { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
+ { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
+ { 0xa000, 0xb800, N_("ADR") },
+ { 0x4800, 0xf800, N_("Literal loads") },
+ { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
+ { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
+ { 0, 0, NULL }
+};
+
static void
it_fsm_post_encode (void)
{
@@ -16456,6 +16494,44 @@ it_fsm_post_encode (void)
if (!now_it.state_handled)
handle_it_state ();
+ if (now_it.insn_cond
+ && !now_it.warn_deprecated
+ && warn_on_deprecated
+ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
+ {
+ if (inst.instruction >= 0x10000)
+ {
+ as_warn (_("it blocks containing wide Thumb instructions are "
+ "deprecated in ARMv8"));
+ now_it.warn_deprecated = TRUE;
+ }
+ else
+ {
+ const struct depr_insn_mask *p = depr_it_insns;
+
+ while (p->mask != 0)
+ {
+ if ((inst.instruction & p->mask) == p->pattern)
+ {
+ as_warn (_("it blocks containing 16-bit Thumb intsructions "
+ "of the following class are deprecated in ARMv8: "
+ "%s"), p->description);
+ now_it.warn_deprecated = TRUE;
+ break;
+ }
+
+ ++p;
+ }
+ }
+
+ if (now_it.block_length > 1)
+ {
+ as_warn (_("it blocks of more than one conditional instruction are "
+ "deprecated in ARMv8"));
+ now_it.warn_deprecated = TRUE;
+ }
+ }
+
is_last = (now_it.mask == 0x10);
if (is_last)
{
diff --git a/gas/config/tc-arm.h b/gas/config/tc-arm.h
index 4425d75..da6469c 100644
--- a/gas/config/tc-arm.h
+++ b/gas/config/tc-arm.h
@@ -257,6 +257,8 @@ struct current_it
int block_length;
char *insn;
int state_handled;
+ int warn_deprecated;
+ int insn_cond;
};
#ifdef OBJ_ELF
diff --git a/gas/testsuite/gas/arm/armv8-a-it-bad.d b/gas/testsuite/gas/arm/armv8-a-it-bad.d
new file mode 100644
index 0000000..4789484
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a-it-bad.d
@@ -0,0 +1,3 @@
+#name: Deprecated IT blocks (ARM v8)
+#error-output: armv8-a-it-bad.l
+#as: -mimplicit-it=always
diff --git a/gas/testsuite/gas/arm/armv8-a-it-bad.l b/gas/testsuite/gas/arm/armv8-a-it-bad.l
new file mode 100644
index 0000000..aa1b53b
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a-it-bad.l
@@ -0,0 +1,14 @@
+.*: Assembler messages:
+.*:7: Warning: it blocks containing wide Thumb instructions are deprecated in ARMv8
+.*:15: Warning: it blocks of more than one conditional instruction are deprecated in ARMv8
+.*:20: Warning: it blocks of more than one conditional instruction are deprecated in ARMv8
+.*:30: Warning: it blocks containing wide Thumb instructions are deprecated in ARMv8
+.*:36: Warning: it blocks of more than one conditional instruction are deprecated in ARMv8
+.*:40: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
+.*:43: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions
+.*:49: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Literal loads
+.*:52: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Hi-register ADD, MOV, CMP, BX, BLX using pc
+.*:55: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
+.*:55: Error: r15 not allowed here -- `addeq r0,pc,pc'
+.*:58: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
+.*:58: Error: r15 not allowed here -- `addeq pc,r0,r0'
diff --git a/gas/testsuite/gas/arm/armv8-a-it-bad.s b/gas/testsuite/gas/arm/armv8-a-it-bad.s
new file mode 100644
index 0000000..42f2b86
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a-it-bad.s
@@ -0,0 +1,58 @@
+.syntax unified
+.arch armv8-a
+
+.thumb
+@ Wide instruction in IT block is deprecated.
+it eq
+ldrdeq r0, [r1]
+
+@ This IT block is not deprecated.
+it eq
+moveq r2, r3
+
+@ IT block of more than one instruction is deprecated.
+itt eq
+moveq r0, r1
+moveq r2, r3
+
+@ Even for auto IT blocks
+moveq r2, r3
+movne r2, r3
+
+adds r0, r1
+
+@ This automatic IT block is valid
+moveq r2,r3
+
+add r0, r1, r2
+
+@ This one is too wide.
+ldrdeq r0, [r1]
+
+add r0, r1, r2
+
+@ Test automatic IT block generation at end of a file.
+movne r0, r1
+moveq r1, r0
+
+@ Test the various classes of 16-bit instructions that are deprecated.
+it eq
+svceq 0
+
+it eq
+uxtheq r0, r1
+
+it eq
+addeq r0, pc, #0
+
+it eq
+ldreq r0, [pc, #4]
+
+it eq
+bxeq pc
+
+it eq
+addeq r0, pc, pc
+
+it eq
+addeq pc, r0, r0
diff --git a/gas/testsuite/gas/arm/ldr-t-bad.s b/gas/testsuite/gas/arm/ldr-t-bad.s
index 81c17a5..a1e22bd 100644
--- a/gas/testsuite/gas/arm/ldr-t-bad.s
+++ b/gas/testsuite/gas/arm/ldr-t-bad.s
@@ -1,5 +1,5 @@
.syntax unified
-
+.arch armv7-a
.thumb
@ldr-immediate
diff --git a/gas/testsuite/gas/arm/ldr-t.d b/gas/testsuite/gas/arm/ldr-t.d
index 1b50837..ddcd612 100644
--- a/gas/testsuite/gas/arm/ldr-t.d
+++ b/gas/testsuite/gas/arm/ldr-t.d
@@ -11,22 +11,22 @@ Disassembly of section [^>]+:
0+10 <[^>]+> f8df f004 ldr.w pc, \[pc, #4\] ; 0+18 <[^>]+0x18>
0+14 <[^>]+> bfa2 ittt ge
0+16 <[^>]+> 4901 ldrge r1, \[pc, #4\] ; \(0+1c <[^>]+0x1c>\)
-0+18 <[^>]+> 46c0 nopge ; \(mov r8, r8\)
-0+1a <[^>]+> 46c0 nopge ; \(mov r8, r8\)
+0+18 <[^>]+> bf00 nopge
+0+1a <[^>]+> bf00 nopge
0+1c <[^>]+> bfa8 it ge
0+1e <[^>]+> f8df f004 ldrge.w pc, \[pc, #4\] ; 0+24 <[^>]+0x24>
0+22 <[^>]+> bfa2 ittt ge
0+24 <[^>]+> f85f 1ab8 ldrge.w r1, \[pc, #-2744\] ; fffff570 <[^>]+>
-0+28 <[^>]+> 46c0 nopge ; \(mov r8, r8\)
-0+2a <[^>]+> 46c0 nopge ; \(mov r8, r8\)
+0+28 <[^>]+> bf00 nopge
+0+2a <[^>]+> bf00 nopge
0+2c <[^>]+> bfa8 it ge
0+2e <[^>]+> f85f fab6 ldrge.w pc, \[pc, #-2742\] ; fffff57a <[^>]+>
0+32 <[^>]+> f85f 1ab9 ldr.w r1, \[pc, #-2745\] ; fffff57b <[^>]+>
0+36 <[^>]+> f85f fab6 ldr.w pc, \[pc, #-2742\] ; fffff582 <[^>]+>
0+3a <[^>]+> bfa2 ittt ge
0+3c <[^>]+> 5851 ldrge r1, \[r2, r1\]
-0+3e <[^>]+> 46c0 nopge ; \(mov r8, r8\)
-0+40 <[^>]+> 46c0 nopge ; \(mov r8, r8\)
+0+3e <[^>]+> bf00 nopge
+0+40 <[^>]+> bf00 nopge
0+42 <[^>]+> bfa8 it ge
0+44 <[^>]+> f852 f001 ldrge.w pc, \[r2, r1\]
0+48 <[^>]+> 58d1 ldr r1, \[r2, r3\]
diff --git a/gas/testsuite/gas/arm/ldr-t.s b/gas/testsuite/gas/arm/ldr-t.s
index b6462c9..4aaecdf 100644
--- a/gas/testsuite/gas/arm/ldr-t.s
+++ b/gas/testsuite/gas/arm/ldr-t.s
@@ -1,5 +1,5 @@
.syntax unified
-
+.arch armv7-a
.thumb
.global foo
foo:
diff --git a/gas/testsuite/gas/arm/neon-cond-bad-inc.s b/gas/testsuite/gas/arm/neon-cond-bad-inc.s
index a92d196..2f56773 100644
--- a/gas/testsuite/gas/arm/neon-cond-bad-inc.s
+++ b/gas/testsuite/gas/arm/neon-cond-bad-inc.s
@@ -1,9 +1,9 @@
# Check for illegal conditional Neon instructions in ARM mode. The instructions
# which overlap with VFP are the tricky cases, so test those.
-
.include "itblock.s"
-
.syntax unified
+ .arch armv7-a
+ .fpu neon
.text
func:
itblock 4 eq
diff --git a/gas/testsuite/gas/arm/sp-pc-validations-bad-t.s b/gas/testsuite/gas/arm/sp-pc-validations-bad-t.s
index 0b155fb..3da0861 100644
--- a/gas/testsuite/gas/arm/sp-pc-validations-bad-t.s
+++ b/gas/testsuite/gas/arm/sp-pc-validations-bad-t.s
@@ -1,6 +1,6 @@
.syntax unified
+.arch armv7-a
.thumb
-
.macro it_test opcode operands:vararg
itt eq
\opcode\()eq r15, \operands
diff --git a/gas/testsuite/gas/arm/vfp-fma-inc.s b/gas/testsuite/gas/arm/vfp-fma-inc.s
index a9dcb14..4f349e1 100644
--- a/gas/testsuite/gas/arm/vfp-fma-inc.s
+++ b/gas/testsuite/gas/arm/vfp-fma-inc.s
@@ -1,4 +1,6 @@
.syntax unified
+ .arch armv7-a
+ .fpu neon-vfpv4
.include "itblock.s"
diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s b/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s
index fad0bde..5005cb7 100644
--- a/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s
+++ b/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s
@@ -1,5 +1,6 @@
@ VFP with Neon-style syntax
.syntax unified
+ .arch armv7-a
.include "itblock.s"
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 05/21] Warn that SETEND is deprecated.
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (3 preceding siblings ...)
2012-08-23 14:57 ` [RFA/ARM 04/21] Warn on deprecated IT blocks Matthew Gretton-Dann
@ 2012-08-23 14:57 ` Matthew Gretton-Dann
2012-08-23 16:32 ` Richard Earnshaw
2012-08-23 14:58 ` [RFA/ARM 06/21] Add support diagnosing UNPREDICTABLE conditional instructions Matthew Gretton-Dann
` (15 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 14:57 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 451 bytes --]
ARMv8 deprecates the SETEND instruction.
This patch causes the assembler to warn when it encounters SETEND.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (do_setend): Warn on deprecated SETEND.
(do_t_setend): Likewise.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a-bad.l: Update
* gas/arm/armv8-a-bad.s: Likewise.
[-- Attachment #2: 0005-Warn-that-SETEND-is-deprecated.txt --]
[-- Type: text/x-patch, Size: 1690 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d9cf3d3..8f2f88b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -8528,6 +8528,10 @@ do_usat16 (void)
static void
do_setend (void)
{
+ if (warn_on_deprecated
+ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
+ as_warn (_("setend use is deprecated for ARMv8"));
+
if (inst.operands[0].imm)
inst.instruction |= 0x200;
}
@@ -11769,6 +11773,10 @@ do_t_rsb (void)
static void
do_t_setend (void)
{
+ if (warn_on_deprecated
+ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
+ as_warn (_("setend use is deprecated for ARMv8"));
+
set_it_insn_type (OUTSIDE_IT_INSN);
if (inst.operands[0].imm)
inst.instruction |= 0x8;
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.l b/gas/testsuite/gas/arm/armv8-a-bad.l
index cde1bba..e96efce 100644
--- a/gas/testsuite/gas/arm/armv8-a-bad.l
+++ b/gas/testsuite/gas/arm/armv8-a-bad.l
@@ -5,3 +5,5 @@
.*:12: Warning: This coprocessor register access is deprecated in ARMv8
.*:13: Warning: This coprocessor register access is deprecated in ARMv8
.*:14: Warning: This coprocessor register access is deprecated in ARMv8
+.*:17: Warning: setend use is deprecated for ARMv8
+.*:20: Warning: setend use is deprecated for ARMv8
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.s b/gas/testsuite/gas/arm/armv8-a-bad.s
index af08639..33a3c17 100644
--- a/gas/testsuite/gas/arm/armv8-a-bad.s
+++ b/gas/testsuite/gas/arm/armv8-a-bad.s
@@ -12,3 +12,9 @@
mcr p15, 0, r2, c7, c10, 5
mrc p14, 6, r1, c0, c0, 0
mrc p14, 6, r0, c1, c0, 0
+
+ // deprecated SETEND
+ setend be
+
+ .thumb
+ setend le
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 06/21] Add support diagnosing UNPREDICTABLE conditional instructions
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (4 preceding siblings ...)
2012-08-23 14:57 ` [RFA/ARM 05/21] Warn that SETEND is deprecated Matthew Gretton-Dann
@ 2012-08-23 14:58 ` Matthew Gretton-Dann
2012-08-23 16:32 ` Richard Earnshaw
2012-08-23 14:59 ` [RFA/ARM 08/21] Add support for SEVL Matthew Gretton-Dann
` (14 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 14:58 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 554 bytes --]
Some of the new instructions in ARMv8 are UNPREDICTABLE when executed
in an IT block (these are all SIMD/FP instructions).
This patch adds infrastructure to support diagnosing these instructions
in the disassembler.
Note that the repurposing of %u in the opcode16 table is fine as it has
never been used previously.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
* arm-dis.c (COND_UNCOND): New constant.
(print_insn_coprocessor): Add support for %u format specifier.
(print_insn_neon): Likewise.
[-- Attachment #2: 0006-Add-support-diagnosing-UNPREDICTABLE-conditional-instr.txt --]
[-- Type: text/x-patch, Size: 3178 bytes --]
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 74d78cb..532a6c8 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -92,7 +92,8 @@ struct opcode16
%c print condition code (always bits 28-31 in ARM mode)
%q print shifter argument
- %u print condition code (unconditional in ARM mode)
+ %u print condition code (unconditional in ARM mode,
+ UNPREDICTABLE if not AL in Thumb)
%A print address for ldc/stc/ldf/stf instruction
%B print vstm/vldm register list
%I print cirrus signed shift immediate: bits 0..3|4..6
@@ -519,6 +520,8 @@ static const struct opcode32 coprocessor_opcodes[] =
%% %
%c print condition code
+ %u print condition code (unconditional in ARM mode,
+ UNPREDICTABLE if not AL in Thumb)
%A print v{st,ld}[1234] operands
%B print v{st,ld}[1234] any one operands
%C print v{st,ld}[1234] single->all operands
@@ -1692,6 +1695,9 @@ static unsigned int ifthen_next_state;
/* The address of the insn for which the IT state is valid. */
static bfd_vma ifthen_address;
#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
+/* Indicates that the current Conditional state is unconditional or outside
+ an IT block. */
+#define COND_UNCOND 16
\f
/* Functions. */
@@ -1870,7 +1876,7 @@ print_insn_coprocessor (bfd_vma pc,
if (ifthen_state)
cond = IFTHEN_COND;
else
- cond = 16;
+ cond = COND_UNCOND;
}
else
{
@@ -1879,13 +1885,13 @@ print_insn_coprocessor (bfd_vma pc,
if ((given & 0xf0000000) == 0xf0000000)
{
mask |= 0xf0000000;
- cond = 16;
+ cond = COND_UNCOND;
}
else
{
cond = (given >> 28) & 0xf;
if (cond == 0xe)
- cond = 16;
+ cond = COND_UNCOND;
}
}
@@ -1979,6 +1985,11 @@ print_insn_coprocessor (bfd_vma pc,
}
break;
+ case 'u':
+ if (cond != COND_UNCOND)
+ is_unpredictable = TRUE;
+
+ /* Fall through. */
case 'c':
func (stream, "%s", arm_conditional[cond]);
break;
@@ -2488,6 +2499,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
if ((given & insn->mask) == insn->value)
{
signed long value_in_comment = 0;
+ bfd_boolean is_unpredictable = FALSE;
const char *c;
for (c = insn->assembler; *c; c++)
@@ -2500,6 +2512,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
func (stream, "%%");
break;
+ case 'u':
+ if (thumb && ifthen_state)
+ is_unpredictable = TRUE;
+
+ /* Fall through. */
case 'c':
if (thumb && ifthen_state)
func (stream, "%s", arm_conditional[IFTHEN_COND]);
@@ -2913,6 +2930,9 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
if (value_in_comment > 32 || value_in_comment < -16)
func (stream, "\t; 0x%lx", value_in_comment);
+ if (is_unpredictable)
+ func (stream, UNPREDICTABLE_INSTRUCTION);
+
return TRUE;
}
}
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 08/21] Add support for SEVL
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (5 preceding siblings ...)
2012-08-23 14:58 ` [RFA/ARM 06/21] Add support diagnosing UNPREDICTABLE conditional instructions Matthew Gretton-Dann
@ 2012-08-23 14:59 ` Matthew Gretton-Dann
2012-08-23 16:33 ` Richard Earnshaw
2012-08-23 14:59 ` [RFA/ARM 07/21] Add support for new options to DMB/DSB Matthew Gretton-Dann
` (13 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 14:59 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 591 bytes --]
ARMv8 adds the SEVL instruction to A32 and T32.
This patch adds support for it.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (T16_32_TAB): Add _sevl.
(insns): Add SEVL.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a.s: New testcase.
* gas/arm/armv8-a.d: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (arm_opcodes): Add SEVL.
(thumb_opcodes): Likewise.
(thumb32_opcodes): Likewise.
[-- Attachment #2: 0008-Add-support-for-SEVL.txt --]
[-- Type: text/x-patch, Size: 3381 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d3838ab..cfcdecb 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -9549,7 +9549,8 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
X(_yield, bf10, f3af8001), \
X(_wfe, bf20, f3af8002), \
X(_wfi, bf30, f3af8003), \
- X(_sev, bf40, f3af8004),
+ X(_sev, bf40, f3af8004), \
+ X(_sevl, bf50, f3af8005)
/* To catch errors in encoding functions, the codes are all offset by
0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
@@ -17966,8 +17967,18 @@ static const struct asm_opcode insns[] =
TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
+ /* AArchv8 instructions. */
+#undef ARM_VARIANT
+#define ARM_VARIANT & arm_ext_v8
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8
+
+ tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
+
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT NULL
cCE("wfs", e200110, 1, (RR), rd),
cCE("rfs", e300110, 1, (RR), rd),
diff --git a/gas/testsuite/gas/arm/armv8-a.d b/gas/testsuite/gas/arm/armv8-a.d
new file mode 100644
index 0000000..f558910
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a.d
@@ -0,0 +1,10 @@
+#name: Valid v8-a
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> e320f005 sevl
+0[0-9a-f]+ <[^>]+> bf50 sevl
+0[0-9a-f]+ <[^>]+> bf50 sevl
+0[0-9a-f]+ <[^>]+> f3af 8005 sevl.w
diff --git a/gas/testsuite/gas/arm/armv8-a.s b/gas/testsuite/gas/arm/armv8-a.s
new file mode 100644
index 0000000..000a5a7
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a.s
@@ -0,0 +1,14 @@
+ .syntax unified
+ .text
+ .arch armv8-a
+
+ .arm
+foo:
+ sevl
+
+ .thumb
+ .thumb_func
+bar:
+ sevl
+ sevl.n
+ sevl.w
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index ccbb6b3..5a450d7 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -849,6 +849,9 @@ static const struct opcode32 arm_opcodes[] =
{ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
{ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
+ /* V8 instructions. */
+ {ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"},
+
/* Virtualization Extension instructions. */
{ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
{ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
@@ -1244,6 +1247,9 @@ static const struct opcode16 thumb_opcodes[] =
{
/* Thumb instructions. */
+ /* ARM V8 instructions. */
+ {ARM_EXT_V8, 0xbf50, 0xffff, "sevl%c"},
+
/* ARM V6K no-argument instructions. */
{ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
{ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
@@ -1413,6 +1419,9 @@ static const struct opcode16 thumb_opcodes[] =
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
+ /* V8 instructions. */
+ {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
+
/* V7 instructions. */
{ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
{ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 07/21] Add support for new options to DMB/DSB
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (6 preceding siblings ...)
2012-08-23 14:59 ` [RFA/ARM 08/21] Add support for SEVL Matthew Gretton-Dann
@ 2012-08-23 14:59 ` Matthew Gretton-Dann
2012-08-23 16:33 ` Richard Earnshaw
2012-08-23 15:00 ` [RFA/ARM 09/21] Add support for DCPS instruction Matthew Gretton-Dann
` (12 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 14:59 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 964 bytes --]
ARMv8 adds new options to DMB/DSB in A32/T32.
We do a bit of re-engineering in opcodes/arm-dis.c to common up the
decode of the options to DMB/DSB.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (asm_barrier_opt): Add arch field.
(mark_feature_used): New function.
(parse_barrier): Check specified option is valid for the
specified architecture.
(UL_BARRIER): New macro.
(barrier_opt_names): Update for new barrier options.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a-barrier.s: New testcase.
* gas/arm/armv8-a-barrier-arm.d: Likewise.
* gas/arm/armv8-a-barrier-thumb.d: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (data_barrier_option): New function.
(print_insn_arm): Use data_barrier_option.
(print_insn_thumb32): Use data_barrier_option.
[-- Attachment #2: 0007-Add-support-for-new-options-to-DMB-DSB.txt --]
[-- Type: text/x-patch, Size: 9243 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 8f2f88b..d3838ab 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -461,8 +461,9 @@ struct asm_psr
struct asm_barrier_opt
{
- const char * template_name;
- unsigned long value;
+ const char * template_name;
+ unsigned long value;
+ const arm_feature_set arch;
};
/* The bit that distinguishes CPSR and SPSR. */
@@ -5766,6 +5767,25 @@ parse_cond (char **str)
return c->value;
}
+/* If the given feature available in the selected CPU, mark it as used.
+ Returns TRUE iff feature is available. */
+static bfd_boolean
+mark_feature_used (const arm_feature_set *feature)
+{
+ /* Ensure the option is valid on the current architecture. */
+ if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
+ return FALSE;
+
+ /* Add the appropriate architecture feature for the barrier option used.
+ */
+ if (thumb_mode)
+ ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
+ else
+ ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
+
+ return TRUE;
+}
+
/* Parse an option for a barrier instruction. Returns the encoding for the
option, or FAIL. */
static int
@@ -5783,6 +5803,9 @@ parse_barrier (char **str)
if (!o)
return FAIL;
+ if (!mark_feature_used (&o->arch))
+ return FAIL;
+
*str = q;
return o->value;
}
@@ -17170,22 +17193,32 @@ static const struct asm_cond conds[] =
{"al", 0xe}
};
+#define UL_BARRIER(L,U,CODE,FEAT) \
+ { L, CODE, ARM_FEATURE (FEAT, 0) }, \
+ { U, CODE, ARM_FEATURE (FEAT, 0) }
+
static struct asm_barrier_opt barrier_opt_names[] =
{
- { "sy", 0xf }, { "SY", 0xf },
- { "un", 0x7 }, { "UN", 0x7 },
- { "st", 0xe }, { "ST", 0xe },
- { "unst", 0x6 }, { "UNST", 0x6 },
- { "ish", 0xb }, { "ISH", 0xb },
- { "sh", 0xb }, { "SH", 0xb },
- { "ishst", 0xa }, { "ISHST", 0xa },
- { "shst", 0xa }, { "SHST", 0xa },
- { "nsh", 0x7 }, { "NSH", 0x7 },
- { "nshst", 0x6 }, { "NSHST", 0x6 },
- { "osh", 0x3 }, { "OSH", 0x3 },
- { "oshst", 0x2 }, { "OSHST", 0x2 }
+ UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
+ UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
+ UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
+ UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
+ UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
+ UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
+ UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
+ UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
+ UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
+ UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
+ UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
+ UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
+ UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
+ UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
+ UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
+ UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
};
+#undef UL_BARRIER
+
/* Table of ARM-format instructions. */
/* Macros for gluing together operand strings. N.B. In all cases
diff --git a/gas/testsuite/gas/arm/armv8-a-barrier-arm.d b/gas/testsuite/gas/arm/armv8-a-barrier-arm.d
new file mode 100644
index 0000000..1a245fa
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a-barrier-arm.d
@@ -0,0 +1,24 @@
+#name: Valid v8-A barrier (ARM)
+#as: -march=armv8-a
+#source: armv8-a-barrier.s
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f57ff04d dsb ld
+0[0-9a-f]+ <[^>]+> f57ff049 dsb ishld
+0[0-9a-f]+ <[^>]+> f57ff045 dsb nshld
+0[0-9a-f]+ <[^>]+> f57ff041 dsb oshld
+0[0-9a-f]+ <[^>]+> f57ff05d dmb ld
+0[0-9a-f]+ <[^>]+> f57ff059 dmb ishld
+0[0-9a-f]+ <[^>]+> f57ff055 dmb nshld
+0[0-9a-f]+ <[^>]+> f57ff051 dmb oshld
+0[0-9a-f]+ <[^>]+> f57ff04d dsb ld
+0[0-9a-f]+ <[^>]+> f57ff049 dsb ishld
+0[0-9a-f]+ <[^>]+> f57ff045 dsb nshld
+0[0-9a-f]+ <[^>]+> f57ff041 dsb oshld
+0[0-9a-f]+ <[^>]+> f57ff05d dmb ld
+0[0-9a-f]+ <[^>]+> f57ff059 dmb ishld
+0[0-9a-f]+ <[^>]+> f57ff055 dmb nshld
+0[0-9a-f]+ <[^>]+> f57ff051 dmb oshld
diff --git a/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d b/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d
new file mode 100644
index 0000000..42dae15
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d
@@ -0,0 +1,24 @@
+#name: Valid v8-A barrier (Thumb)
+#as: -march=armv8-a -mthumb
+#source: armv8-a-barrier.s
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f3bf 8f4d dsb ld
+0[0-9a-f]+ <[^>]+> f3bf 8f49 dsb ishld
+0[0-9a-f]+ <[^>]+> f3bf 8f45 dsb nshld
+0[0-9a-f]+ <[^>]+> f3bf 8f41 dsb oshld
+0[0-9a-f]+ <[^>]+> f3bf 8f5d dmb ld
+0[0-9a-f]+ <[^>]+> f3bf 8f59 dmb ishld
+0[0-9a-f]+ <[^>]+> f3bf 8f55 dmb nshld
+0[0-9a-f]+ <[^>]+> f3bf 8f51 dmb oshld
+0[0-9a-f]+ <[^>]+> f3bf 8f4d dsb ld
+0[0-9a-f]+ <[^>]+> f3bf 8f49 dsb ishld
+0[0-9a-f]+ <[^>]+> f3bf 8f45 dsb nshld
+0[0-9a-f]+ <[^>]+> f3bf 8f41 dsb oshld
+0[0-9a-f]+ <[^>]+> f3bf 8f5d dmb ld
+0[0-9a-f]+ <[^>]+> f3bf 8f59 dmb ishld
+0[0-9a-f]+ <[^>]+> f3bf 8f55 dmb nshld
+0[0-9a-f]+ <[^>]+> f3bf 8f51 dmb oshld
diff --git a/gas/testsuite/gas/arm/armv8-a-barrier.s b/gas/testsuite/gas/arm/armv8-a-barrier.s
new file mode 100644
index 0000000..f7b71c0
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a-barrier.s
@@ -0,0 +1,18 @@
+ .syntax unified
+ .text
+ dsb ld
+ dsb ishld
+ dsb nshld
+ dsb oshld
+ dmb ld
+ dmb ishld
+ dmb nshld
+ dmb oshld
+ dsb LD
+ dsb ISHLD
+ dsb NSHLD
+ dsb OSHLD
+ dmb LD
+ dmb ISHLD
+ dmb NSHLD
+ dmb OSHLD
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 532a6c8..ccbb6b3 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -863,6 +863,8 @@ static const struct opcode32 arm_opcodes[] =
/* V7 instructions. */
{ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
{ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
+ {ARM_EXT_V8, 0xf57ff051, 0xfffffff3, "dmb\t%U"},
+ {ARM_EXT_V8, 0xf57ff041, 0xfffffff3, "dsb\t%U"},
{ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
{ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
{ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
@@ -1414,6 +1416,8 @@ static const struct opcode32 thumb32_opcodes[] =
/* V7 instructions. */
{ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
{ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
+ {ARM_EXT_V8, 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
+ {ARM_EXT_V8, 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
{ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
{ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
{ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
@@ -2985,6 +2989,28 @@ banked_regname (unsigned reg)
}
}
+/* Return the name of the DMB/DSB option. */
+static const char *
+data_barrier_option (unsigned option)
+{
+ switch (option & 0xf)
+ {
+ case 0xf: return "sy";
+ case 0xe: return "st";
+ case 0xd: return "ld";
+ case 0xb: return "ish";
+ case 0xa: return "ishst";
+ case 0x9: return "ishld";
+ case 0x7: return "un";
+ case 0x6: return "unst";
+ case 0x5: return "nshld";
+ case 0x3: return "osh";
+ case 0x2: return "oshst";
+ case 0x1: return "oshld";
+ default: return NULL;
+ }
+}
+
/* Print one ARM instruction from PC on INFO->STREAM. */
static void
@@ -3335,20 +3361,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
}
else
{
- switch (given & 0xf)
- {
- case 0xf: func (stream, "sy"); break;
- case 0x7: func (stream, "un"); break;
- case 0xe: func (stream, "st"); break;
- case 0x6: func (stream, "unst"); break;
- case 0xb: func (stream, "ish"); break;
- case 0xa: func (stream, "ishst"); break;
- case 0x3: func (stream, "osh"); break;
- case 0x2: func (stream, "oshst"); break;
- default:
+ const char * opt = data_barrier_option (given & 0xf);
+ if (opt != NULL)
+ func (stream, "%s", opt);
+ else
func (stream, "#%d", (int) given & 0xf);
- break;
- }
}
break;
@@ -4222,20 +4239,11 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
}
else
{
- switch (given & 0xf)
- {
- case 0xf: func (stream, "sy"); break;
- case 0x7: func (stream, "un"); break;
- case 0xe: func (stream, "st"); break;
- case 0x6: func (stream, "unst"); break;
- case 0xb: func (stream, "ish"); break;
- case 0xa: func (stream, "ishst"); break;
- case 0x3: func (stream, "osh"); break;
- case 0x2: func (stream, "oshst"); break;
- default:
- func (stream, "#%d", (int) given & 0xf);
- break;
- }
+ const char * opt = data_barrier_option (given & 0xf);
+ if (opt != NULL)
+ func (stream, "%s", opt);
+ else
+ func (stream, "#%d", (int) given & 0xf);
}
break;
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 10/21] Add support for HLT
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (8 preceding siblings ...)
2012-08-23 15:00 ` [RFA/ARM 09/21] Add support for DCPS instruction Matthew Gretton-Dann
@ 2012-08-23 15:00 ` Matthew Gretton-Dann
2012-08-23 16:35 ` Richard Earnshaw
2012-08-23 15:01 ` [RFA/ARM 11/21] Add support for LDRA and STRL instructions Matthew Gretton-Dann
` (10 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:00 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 701 bytes --]
ARMv8 adds a HLT instruction in A32 and T32.
This patch adds support for it.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (do_t_bkpt_hlt1): New function.
(do_t_hlt): New function.
(do_t_bkpt): Use do_t_bkpt_hlt1.
(insns): Add HLT.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a-bad.l: Update for HLT.
* gas/arm/armv8-a-bad.s: Likewise.
* gas/arm/armv8-a.d: Likewise.
* gas/arm/armv8-a.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (arm_opcodes): Add HLT.
(thumb_opcodes): Likewise.
[-- Attachment #2: 0010-Add-support-for-HLT.txt --]
[-- Type: text/x-patch, Size: 4396 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 1c5eb31..d98944b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10198,18 +10198,34 @@ do_t_branch (void)
inst.reloc.pc_rel = 1;
}
+/* Actually do the work for Thumb state bkpt and hlt. The only difference
+ between the two is the maximum immediate allowed - which is passed in
+ RANGE. */
static void
-do_t_bkpt (void)
+do_t_bkpt_hlt1 (int range)
{
constraint (inst.cond != COND_ALWAYS,
_("instruction is always unconditional"));
if (inst.operands[0].present)
{
- constraint (inst.operands[0].imm > 255,
+ constraint (inst.operands[0].imm > range,
_("immediate value out of range"));
inst.instruction |= inst.operands[0].imm;
- set_it_insn_type (NEUTRAL_IT_INSN);
}
+
+ set_it_insn_type (NEUTRAL_IT_INSN);
+}
+
+static void
+do_t_hlt (void)
+{
+ do_t_bkpt_hlt1 (63);
+}
+
+static void
+do_t_bkpt (void)
+{
+ do_t_bkpt_hlt1 (255);
}
static void
@@ -17974,7 +17990,9 @@ static const struct asm_opcode insns[] =
#define THUMB_VARIANT & arm_ext_v8
tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
+ TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
+ /* ARMv8 T32 only. */
#undef ARM_VARIANT
#define ARM_VARIANT NULL
TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.l b/gas/testsuite/gas/arm/armv8-a-bad.l
index e96efce..d81e475 100644
--- a/gas/testsuite/gas/arm/armv8-a-bad.l
+++ b/gas/testsuite/gas/arm/armv8-a-bad.l
@@ -7,3 +7,8 @@
.*:14: Warning: This coprocessor register access is deprecated in ARMv8
.*:17: Warning: setend use is deprecated for ARMv8
.*:20: Warning: setend use is deprecated for ARMv8
+.*:24: Error: immediate value out of range -- `hlt 0x10000'
+.*:25: Error: instruction cannot be conditional -- `hltne 0x1'
+.*:29: Error: immediate value out of range -- `hlt 64'
+.*:31: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions
+.*:31: Error: instruction is always unconditional -- `hltne 0'
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.s b/gas/testsuite/gas/arm/armv8-a-bad.s
index 33a3c17..cef9878 100644
--- a/gas/testsuite/gas/arm/armv8-a-bad.s
+++ b/gas/testsuite/gas/arm/armv8-a-bad.s
@@ -18,3 +18,14 @@
.thumb
setend le
+
+ // HLT A32
+ .arm
+ hlt 0x10000
+ hltne 0x1
+
+ // HLT T32
+ .thumb
+ hlt 64
+ it ne
+ hltne 0
diff --git a/gas/testsuite/gas/arm/armv8-a.d b/gas/testsuite/gas/arm/armv8-a.d
index 52fcf71..3f7b249 100644
--- a/gas/testsuite/gas/arm/armv8-a.d
+++ b/gas/testsuite/gas/arm/armv8-a.d
@@ -5,9 +5,14 @@
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e320f005 sevl
+0[0-9a-f]+ <[^>]+> e1000070 hlt 0x0000
+0[0-9a-f]+ <[^>]+> e100007f hlt 0x000f
+0[0-9a-f]+ <[^>]+> e10fff70 hlt 0xfff0
0[0-9a-f]+ <[^>]+> bf50 sevl
0[0-9a-f]+ <[^>]+> bf50 sevl
0[0-9a-f]+ <[^>]+> f3af 8005 sevl.w
0[0-9a-f]+ <[^>]+> f78f 8001 dcps1
0[0-9a-f]+ <[^>]+> f78f 8002 dcps2
0[0-9a-f]+ <[^>]+> f78f 8003 dcps3
+0[0-9a-f]+ <[^>]+> ba80 hlt 0x0000
+0[0-9a-f]+ <[^>]+> babf hlt 0x003f
diff --git a/gas/testsuite/gas/arm/armv8-a.s b/gas/testsuite/gas/arm/armv8-a.s
index 4e097b1..89e7c5a 100644
--- a/gas/testsuite/gas/arm/armv8-a.s
+++ b/gas/testsuite/gas/arm/armv8-a.s
@@ -5,6 +5,9 @@
.arm
foo:
sevl
+ hlt 0x0
+ hlt 0xf
+ hlt 0xfff0
.thumb
.thumb_func
@@ -15,3 +18,5 @@ bar:
dcps1
dcps2
dcps3
+ hlt 0
+ hlt 63
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 6ee016f..754556c 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -851,6 +851,8 @@ static const struct opcode32 arm_opcodes[] =
/* V8 instructions. */
{ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"},
+ {ARM_EXT_V8, 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
+
/* Virtualization Extension instructions. */
{ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
@@ -1249,6 +1251,7 @@ static const struct opcode16 thumb_opcodes[] =
/* ARM V8 instructions. */
{ARM_EXT_V8, 0xbf50, 0xffff, "sevl%c"},
+ {ARM_EXT_V8, 0xba80, 0xffc0, "hlt\t%0-5x"},
/* ARM V6K no-argument instructions. */
{ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 09/21] Add support for DCPS instruction.
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (7 preceding siblings ...)
2012-08-23 14:59 ` [RFA/ARM 07/21] Add support for new options to DMB/DSB Matthew Gretton-Dann
@ 2012-08-23 15:00 ` Matthew Gretton-Dann
2012-08-23 16:34 ` Richard Earnshaw
2012-08-23 15:00 ` [RFA/ARM 10/21] Add support for HLT Matthew Gretton-Dann
` (11 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:00 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 532 bytes --]
ARMv8 adds a DCPS instruction to T32 (in debug mode).
This patch adds support for it.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (insns): Add DCPS instruction.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a.d: Update.
* gas/arm/armv8-a.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (thumb32_opcodes): Add DCPS instruction.
[-- Attachment #2: 0009-Add-support-for-DCPS-instruction.txt --]
[-- Type: text/x-patch, Size: 1775 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index cfcdecb..1c5eb31 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -17975,6 +17975,12 @@ static const struct asm_opcode insns[] =
tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
+#undef ARM_VARIANT
+#define ARM_VARIANT NULL
+ TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
+ TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
+ TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
+
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
#undef THUMB_VARIANT
diff --git a/gas/testsuite/gas/arm/armv8-a.d b/gas/testsuite/gas/arm/armv8-a.d
index f558910..52fcf71 100644
--- a/gas/testsuite/gas/arm/armv8-a.d
+++ b/gas/testsuite/gas/arm/armv8-a.d
@@ -8,3 +8,6 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> bf50 sevl
0[0-9a-f]+ <[^>]+> bf50 sevl
0[0-9a-f]+ <[^>]+> f3af 8005 sevl.w
+0[0-9a-f]+ <[^>]+> f78f 8001 dcps1
+0[0-9a-f]+ <[^>]+> f78f 8002 dcps2
+0[0-9a-f]+ <[^>]+> f78f 8003 dcps3
diff --git a/gas/testsuite/gas/arm/armv8-a.s b/gas/testsuite/gas/arm/armv8-a.s
index 000a5a7..4e097b1 100644
--- a/gas/testsuite/gas/arm/armv8-a.s
+++ b/gas/testsuite/gas/arm/armv8-a.s
@@ -12,3 +12,6 @@ bar:
sevl
sevl.n
sevl.w
+ dcps1
+ dcps2
+ dcps3
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 5a450d7..6ee016f 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1421,6 +1421,7 @@ static const struct opcode32 thumb32_opcodes[] =
{
/* V8 instructions. */
{ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
+ {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
/* V7 instructions. */
{ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 12/21] Add support for VSEL.
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (10 preceding siblings ...)
2012-08-23 15:01 ` [RFA/ARM 11/21] Add support for LDRA and STRL instructions Matthew Gretton-Dann
@ 2012-08-23 15:01 ` Matthew Gretton-Dann
2012-08-23 16:36 ` Richard Earnshaw
2012-08-23 15:02 ` [RFA/ARM 13/21] Add support for VMAXNM/VMINNM instructions Matthew Gretton-Dann
` (8 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:01 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 726 bytes --]
ARMv8 adds a VSEL instruction to A32/T32.
This patch adds support for it.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.
(NEON_ENC_FPV8_): New define.
(do_vfp_nsyn_fpv8): New function.
(do_vsel): Likewise.
(insns): Add VSEL instructions.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a+fp.d: New testcase.
* gas/arm/armv8-a+fp.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (coprocessor_opcodes): Add VSEL.
(print_insn_coprocessor): Add new %<>c bitfield format
specifier.
[-- Attachment #2: 0012-Add-support-for-VSEL.txt --]
[-- Type: text/x-patch, Size: 5965 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 93542e3..5612d7e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12341,7 +12341,11 @@ struct neon_tab_entry
X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
- X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
+ X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
+ X(vseleq, 0xe000a00, N_INV, N_INV), \
+ X(vselvs, 0xe100a00, N_INV, N_INV), \
+ X(vselge, 0xe200a00, N_INV, N_INV), \
+ X(vselgt, 0xe300a00, N_INV, N_INV)
enum neon_opc
{
@@ -12371,6 +12375,8 @@ NEON_ENC_TAB
((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
#define NEON_ENC_DOUBLE_(X) \
((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
+#define NEON_ENC_FPV8_(X) \
+ ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
#define NEON_ENCODE(type, inst) \
do \
@@ -15841,6 +15847,33 @@ do_neon_ldx_stx (void)
else
inst.instruction |= 0xf4000000;
}
+
+/* FP v8. */
+static void
+do_vfp_nsyn_fpv8 (enum neon_shape rs)
+{
+ NEON_ENCODE (FPV8, inst);
+
+ if (rs == NS_FFF)
+ do_vfp_sp_dyadic ();
+ else
+ do_vfp_dp_rd_rn_rm ();
+
+ if (rs == NS_DDD)
+ inst.instruction |= 0x100;
+
+ inst.instruction |= 0xf0000000;
+}
+
+static void
+do_vsel (void)
+{
+ set_it_insn_type (OUTSIDE_IT_INSN);
+
+ if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
+ first_error (_("invalid instruction shape"));
+}
+
\f
/* Overall per-instruction processing. */
@@ -18044,6 +18077,17 @@ static const struct asm_opcode insns[] =
TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
+ /* FP for ARMv8. */
+#undef ARM_VARIANT
+#define ARM_VARIANT & fpu_vfp_ext_armv8
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & fpu_vfp_ext_armv8
+
+ nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
+ nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
+ nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
+ nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
+
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
#undef THUMB_VARIANT
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d
new file mode 100644
index 0000000..568d317
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a+fp.d
@@ -0,0 +1,22 @@
+#name: Valid v8-a+fp
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> fe000a00 vseleq.f32 s0, s0, s0
+0[0-9a-f]+ <[^>]+> fe500aa0 vselvs.f32 s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe2ffa0f vselge.f32 s30, s30, s30
+0[0-9a-f]+ <[^>]+> fe7ffaaf vselgt.f32 s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe000b00 vseleq.f64 d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe500ba0 vselvs.f64 d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe2ffb0f vselge.f64 d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe7ffbaf vselgt.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
+0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
+0[0-9a-f]+ <[^>]+> fe7f faaf vselgt.f32 s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe00 0b00 vseleq.f64 d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe50 0ba0 vselvs.f64 d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe2f fb0f vselge.f64 d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe7f fbaf vselgt.f64 d31, d31, d31
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.s b/gas/testsuite/gas/arm/armv8-a+fp.s
new file mode 100644
index 0000000..ec79f99
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a+fp.s
@@ -0,0 +1,24 @@
+ .syntax unified
+ .text
+ .arch armv8-a
+ .arch_extension fp
+
+ .arm
+ vseleq.f32 s0, s0, s0
+ vselvs.f32 s1, s1, s1
+ vselge.f32 s30, s30, s30
+ vselgt.f32 s31, s31, s31
+ vseleq.f64 d0, d0, d0
+ vselvs.f64 d16, d16, d16
+ vselge.f64 d15, d15, d15
+ vselgt.f64 d31, d31, d31
+
+ .thumb
+ vseleq.f32 s0, s0, s0
+ vselvs.f32 s1, s1, s1
+ vselge.f32 s30, s30, s30
+ vselgt.f32 s31, s31, s31
+ vseleq.f64 d0, d0, d0
+ vselvs.f64 d16, d16, d16
+ vselge.f64 d15, d15, d15
+ vselgt.f64 d31, d31, d31
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 9bc466c..2e4b333 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -102,6 +102,7 @@ struct opcode16
%Q print floating point precision in ldf/stf insn
%R print floating point rounding mode
+ %<bitfield>c print as a condition code (for vsel)
%<bitfield>r print as an ARM register
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
%<bitfield>ru as %<>r but each u register must be unique.
@@ -486,6 +487,10 @@ static const struct opcode32 coprocessor_opcodes[] =
{FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
{FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
+ /* FP v5. */
+ {FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
+ {FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
+
/* Generic coprocessor instructions. */
{ 0, SENTINEL_GENERIC_START, 0, "" },
{ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
@@ -2198,6 +2203,31 @@ print_insn_coprocessor (bfd_vma pc,
func (stream, "0x%lx", (value & 0xffffffffUL));
break;
+ case 'c':
+ switch (value)
+ {
+ case 0:
+ func (stream, "eq");
+ break;
+
+ case 1:
+ func (stream, "vs");
+ break;
+
+ case 2:
+ func (stream, "ge");
+ break;
+
+ case 3:
+ func (stream, "gt");
+ break;
+
+ default:
+ func (stream, "??");
+ break;
+ }
+ break;
+
case '`':
c++;
if (value == 0)
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 11/21] Add support for LDRA and STRL instructions.
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (9 preceding siblings ...)
2012-08-23 15:00 ` [RFA/ARM 10/21] Add support for HLT Matthew Gretton-Dann
@ 2012-08-23 15:01 ` Matthew Gretton-Dann
2012-08-23 16:35 ` Richard Earnshaw
2012-08-23 15:01 ` [RFA/ARM 12/21] Add support for VSEL Matthew Gretton-Dann
` (9 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:01 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 817 bytes --]
ARMv8 adds LDRA and STRL instructions (and variants) in A32 and T32.
This patch adds support for them.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (do_rm_rn): New function.
(do_strlex): Likewise.
(do_t_strlex): Likewise.
(insns): Add support for LDRA/STRL instructions.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a-bad.l: Update testcase.
* gas/arm/armv8-a-bad.s: Likewise.
* gas/arm/armv8-a.d: Likewise.
* gas/arm/armv8-a.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
(thumb32_opcodes): Likewise.
(print_arm_insn): Add support for %<>T formatter.
[-- Attachment #2: 0011-Add-support-for-LDRA-and-STRL-instructions.txt --]
[-- Type: text/x-patch, Size: 21104 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d98944b..93542e3 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7383,6 +7383,13 @@ do_rd_rm (void)
}
static void
+do_rm_rn (void)
+{
+ inst.instruction |= inst.operands[0].reg;
+ inst.instruction |= inst.operands[1].reg << 16;
+}
+
+static void
do_rd_rn (void)
{
inst.instruction |= inst.operands[0].reg << 12;
@@ -8729,6 +8736,25 @@ do_strexd (void)
inst.instruction |= inst.operands[3].reg << 16;
}
+/* ARM V8 STRL. */
+static void
+do_strlex (void)
+{
+ constraint (inst.operands[0].reg == inst.operands[1].reg
+ || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
+
+ do_rd_rm_rn ();
+}
+
+static void
+do_t_strlex (void)
+{
+ constraint (inst.operands[0].reg == inst.operands[1].reg
+ || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
+
+ do_rm_rd_rn ();
+}
+
/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
extends it to 32-bits, and adds the result to a value in another
register. You can specify a rotation by 0, 8, 16, or 24 bits
@@ -17991,6 +18017,25 @@ static const struct asm_opcode insns[] =
tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
+ TCE("ldraex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
+ TCE("ldraexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
+ ldrexd, t_ldrexd),
+ TCE("ldraexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
+ TCE("ldraexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
+ TCE("strlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
+ strlex, t_strlex),
+ TCE("strlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
+ strexd, t_strexd),
+ TCE("strlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
+ strlex, t_strlex),
+ TCE("strlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
+ strlex, t_strlex),
+ TCE("ldra", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
+ TCE("ldrab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
+ TCE("ldrah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
+ TCE("strl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
+ TCE("strlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
+ TCE("strlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
/* ARMv8 T32 only. */
#undef ARM_VARIANT
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.l b/gas/testsuite/gas/arm/armv8-a-bad.l
index d81e475..7950f0a 100644
--- a/gas/testsuite/gas/arm/armv8-a-bad.l
+++ b/gas/testsuite/gas/arm/armv8-a-bad.l
@@ -12,3 +12,85 @@
.*:29: Error: immediate value out of range -- `hlt 64'
.*:31: Warning: it blocks containing 16-bit Thumb intsructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions
.*:31: Error: instruction is always unconditional -- `hltne 0'
+.*:35: Error: r15 not allowed here -- `strlb pc,\[r0\]'
+.*:36: Error: r15 not allowed here -- `strlb r0,\[pc\]'
+.*:37: Error: r15 not allowed here -- `strlh pc,\[r0\]'
+.*:38: Error: r15 not allowed here -- `strlh r0,\[pc\]'
+.*:39: Error: r15 not allowed here -- `strl pc,\[r0\]'
+.*:40: Error: r15 not allowed here -- `strl r0,\[pc\]'
+.*:41: Error: r15 not allowed here -- `strlexb r1,pc,\[r0\]'
+.*:42: Error: r15 not allowed here -- `strlexb r1,r0,\[pc\]'
+.*:43: Error: r15 not allowed here -- `strlexb pc,r0,\[r1\]'
+.*:44: Error: registers may not be the same -- `strlexb r0,r0,\[r1\]'
+.*:45: Error: registers may not be the same -- `strlexb r0,r1,\[r0\]'
+.*:46: Error: r15 not allowed here -- `strlexh r1,pc,\[r0\]'
+.*:47: Error: r15 not allowed here -- `strlexh r1,r0,\[pc\]'
+.*:48: Error: r15 not allowed here -- `strlexh pc,r0,\[r1\]'
+.*:49: Error: registers may not be the same -- `strlexh r0,r0,\[r1\]'
+.*:50: Error: registers may not be the same -- `strlexh r0,r1,\[r0\]'
+.*:51: Error: r15 not allowed here -- `strlex r1,pc,\[r0\]'
+.*:52: Error: r15 not allowed here -- `strlex r1,r0,\[pc\]'
+.*:53: Error: r15 not allowed here -- `strlex pc,r0,\[r1\]'
+.*:54: Error: registers may not be the same -- `strlex r0,r0,\[r1\]'
+.*:55: Error: registers may not be the same -- `strlex r0,r1,\[r0\]'
+.*:56: Error: r14 not allowed here -- `strlexd r1,lr,\[r0\]'
+.*:57: Error: r15 not allowed here -- `strlexd r1,r0,\[pc\]'
+.*:58: Error: r15 not allowed here -- `strlexd pc,r0,\[r1\]'
+.*:59: Error: registers may not be the same -- `strlexd r0,r0,\[r1\]'
+.*:60: Error: registers may not be the same -- `strlexd r0,r2,\[r0\]'
+.*:61: Error: even register required -- `strlexd r0,r1,\[r2\]'
+.*:65: Error: r15 not allowed here -- `strlb pc,\[r0\]'
+.*:66: Error: r15 not allowed here -- `strlb r0,\[pc\]'
+.*:67: Error: r15 not allowed here -- `strlh pc,\[r0\]'
+.*:68: Error: r15 not allowed here -- `strlh r0,\[pc\]'
+.*:69: Error: r15 not allowed here -- `strl pc,\[r0\]'
+.*:70: Error: r15 not allowed here -- `strl r0,\[pc\]'
+.*:71: Error: r15 not allowed here -- `strlexb r1,pc,\[r0\]'
+.*:72: Error: r15 not allowed here -- `strlexb r1,r0,\[pc\]'
+.*:73: Error: r15 not allowed here -- `strlexb pc,r0,\[r1\]'
+.*:74: Error: registers may not be the same -- `strlexb r0,r0,\[r1\]'
+.*:75: Error: registers may not be the same -- `strlexb r0,r1,\[r0\]'
+.*:76: Error: r15 not allowed here -- `strlexh r1,pc,\[r0\]'
+.*:77: Error: r15 not allowed here -- `strlexh r1,r0,\[pc\]'
+.*:78: Error: r15 not allowed here -- `strlexh pc,r0,\[r1\]'
+.*:79: Error: registers may not be the same -- `strlexh r0,r0,\[r1\]'
+.*:80: Error: registers may not be the same -- `strlexh r0,r1,\[r0\]'
+.*:81: Error: r15 not allowed here -- `strlex r1,pc,\[r0\]'
+.*:82: Error: r15 not allowed here -- `strlex r1,r0,\[pc\]'
+.*:83: Error: r15 not allowed here -- `strlex pc,r0,\[r1\]'
+.*:84: Error: registers may not be the same -- `strlex r0,r0,\[r1\]'
+.*:85: Error: registers may not be the same -- `strlex r0,r1,\[r0\]'
+.*:87: Error: r15 not allowed here -- `strlexd r1,r0,\[pc\]'
+.*:88: Error: r15 not allowed here -- `strlexd pc,r0,\[r1\]'
+.*:89: Error: registers may not be the same -- `strlexd r0,r0,\[r1\]'
+.*:90: Error: registers may not be the same -- `strlexd r0,r2,\[r0\]'
+.*:95: Error: r15 not allowed here -- `ldrab pc,\[r0\]'
+.*:96: Error: r15 not allowed here -- `ldrab r0,\[pc\]'
+.*:97: Error: r15 not allowed here -- `ldrah pc,\[r0\]'
+.*:98: Error: r15 not allowed here -- `ldrah r0,\[pc\]'
+.*:99: Error: r15 not allowed here -- `ldra pc,\[r0\]'
+.*:100: Error: r15 not allowed here -- `ldra r0,\[pc\]'
+.*:101: Error: r15 not allowed here -- `ldraexb pc,\[r0\]'
+.*:102: Error: r15 not allowed here -- `ldraexb r0,\[pc\]'
+.*:103: Error: r15 not allowed here -- `ldraexh pc,\[r0\]'
+.*:104: Error: r15 not allowed here -- `ldraexh r0,\[pc\]'
+.*:105: Error: r15 not allowed here -- `ldraex pc,\[r0\]'
+.*:106: Error: r15 not allowed here -- `ldraex r0,\[pc\]'
+.*:107: Error: r14 not allowed here -- `ldraexd lr,\[r0\]'
+.*:108: Error: r15 not allowed here -- `ldraexd r0,\[pc\]'
+.*:109: Error: even register required -- `ldraexd r1,\[r2\]'
+.*:113: Error: r15 not allowed here -- `ldrab pc,\[r0\]'
+.*:114: Error: r15 not allowed here -- `ldrab r0,\[pc\]'
+.*:115: Error: r15 not allowed here -- `ldrah pc,\[r0\]'
+.*:116: Error: r15 not allowed here -- `ldrah r0,\[pc\]'
+.*:117: Error: r15 not allowed here -- `ldra pc,\[r0\]'
+.*:118: Error: r15 not allowed here -- `ldra r0,\[pc\]'
+.*:119: Error: r15 not allowed here -- `ldraexb pc,\[r0\]'
+.*:120: Error: r15 not allowed here -- `ldraexb r0,\[pc\]'
+.*:121: Error: r15 not allowed here -- `ldraexh pc,\[r0\]'
+.*:122: Error: r15 not allowed here -- `ldraexh r0,\[pc\]'
+.*:123: Error: r15 not allowed here -- `ldraex pc,\[r0\]'
+.*:124: Error: r15 not allowed here -- `ldraex r0,\[pc\]'
+.*:125: Error: r15 not allowed here -- `ldraexd r0,pc,\[r0\]'
+.*:126: Error: r15 not allowed here -- `ldraexd pc,r0,\[r0\]'
+.*:127: Error: r15 not allowed here -- `ldraexd r1,r0,\[pc\]'
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.s b/gas/testsuite/gas/arm/armv8-a-bad.s
index cef9878..2431dc2 100644
--- a/gas/testsuite/gas/arm/armv8-a-bad.s
+++ b/gas/testsuite/gas/arm/armv8-a-bad.s
@@ -29,3 +29,99 @@
hlt 64
it ne
hltne 0
+
+ // STRL A32
+ .arm
+ strlb pc, [r0]
+ strlb r0, [pc]
+ strlh pc, [r0]
+ strlh r0, [pc]
+ strl pc, [r0]
+ strl r0, [pc]
+ strlexb r1, pc, [r0]
+ strlexb r1, r0, [pc]
+ strlexb pc, r0, [r1]
+ strlexb r0, r0, [r1]
+ strlexb r0, r1, [r0]
+ strlexh r1, pc, [r0]
+ strlexh r1, r0, [pc]
+ strlexh pc, r0, [r1]
+ strlexh r0, r0, [r1]
+ strlexh r0, r1, [r0]
+ strlex r1, pc, [r0]
+ strlex r1, r0, [pc]
+ strlex pc, r0, [r1]
+ strlex r0, r0, [r1]
+ strlex r0, r1, [r0]
+ strlexd r1, lr, [r0]
+ strlexd r1, r0, [pc]
+ strlexd pc, r0, [r1]
+ strlexd r0, r0, [r1]
+ strlexd r0, r2, [r0]
+ strlexd r0, r1, [r2]
+
+ // STRL T32
+ .thumb
+ strlb pc, [r0]
+ strlb r0, [pc]
+ strlh pc, [r0]
+ strlh r0, [pc]
+ strl pc, [r0]
+ strl r0, [pc]
+ strlexb r1, pc, [r0]
+ strlexb r1, r0, [pc]
+ strlexb pc, r0, [r1]
+ strlexb r0, r0, [r1]
+ strlexb r0, r1, [r0]
+ strlexh r1, pc, [r0]
+ strlexh r1, r0, [pc]
+ strlexh pc, r0, [r1]
+ strlexh r0, r0, [r1]
+ strlexh r0, r1, [r0]
+ strlex r1, pc, [r0]
+ strlex r1, r0, [pc]
+ strlex pc, r0, [r1]
+ strlex r0, r0, [r1]
+ strlex r0, r1, [r0]
+ strlexd r1, lr, [r0]
+ strlexd r1, r0, [pc]
+ strlexd pc, r0, [r1]
+ strlexd r0, r0, [r1]
+ strlexd r0, r2, [r0]
+ strlexd r0, r1, [r2]
+
+ // LDRA A32
+ .arm
+ ldrab pc, [r0]
+ ldrab r0, [pc]
+ ldrah pc, [r0]
+ ldrah r0, [pc]
+ ldra pc, [r0]
+ ldra r0, [pc]
+ ldraexb pc, [r0]
+ ldraexb r0, [pc]
+ ldraexh pc, [r0]
+ ldraexh r0, [pc]
+ ldraex pc, [r0]
+ ldraex r0, [pc]
+ ldraexd lr, [r0]
+ ldraexd r0, [pc]
+ ldraexd r1, [r2]
+
+ // LDRA T32
+ .thumb
+ ldrab pc, [r0]
+ ldrab r0, [pc]
+ ldrah pc, [r0]
+ ldrah r0, [pc]
+ ldra pc, [r0]
+ ldra r0, [pc]
+ ldraexb pc, [r0]
+ ldraexb r0, [pc]
+ ldraexh pc, [r0]
+ ldraexh r0, [pc]
+ ldraex pc, [r0]
+ ldraex r0, [pc]
+ ldraexd r0, pc, [r0]
+ ldraexd pc, r0, [r0]
+ ldraexd r1, r0, [pc]
diff --git a/gas/testsuite/gas/arm/armv8-a.d b/gas/testsuite/gas/arm/armv8-a.d
index 3f7b249..03219ca 100644
--- a/gas/testsuite/gas/arm/armv8-a.d
+++ b/gas/testsuite/gas/arm/armv8-a.d
@@ -8,6 +8,48 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e1000070 hlt 0x0000
0[0-9a-f]+ <[^>]+> e100007f hlt 0x000f
0[0-9a-f]+ <[^>]+> e10fff70 hlt 0xfff0
+0[0-9a-f]+ <[^>]+> e1c0fc90 strlb r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1c1fc91 strlb r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1cefc9e strlb lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1e0fc90 strlh r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1e1fc91 strlh r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1eefc9e strlh lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e180fc90 strl r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e181fc91 strl r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e18efc9e strl lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1ce0e91 strlexb r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e1c01e9e strlexb r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e1c1ee90 strlexb lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e1ee0e91 strlexh r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e1e01e9e strlexh r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e1e1ee90 strlexh lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e18e0e91 strlex r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e1801e9e strlex r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e181ee90 strlex lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e1ae0e92 strlexd r0, r2, r3, \[lr\]
+0[0-9a-f]+ <[^>]+> e1a01e9c strlexd r1, ip, sp, \[r0\]
+0[0-9a-f]+ <[^>]+> e1a1ee90 strlexd lr, r0, r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1d00c9f ldrab r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1d11c9f ldrab r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1deec9f ldrab lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1f00c9f ldraexh r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1f11c9f ldraexh r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1feec9f ldraexh lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1900c9f ldra r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1911c9f ldra r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e19eec9f ldra lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1d00e9f ldraexb r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1d11e9f ldraexb r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1deee9f ldraexb lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1f00e9f ldraexh r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1f11e9f ldraexh r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1feee9f ldraexh lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1900e9f ldraex r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1911e9f ldraex r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e19eee9f ldraex lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1b00e9f ldraexd r0, r1, \[r0\]
+0[0-9a-f]+ <[^>]+> e1b12e9f ldraexd r2, r3, \[r1\]
+0[0-9a-f]+ <[^>]+> e1bece9f ldraexd ip, sp, \[lr\]
0[0-9a-f]+ <[^>]+> bf50 sevl
0[0-9a-f]+ <[^>]+> bf50 sevl
0[0-9a-f]+ <[^>]+> f3af 8005 sevl.w
@@ -16,3 +58,45 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f78f 8003 dcps3
0[0-9a-f]+ <[^>]+> ba80 hlt 0x0000
0[0-9a-f]+ <[^>]+> babf hlt 0x003f
+0[0-9a-f]+ <[^>]+> e8c0 0f8f strlb r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 1f8f strlb r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce ef8f strlb lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 0f9f strlh r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 1f9f strlh r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce ef9f strlh lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 0faf strl r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 1faf strl r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce efaf strl lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8ce 1fc0 strlexb r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 efc1 strlexb r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 0fce strlexb lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce 1fd0 strlexh r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 efd1 strlexh r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 0fde strlexh lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce 1fe0 strlex r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 efe1 strlex r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 0fee strlex lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce 11f0 strlexd r0, r1, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 eef1 strlexd r1, lr, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 00fe strlexd lr, r0, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e8d0 0f8f ldrab r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1f8f ldrab r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de ef8f ldrab lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 0f9f ldrah r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1f9f ldrah r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de ef9f ldrah lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 0faf ldra r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1faf ldra r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de efaf ldra lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 0fcf ldraexb r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1fcf ldraexb r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de efcf ldraexb lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 0fdf ldraexh r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1fdf ldraexh r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de efdf ldraexh lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 0fef ldraex r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1fef ldraex r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de efef ldraex lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 01ff ldraexd r0, r1, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1eff ldraexd r1, lr, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de e0ff ldraexd lr, r0, \[lr\]
diff --git a/gas/testsuite/gas/arm/armv8-a.s b/gas/testsuite/gas/arm/armv8-a.s
index 89e7c5a..f35d000 100644
--- a/gas/testsuite/gas/arm/armv8-a.s
+++ b/gas/testsuite/gas/arm/armv8-a.s
@@ -8,6 +8,48 @@ foo:
hlt 0x0
hlt 0xf
hlt 0xfff0
+ strlb r0, [r0]
+ strlb r1, [r1]
+ strlb r14, [r14]
+ strlh r0, [r0]
+ strlh r1, [r1]
+ strlh r14, [r14]
+ strl r0, [r0]
+ strl r1, [r1]
+ strl r14, [r14]
+ strlexb r0, r1, [r14]
+ strlexb r1, r14, [r0]
+ strlexb r14, r0, [r1]
+ strlexh r0, r1, [r14]
+ strlexh r1, r14, [r0]
+ strlexh r14, r0, [r1]
+ strlex r0, r1, [r14]
+ strlex r1, r14, [r0]
+ strlex r14, r0, [r1]
+ strlexd r0, r2, r3, [r14]
+ strlexd r1, r12, r13, [r0]
+ strlexd r14, r0, r1, [r1]
+ ldrab r0, [r0]
+ ldrab r1, [r1]
+ ldrab r14, [r14]
+ ldrah r0, [r0]
+ ldrah r1, [r1]
+ ldrah r14, [r14]
+ ldra r0, [r0]
+ ldra r1, [r1]
+ ldra r14, [r14]
+ ldraexb r0, [r0]
+ ldraexb r1, [r1]
+ ldraexb r14, [r14]
+ ldraexh r0, [r0]
+ ldraexh r1, [r1]
+ ldraexh r14, [r14]
+ ldraex r0, [r0]
+ ldraex r1, [r1]
+ ldraex r14, [r14]
+ ldraexd r0, r1, [r0]
+ ldraexd r2, r3, [r1]
+ ldraexd r12, r13, [r14]
.thumb
.thumb_func
@@ -20,3 +62,45 @@ bar:
dcps3
hlt 0
hlt 63
+ strlb r0, [r0]
+ strlb r1, [r1]
+ strlb r14, [r14]
+ strlh r0, [r0]
+ strlh r1, [r1]
+ strlh r14, [r14]
+ strl r0, [r0]
+ strl r1, [r1]
+ strl r14, [r14]
+ strlexb r0, r1, [r14]
+ strlexb r1, r14, [r0]
+ strlexb r14, r0, [r1]
+ strlexh r0, r1, [r14]
+ strlexh r1, r14, [r0]
+ strlexh r14, r0, [r1]
+ strlex r0, r1, [r14]
+ strlex r1, r14, [r0]
+ strlex r14, r0, [r1]
+ strlexd r0, r1, r1, [r14]
+ strlexd r1, r14, r14, [r0]
+ strlexd r14, r0, r0, [r1]
+ ldrab r0, [r0]
+ ldrab r1, [r1]
+ ldrab r14, [r14]
+ ldrah r0, [r0]
+ ldrah r1, [r1]
+ ldrah r14, [r14]
+ ldra r0, [r0]
+ ldra r1, [r1]
+ ldra r14, [r14]
+ ldraexb r0, [r0]
+ ldraexb r1, [r1]
+ ldraexb r14, [r14]
+ ldraexh r0, [r0]
+ ldraexh r1, [r1]
+ ldraexh r14, [r14]
+ ldraex r0, [r0]
+ ldraex r1, [r1]
+ ldraex r14, [r14]
+ ldraexd r0, r1, [r0]
+ ldraexd r1, r14, [r1]
+ ldraexd r14, r0, [r14]
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 754556c..9bc466c 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -821,6 +821,7 @@ static const struct opcode32 neon_opcodes[] =
%P print address for pli instruction.
%<bitfield>r print as an ARM register
+ %<bitfield>T print as an ARM register + 1
%<bitfield>R as %r but r15 is UNPREDICTABLE
%<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
%<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
@@ -852,7 +853,20 @@ static const struct opcode32 arm_opcodes[] =
/* V8 instructions. */
{ARM_EXT_V8, 0x0320f005, 0x0fffffff, "sevl"},
{ARM_EXT_V8, 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
-
+ {ARM_EXT_V8, 0x01800e90, 0x0ff00ff0, "strlex%c\t%12-15r, %0-3r, [%16-19R]"},
+ {ARM_EXT_V8, 0x01900e9f, 0x0ff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0x01a00e90, 0x0ff00ff0, "strlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
+ {ARM_EXT_V8, 0x01b00e9f, 0x0ff00fff, "ldraexd%c\t%12-15r, %12-15T, [%16-19R]"},
+ {ARM_EXT_V8, 0x01c00e90, 0x0ff00ff0, "strlexb%c\t%12-15r, %0-3r, [%16-19R]"},
+ {ARM_EXT_V8, 0x01d00e9f, 0x0ff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0x01e00e90, 0x0ff00ff0, "strlexh%c\t%12-15r, %0-3r, [%16-19R]"},
+ {ARM_EXT_V8, 0x01f00e9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0x0180fc90, 0x0ff0fff0, "strl%c\t%0-3r, [%16-19R]"},
+ {ARM_EXT_V8, 0x01900c9f, 0x0ff00fff, "ldra%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0x01c0fc90, 0x0ff0fff0, "strlb%c\t%0-3r, [%16-19R]"},
+ {ARM_EXT_V8, 0x01d00c9f, 0x0ff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0x01e0fc90, 0x0ff0fff0, "strlh%c\t%0-3r, [%16-19R]"},
+ {ARM_EXT_V8, 0x01f00c9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
/* Virtualization Extension instructions. */
{ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
@@ -1425,6 +1439,20 @@ static const struct opcode32 thumb32_opcodes[] =
/* V8 instructions. */
{ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
{ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
+ {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "strlb%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "strlh%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "strl%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "strlexb%c\t%0-3r, %12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "strlexh%c\t%0-3r, %12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "strlex%c\t%0-3r, %12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "strlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldrah%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "ldra%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
+ {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldraexd%c\t%12-15r, %8-11r, [%16-19R]"},
/* V7 instructions. */
{ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
@@ -3397,6 +3425,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
is_unpredictable = TRUE;
/* Fall through. */
case 'r':
+ case 'T':
+ /* We want register + 1 when decoding T. */
+ if (*c == 'T')
+ ++value;
+
if (c[1] == 'u')
{
/* Eat the 'u' character. */
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 13/21] Add support for VMAXNM/VMINNM instructions.
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (11 preceding siblings ...)
2012-08-23 15:01 ` [RFA/ARM 12/21] Add support for VSEL Matthew Gretton-Dann
@ 2012-08-23 15:02 ` Matthew Gretton-Dann
2012-08-23 16:37 ` Richard Earnshaw
2012-08-23 15:03 ` [RFA/ARM 15/21] Add support for VCVT[ANPM] Matthew Gretton-Dann
` (7 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:02 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 900 bytes --]
ARMv8 adds VMAXNM and VMINNM instructions in A32 and T32.
This patch adds support for them.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.
(vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator.
(vfp_or_neon_is_neon): Add check for SIMD for ARMv8.
(do_maxnm): New function.
(insns): Add vmaxnm, vminnm entries.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/testsuite/gas/armv8-a+fp.d: Update testcase.
* gas/testsuite/gas/armv8-a+fp.s: Likewise.
* gas/testsuite/gas/armv8-a+simd.d: New testcase.
* gas/testsuite/gas/armv8-a+simd.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
(neon_opcodes): Likewise.
[-- Attachment #2: 0013-Add-support-for-VMAXNM-VMINNM-instructions.txt --]
[-- Type: text/x-patch, Size: 10809 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 5612d7e..4c46abc 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12345,7 +12345,9 @@ struct neon_tab_entry
X(vseleq, 0xe000a00, N_INV, N_INV), \
X(vselvs, 0xe100a00, N_INV, N_INV), \
X(vselge, 0xe200a00, N_INV, N_INV), \
- X(vselgt, 0xe300a00, N_INV, N_INV)
+ X(vselgt, 0xe300a00, N_INV, N_INV), \
+ X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
+ X(vminnm, 0xe800a40, 0x3200f10, N_INV)
enum neon_opc
{
@@ -13982,7 +13984,8 @@ do_neon_dyadic_if_i_d (void)
enum vfp_or_neon_is_neon_bits
{
NEON_CHECK_CC = 1,
- NEON_CHECK_ARCH = 2
+ NEON_CHECK_ARCH = 2,
+ NEON_CHECK_ARCH8 = 4
};
/* Call this function if an instruction which may have belonged to the VFP or
@@ -14020,7 +14023,14 @@ vfp_or_neon_is_neon (unsigned check)
}
if ((check & NEON_CHECK_ARCH)
- && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
+ && !mark_feature_used (&fpu_neon_ext_v1))
+ {
+ first_error (_(BAD_FPU));
+ return FAIL;
+ }
+
+ if ((check & NEON_CHECK_ARCH8)
+ && !mark_feature_used (&fpu_neon_ext_armv8))
{
first_error (_(BAD_FPU));
return FAIL;
@@ -15874,6 +15884,20 @@ do_vsel (void)
first_error (_("invalid instruction shape"));
}
+static void
+do_vmaxnm (void)
+{
+ set_it_insn_type (OUTSIDE_IT_INSN);
+
+ if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
+ return;
+
+ if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
+ return;
+
+ neon_dyadic_misc (NT_untyped, N_F32, 0);
+}
+
\f
/* Overall per-instruction processing. */
@@ -18087,6 +18111,8 @@ static const struct asm_opcode insns[] =
nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
+ nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
+ nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d
index 568d317..c902874 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.d
+++ b/gas/testsuite/gas/arm/armv8-a+fp.d
@@ -12,6 +12,22 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fe500ba0 vselvs.f64 d16, d16, d16
0[0-9a-f]+ <[^>]+> fe2ffb0f vselge.f64 d15, d15, d15
0[0-9a-f]+ <[^>]+> fe7ffbaf vselgt.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec00aa0 vmaxnm.f32 s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8ffa0f vmaxnm.f32 s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecffaaf vmaxnm.f32 s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe800b00 vmaxnm.f64 d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec00ba0 vmaxnm.f64 d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8ffb0f vmaxnm.f64 d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecffbaf vmaxnm.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec00ae0 vminnm.f32 s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8ffa4f vminnm.f32 s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecffaef vminnm.f32 s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe800b40 vminnm.f64 d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec00be0 vminnm.f64 d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8ffb4f vminnm.f64 d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecffbef vminnm.f64 d31, d31, d31
0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
@@ -20,3 +36,19 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fe50 0ba0 vselvs.f64 d16, d16, d16
0[0-9a-f]+ <[^>]+> fe2f fb0f vselge.f64 d15, d15, d15
0[0-9a-f]+ <[^>]+> fe7f fbaf vselgt.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b00 vmaxnm.f64 d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec0 0ba0 vmaxnm.f64 d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8f fb0f vmaxnm.f64 d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecf fbaf vmaxnm.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa4f vminnm.f32 s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faef vminnm.f32 s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b40 vminnm.f64 d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec0 0be0 vminnm.f64 d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8f fb4f vminnm.f64 d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecf fbef vminnm.f64 d31, d31, d31
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.s b/gas/testsuite/gas/arm/armv8-a+fp.s
index ec79f99..e967b1a 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.s
+++ b/gas/testsuite/gas/arm/armv8-a+fp.s
@@ -12,6 +12,22 @@
vselvs.f64 d16, d16, d16
vselge.f64 d15, d15, d15
vselgt.f64 d31, d31, d31
+ vmaxnm.f32 s0, s0, s0
+ vmaxnm.f32 s1, s1, s1
+ vmaxnm.f32 s30, s30, s30
+ vmaxnm.f32 s31, s31, s31
+ vmaxnm.f64 d0, d0, d0
+ vmaxnm.f64 d16, d16, d16
+ vmaxnm.f64 d15, d15, d15
+ vmaxnm.f64 d31, d31, d31
+ vminnm.f32 s0, s0, s0
+ vminnm.f32 s1, s1, s1
+ vminnm.f32 s30, s30, s30
+ vminnm.f32 s31, s31, s31
+ vminnm.f64 d0, d0, d0
+ vminnm.f64 d16, d16, d16
+ vminnm.f64 d15, d15, d15
+ vminnm.f64 d31, d31, d31
.thumb
vseleq.f32 s0, s0, s0
@@ -22,3 +38,19 @@
vselvs.f64 d16, d16, d16
vselge.f64 d15, d15, d15
vselgt.f64 d31, d31, d31
+ vmaxnm.f32 s0, s0, s0
+ vmaxnm.f32 s1, s1, s1
+ vmaxnm.f32 s30, s30, s30
+ vmaxnm.f32 s31, s31, s31
+ vmaxnm.f64 d0, d0, d0
+ vmaxnm.f64 d16, d16, d16
+ vmaxnm.f64 d15, d15, d15
+ vmaxnm.f64 d31, d31, d31
+ vminnm.f32 s0, s0, s0
+ vminnm.f32 s1, s1, s1
+ vminnm.f32 s30, s30, s30
+ vminnm.f32 s31, s31, s31
+ vminnm.f64 d0, d0, d0
+ vminnm.f64 d16, d16, d16
+ vminnm.f64 d15, d15, d15
+ vminnm.f64 d31, d31, d31
diff --git a/gas/testsuite/gas/arm/armv8-a+simd.d b/gas/testsuite/gas/arm/armv8-a+simd.d
new file mode 100644
index 0000000..d194ccb
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a+simd.d
@@ -0,0 +1,38 @@
+#name: Valid v8-a+simdv3
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f3000f10 vmaxnm.f32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3400fb0 vmaxnm.f32 d16, d16, d16
+0[0-9a-f]+ <[^>]+> f30fff1f vmaxnm.f32 d15, d15, d15
+0[0-9a-f]+ <[^>]+> f34fffbf vmaxnm.f32 d31, d31, d31
+0[0-9a-f]+ <[^>]+> f3000f50 vmaxnm.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3400ff0 vmaxnm.f32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f30eef5e vmaxnm.f32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f34eeffe vmaxnm.f32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3200f10 vminnm.f32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3600fb0 vminnm.f32 d16, d16, d16
+0[0-9a-f]+ <[^>]+> f32fff1f vminnm.f32 d15, d15, d15
+0[0-9a-f]+ <[^>]+> f36fffbf vminnm.f32 d31, d31, d31
+0[0-9a-f]+ <[^>]+> f3200f50 vminnm.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3600ff0 vminnm.f32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f32eef5e vminnm.f32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f36eeffe vminnm.f32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff00 0f10 vmaxnm.f32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> ff40 0fb0 vmaxnm.f32 d16, d16, d16
+0[0-9a-f]+ <[^>]+> ff0f ff1f vmaxnm.f32 d15, d15, d15
+0[0-9a-f]+ <[^>]+> ff4f ffbf vmaxnm.f32 d31, d31, d31
+0[0-9a-f]+ <[^>]+> ff00 0f50 vmaxnm.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff40 0ff0 vmaxnm.f32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff0e ef5e vmaxnm.f32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff4e effe vmaxnm.f32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff20 0f10 vminnm.f32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> ff60 0fb0 vminnm.f32 d16, d16, d16
+0[0-9a-f]+ <[^>]+> ff2f ff1f vminnm.f32 d15, d15, d15
+0[0-9a-f]+ <[^>]+> ff6f ffbf vminnm.f32 d31, d31, d31
+0[0-9a-f]+ <[^>]+> ff20 0f50 vminnm.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff60 0ff0 vminnm.f32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff2e ef5e vminnm.f32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff6e effe vminnm.f32 q15, q15, q15
diff --git a/gas/testsuite/gas/arm/armv8-a+simd.s b/gas/testsuite/gas/arm/armv8-a+simd.s
new file mode 100644
index 0000000..f11103c
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a+simd.s
@@ -0,0 +1,39 @@
+ .syntax unified
+ .arch armv8-a
+ .arch_extension simd
+
+ .arm
+ vmaxnm.f32 d0, d0, d0
+ vmaxnm.f32 d16, d16, d16
+ vmaxnm.f32 d15, d15, d15
+ vmaxnm.f32 d31, d31, d31
+ vmaxnm.f32 q0, q0, q0
+ vmaxnm.f32 q8, q8, q8
+ vmaxnm.f32 q7, q7, q7
+ vmaxnm.f32 q15, q15, q15
+ vminnm.f32 d0, d0, d0
+ vminnm.f32 d16, d16, d16
+ vminnm.f32 d15, d15, d15
+ vminnm.f32 d31, d31, d31
+ vminnm.f32 q0, q0, q0
+ vminnm.f32 q8, q8, q8
+ vminnm.f32 q7, q7, q7
+ vminnm.f32 q15, q15, q15
+
+ .thumb
+ vmaxnm.f32 d0, d0, d0
+ vmaxnm.f32 d16, d16, d16
+ vmaxnm.f32 d15, d15, d15
+ vmaxnm.f32 d31, d31, d31
+ vmaxnm.f32 q0, q0, q0
+ vmaxnm.f32 q8, q8, q8
+ vmaxnm.f32 q7, q7, q7
+ vmaxnm.f32 q15, q15, q15
+ vminnm.f32 d0, d0, d0
+ vminnm.f32 d16, d16, d16
+ vminnm.f32 d15, d15, d15
+ vminnm.f32 d31, d31, d31
+ vminnm.f32 q0, q0, q0
+ vminnm.f32 q8, q8, q8
+ vminnm.f32 q7, q7, q7
+ vminnm.f32 q15, q15, q15
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 2e4b333..9757c20 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -490,6 +490,10 @@ static const struct opcode32 coprocessor_opcodes[] =
/* FP v5. */
{FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
{FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
+ {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
+ {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
+ {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
+ {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
/* Generic coprocessor instructions. */
{ 0, SENTINEL_GENERIC_START, 0, "" },
@@ -607,6 +611,8 @@ static const struct opcode32 neon_opcodes[] =
{FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
/* Three registers of the same length. */
+ {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 15/21] Add support for VCVT[ANPM]
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (12 preceding siblings ...)
2012-08-23 15:02 ` [RFA/ARM 13/21] Add support for VMAXNM/VMINNM instructions Matthew Gretton-Dann
@ 2012-08-23 15:03 ` Matthew Gretton-Dann
2012-08-23 16:39 ` Richard Earnshaw
2012-08-23 15:03 ` [RFA/ARM 14/21] Tidy up neon_cvt_flavour Matthew Gretton-Dann
` (6 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:03 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1034 bytes --]
ARMv8 adds new VCVT variants, VCVT[ANPM] to A32 and T32.
This patch adds support for them.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (NEON_ENC_TAB): Add vcvta entry.
(neon_cvt_mode): New enumeration.
(do_vfp_nsyn_cvt_fpv8): New function.
(do_neon_cvt_1): Add support for new conversions.
(do_neon_cvtr): Use neon_cvt_mode enumerator.
(do_neon_cvt): Likewise.
(do_neon_cvta): New function.
(do_neon_cvtn): Likewise.
(do_neon_cvtp): Likewise.
(do_neon_cvtm): Likewise.
(insns): Add new VCVT instructions.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a+fp.d: Update testcase.
* gas/arm/armv8-a+fp.s: Likewise.
* gas/arm/armv8-a+simd.d: Likewise.
* gas/arm/armv8-a+simd.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (coprocessor_opcodes): Add support for new VCVT
variants.
(neon_opcodes): Likewise.
[-- Attachment #2: 0015-Add-support-for-VCVT-ANPM.txt --]
[-- Type: text/x-patch, Size: 13619 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 7dc938b..f7749b3 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12347,7 +12347,8 @@ struct neon_tab_entry
X(vselge, 0xe200a00, N_INV, N_INV), \
X(vselgt, 0xe300a00, N_INV, N_INV), \
X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
- X(vminnm, 0xe800a40, 0x3200f10, N_INV)
+ X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
+ X(vcvta, 0xebc0a40, 0x3bb0000, N_INV)
enum neon_opc
{
@@ -14574,6 +14575,16 @@ get_neon_cvt_flavour (enum neon_shape rs)
#undef CVT_VAR
}
+enum neon_cvt_mode
+{
+ neon_cvt_mode_a,
+ neon_cvt_mode_n,
+ neon_cvt_mode_p,
+ neon_cvt_mode_m,
+ neon_cvt_mode_z,
+ neon_cvt_mode_x
+};
+
/* Neon-syntax VFP conversions. */
static void
@@ -14638,14 +14649,65 @@ do_vfp_nsyn_cvtz (void)
}
static void
-do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
+do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
+ enum neon_cvt_mode mode)
+{
+ int sz, op;
+ int rm;
+
+ set_it_insn_type (OUTSIDE_IT_INSN);
+
+ switch (flavour)
+ {
+ case neon_cvt_flavour_s32_f64:
+ sz = 1;
+ op = 0;
+ break;
+ case neon_cvt_flavour_s32_f32:
+ sz = 0;
+ op = 1;
+ break;
+ case neon_cvt_flavour_u32_f64:
+ sz = 1;
+ op = 0;
+ break;
+ case neon_cvt_flavour_u32_f32:
+ sz = 0;
+ op = 0;
+ break;
+ default:
+ first_error (_("invalid instruction shape"));
+ return;
+ }
+
+ switch (mode)
+ {
+ case neon_cvt_mode_a: rm = 0; break;
+ case neon_cvt_mode_n: rm = 1; break;
+ case neon_cvt_mode_p: rm = 2; break;
+ case neon_cvt_mode_m: rm = 3; break;
+ default: first_error (_("invalid rounding mode")); return;
+ }
+
+ NEON_ENCODE (FPV8, inst);
+ encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+ encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
+ inst.instruction |= sz << 8;
+ inst.instruction |= op << 7;
+ inst.instruction |= rm << 16;
+ inst.instruction |= 0xf0000000;
+ inst.is_neon = TRUE;
+}
+
+static void
+do_neon_cvt_1 (enum neon_cvt_mode mode)
{
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
/* PR11109: Handle round-to-zero for VCVT conversions. */
- if (round_to_zero
+ if (mode == neon_cvt_mode_z
&& ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
&& (flavour == neon_cvt_flavour_s32_f32
|| flavour == neon_cvt_flavour_u32_f32
@@ -14660,7 +14722,11 @@ do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
/* VFP rather than Neon conversions. */
if (flavour >= neon_cvt_flavour_first_fp)
{
- do_vfp_nsyn_cvt (rs, flavour);
+ if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
+ do_vfp_nsyn_cvt (rs, flavour);
+ else
+ do_vfp_nsyn_cvt_fpv8 (flavour, mode);
+
return;
}
@@ -14697,28 +14763,51 @@ do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
case NS_DD:
case NS_QQ:
+ if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
+ {
+ NEON_ENCODE (FLOAT, inst);
+ set_it_insn_type (OUTSIDE_IT_INSN);
+
+ if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
+ return;
+
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= LOW4 (inst.operands[1].reg);
+ inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+ inst.instruction |= neon_quad (rs) << 6;
+ inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
+ inst.instruction |= mode << 8;
+ if (thumb_mode)
+ inst.instruction |= 0xfc000000;
+ else
+ inst.instruction |= 0xf0000000;
+ }
+ else
+ {
int_encode:
- {
- unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
+ {
+ unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
- NEON_ENCODE (INTEGER, inst);
+ NEON_ENCODE (INTEGER, inst);
- if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
- return;
+ if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+ return;
- if (flavour != neon_cvt_flavour_invalid)
- inst.instruction |= enctab[flavour];
+ if (flavour != neon_cvt_flavour_invalid)
+ inst.instruction |= enctab[flavour];
- inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
- inst.instruction |= HI1 (inst.operands[0].reg) << 22;
- inst.instruction |= LOW4 (inst.operands[1].reg);
- inst.instruction |= HI1 (inst.operands[1].reg) << 5;
- inst.instruction |= neon_quad (rs) << 6;
- inst.instruction |= 2 << 18;
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= LOW4 (inst.operands[1].reg);
+ inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+ inst.instruction |= neon_quad (rs) << 6;
+ inst.instruction |= 2 << 18;
- neon_dp_fixup (&inst);
- }
- break;
+ neon_dp_fixup (&inst);
+ }
+ }
+ break;
/* Half-precision conversions for Advanced SIMD -- neon. */
case NS_QD:
@@ -14752,20 +14841,47 @@ do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
default:
/* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
- do_vfp_nsyn_cvt (rs, flavour);
+ if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
+ do_vfp_nsyn_cvt (rs, flavour);
+ else
+ do_vfp_nsyn_cvt_fpv8 (flavour, mode);
}
}
static void
do_neon_cvtr (void)
{
- do_neon_cvt_1 (FALSE);
+ do_neon_cvt_1 (neon_cvt_mode_x);
}
static void
do_neon_cvt (void)
{
- do_neon_cvt_1 (TRUE);
+ do_neon_cvt_1 (neon_cvt_mode_z);
+}
+
+static void
+do_neon_cvta (void)
+{
+ do_neon_cvt_1 (neon_cvt_mode_a);
+}
+
+static void
+do_neon_cvtn (void)
+{
+ do_neon_cvt_1 (neon_cvt_mode_n);
+}
+
+static void
+do_neon_cvtp (void)
+{
+ do_neon_cvt_1 (neon_cvt_mode_p);
+}
+
+static void
+do_neon_cvtm (void)
+{
+ do_neon_cvt_1 (neon_cvt_mode_m);
}
static void
@@ -18100,6 +18216,10 @@ static const struct asm_opcode insns[] =
nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
+ nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
+ nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
+ nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
+ nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d
index c902874..ef54277 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.d
+++ b/gas/testsuite/gas/arm/armv8-a+fp.d
@@ -28,6 +28,14 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fec00be0 vminnm.f64 d16, d16, d16
0[0-9a-f]+ <[^>]+> fe8ffb4f vminnm.f64 d15, d15, d15
0[0-9a-f]+ <[^>]+> fecffbef vminnm.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> febc0ac0 vcvta.s32.f32 s0, s0
+0[0-9a-f]+ <[^>]+> fefd0ae0 vcvtn.s32.f32 s1, s1
+0[0-9a-f]+ <[^>]+> febefa4f vcvtp.u32.f32 s30, s30
+0[0-9a-f]+ <[^>]+> fefffa6f vcvtm.u32.f32 s31, s31
+0[0-9a-f]+ <[^>]+> febc0b40 vcvta.u32.f64 s0, d0
+0[0-9a-f]+ <[^>]+> fefd0b60 vcvtn.u32.f64 s1, d16
+0[0-9a-f]+ <[^>]+> febefb4f vcvtp.u32.f64 s30, d15
+0[0-9a-f]+ <[^>]+> fefffb6f vcvtm.u32.f64 s31, d31
0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
@@ -52,3 +60,11 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fec0 0be0 vminnm.f64 d16, d16, d16
0[0-9a-f]+ <[^>]+> fe8f fb4f vminnm.f64 d15, d15, d15
0[0-9a-f]+ <[^>]+> fecf fbef vminnm.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> febc 0ac0 vcvta.s32.f32 s0, s0
+0[0-9a-f]+ <[^>]+> fefd 0ae0 vcvtn.s32.f32 s1, s1
+0[0-9a-f]+ <[^>]+> febe fa4f vcvtp.u32.f32 s30, s30
+0[0-9a-f]+ <[^>]+> feff fa6f vcvtm.u32.f32 s31, s31
+0[0-9a-f]+ <[^>]+> febc 0b40 vcvta.u32.f64 s0, d0
+0[0-9a-f]+ <[^>]+> fefd 0b60 vcvtn.u32.f64 s1, d16
+0[0-9a-f]+ <[^>]+> febe fb4f vcvtp.u32.f64 s30, d15
+0[0-9a-f]+ <[^>]+> feff fb6f vcvtm.u32.f64 s31, d31
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.s b/gas/testsuite/gas/arm/armv8-a+fp.s
index e967b1a..a95e989 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.s
+++ b/gas/testsuite/gas/arm/armv8-a+fp.s
@@ -28,6 +28,14 @@
vminnm.f64 d16, d16, d16
vminnm.f64 d15, d15, d15
vminnm.f64 d31, d31, d31
+ vcvta.s32.f32 s0, s0
+ vcvtn.s32.f32 s1, s1
+ vcvtp.u32.f32 s30, s30
+ vcvtm.u32.f32 s31, s31
+ vcvta.s32.f64 s0, d0
+ vcvtn.s32.f64 s1, d16
+ vcvtp.u32.f64 s30, d15
+ vcvtm.u32.f64 s31, d31
.thumb
vseleq.f32 s0, s0, s0
@@ -54,3 +62,11 @@
vminnm.f64 d16, d16, d16
vminnm.f64 d15, d15, d15
vminnm.f64 d31, d31, d31
+ vcvta.s32.f32 s0, s0
+ vcvtn.s32.f32 s1, s1
+ vcvtp.u32.f32 s30, s30
+ vcvtm.u32.f32 s31, s31
+ vcvta.s32.f64 s0, d0
+ vcvtn.s32.f64 s1, d16
+ vcvtp.u32.f64 s30, d15
+ vcvtm.u32.f64 s31, d31
diff --git a/gas/testsuite/gas/arm/armv8-a+simd.d b/gas/testsuite/gas/arm/armv8-a+simd.d
index d194ccb..f10140f 100644
--- a/gas/testsuite/gas/arm/armv8-a+simd.d
+++ b/gas/testsuite/gas/arm/armv8-a+simd.d
@@ -20,6 +20,14 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3600ff0 vminnm.f32 q8, q8, q8
0[0-9a-f]+ <[^>]+> f32eef5e vminnm.f32 q7, q7, q7
0[0-9a-f]+ <[^>]+> f36eeffe vminnm.f32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3bb0000 vcvta.s32.f32 d0, d0
+0[0-9a-f]+ <[^>]+> f3fb0120 vcvtn.s32.f32 d16, d16
+0[0-9a-f]+ <[^>]+> f3bbf28f vcvtp.u32.f32 d15, d15
+0[0-9a-f]+ <[^>]+> f3fbf3af vcvtm.u32.f32 d31, d31
+0[0-9a-f]+ <[^>]+> f3bb0040 vcvta.s32.f32 q0, q0
+0[0-9a-f]+ <[^>]+> f3fb0160 vcvtn.s32.f32 q8, q8
+0[0-9a-f]+ <[^>]+> f3bbe2ce vcvtp.u32.f32 q7, q7
+0[0-9a-f]+ <[^>]+> f3fbe3ee vcvtm.u32.f32 q15, q15
0[0-9a-f]+ <[^>]+> ff00 0f10 vmaxnm.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> ff40 0fb0 vmaxnm.f32 d16, d16, d16
0[0-9a-f]+ <[^>]+> ff0f ff1f vmaxnm.f32 d15, d15, d15
@@ -36,3 +44,11 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ff60 0ff0 vminnm.f32 q8, q8, q8
0[0-9a-f]+ <[^>]+> ff2e ef5e vminnm.f32 q7, q7, q7
0[0-9a-f]+ <[^>]+> ff6e effe vminnm.f32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ffbb 0000 vcvta.s32.f32 d0, d0
+0[0-9a-f]+ <[^>]+> fffb 0120 vcvtn.s32.f32 d16, d16
+0[0-9a-f]+ <[^>]+> ffbb f28f vcvtp.u32.f32 d15, d15
+0[0-9a-f]+ <[^>]+> fffb f3af vcvtm.u32.f32 d31, d31
+0[0-9a-f]+ <[^>]+> ffbb 0040 vcvta.s32.f32 q0, q0
+0[0-9a-f]+ <[^>]+> fffb 0160 vcvtn.s32.f32 q8, q8
+0[0-9a-f]+ <[^>]+> ffbb e2ce vcvtp.u32.f32 q7, q7
+0[0-9a-f]+ <[^>]+> fffb e3ee vcvtm.u32.f32 q15, q15
diff --git a/gas/testsuite/gas/arm/armv8-a+simd.s b/gas/testsuite/gas/arm/armv8-a+simd.s
index f11103c..0578902 100644
--- a/gas/testsuite/gas/arm/armv8-a+simd.s
+++ b/gas/testsuite/gas/arm/armv8-a+simd.s
@@ -19,6 +19,14 @@
vminnm.f32 q8, q8, q8
vminnm.f32 q7, q7, q7
vminnm.f32 q15, q15, q15
+ vcvta.s32.f32 d0, d0
+ vcvtn.s32.f32 d16, d16
+ vcvtp.u32.f32 d15, d15
+ vcvtm.u32.f32 d31, d31
+ vcvta.s32.f32 q0, q0
+ vcvtn.s32.f32 q8, q8
+ vcvtp.u32.f32 q7, q7
+ vcvtm.u32.f32 q15, q15
.thumb
vmaxnm.f32 d0, d0, d0
@@ -37,3 +45,11 @@
vminnm.f32 q8, q8, q8
vminnm.f32 q7, q7, q7
vminnm.f32 q15, q15, q15
+ vcvta.s32.f32 d0, d0
+ vcvtn.s32.f32 d16, d16
+ vcvtp.u32.f32 d15, d15
+ vcvtm.u32.f32 d31, d31
+ vcvta.s32.f32 q0, q0
+ vcvtn.s32.f32 q8, q8
+ vcvtp.u32.f32 q7, q7
+ vcvtm.u32.f32 q15, q15
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 9757c20..9d77432 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -494,6 +494,8 @@ static const struct opcode32 coprocessor_opcodes[] =
{FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
{FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
{FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
+ {FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
+ {FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
/* Generic coprocessor instructions. */
{ 0, SENTINEL_GENERIC_START, 0, "" },
@@ -576,6 +578,7 @@ static const struct opcode32 neon_opcodes[] =
{FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
/* Two registers, miscellaneous. */
+ {FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
@@ -2917,7 +2920,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
func (stream, "{d%d-d%d}", regno, regno + num);
}
break;
-
+
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 14/21] Tidy up neon_cvt_flavour
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (13 preceding siblings ...)
2012-08-23 15:03 ` [RFA/ARM 15/21] Add support for VCVT[ANPM] Matthew Gretton-Dann
@ 2012-08-23 15:03 ` Matthew Gretton-Dann
2012-08-23 16:38 ` Richard Earnshaw
2012-08-23 15:04 ` [RFA/ARM 16/21] Add support for VRINT instructions Matthew Gretton-Dann
` (5 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:03 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 600 bytes --]
This is a tidy-up check in which creates an enum neon_cvt_flavour, and
moves all the data which depends on it into one large 'table'. This was
done to make the code understandable for adding the new VCVT variants.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm>
* config/tc-arm.c (CVT_FLAVOUR_VAR): New define.
(CVT_VAR): New helper define.
(neon_cvt_flavour): New enumeration, function renamed...
(get_neon_cvt_flavour): ...to this.
(do_vfp_nsyn_cvt): Update to use new neon_cvt_flavour.
(do_vfp_nsyn_cvtz): Likewise.
(do_neon_cvt_1): Likewise.
[-- Attachment #2: 0014-Tidy-up-neon_cvt_flavour.txt --]
[-- Type: text/x-patch, Size: 8867 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 4c46abc..7dc938b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -14510,16 +14510,55 @@ do_neon_shll (void)
/* Check the various types for the VCVT instruction, and return which version
the current instruction is. */
-static int
-neon_cvt_flavour (enum neon_shape rs)
+#define CVT_FLAVOUR_VAR \
+ CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
+ CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
+ CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
+ CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
+ /* Half-precision conversions. */ \
+ CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
+ CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
+ /* VFP instructions. */ \
+ CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
+ CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
+ CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
+ CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
+ CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
+ CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
+ /* VFP instructions with bitshift. */ \
+ CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
+ CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
+ CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
+ CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
+ CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
+ CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
+ CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
+ CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
+
+#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
+ neon_cvt_flavour_##C,
+
+/* The different types of conversions we can do. */
+enum neon_cvt_flavour
+{
+ CVT_FLAVOUR_VAR
+ neon_cvt_flavour_invalid,
+ neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
+};
+
+#undef CVT_VAR
+
+static enum neon_cvt_flavour
+get_neon_cvt_flavour (enum neon_shape rs)
{
-#define CVT_VAR(C,X,Y) \
- et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
- if (et.type != NT_invtype) \
- { \
- inst.error = NULL; \
- return (C); \
+#define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
+ et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
+ if (et.type != NT_invtype) \
+ { \
+ inst.error = NULL; \
+ return (neon_cvt_flavour_##C); \
}
+
struct neon_type_el et;
unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
|| rs == NS_FF) ? N_VFP : 0;
@@ -14529,41 +14568,16 @@ neon_cvt_flavour (enum neon_shape rs)
here by making the size equal to the key (wider, in this case) operand. */
unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
- CVT_VAR (0, N_S32, N_F32);
- CVT_VAR (1, N_U32, N_F32);
- CVT_VAR (2, N_F32, N_S32);
- CVT_VAR (3, N_F32, N_U32);
- /* Half-precision conversions. */
- CVT_VAR (4, N_F32, N_F16);
- CVT_VAR (5, N_F16, N_F32);
-
- whole_reg = N_VFP;
-
- /* VFP instructions. */
- CVT_VAR (6, N_F32, N_F64);
- CVT_VAR (7, N_F64, N_F32);
- CVT_VAR (8, N_S32, N_F64 | key);
- CVT_VAR (9, N_U32, N_F64 | key);
- CVT_VAR (10, N_F64 | key, N_S32);
- CVT_VAR (11, N_F64 | key, N_U32);
- /* VFP instructions with bitshift. */
- CVT_VAR (12, N_F32 | key, N_S16);
- CVT_VAR (13, N_F32 | key, N_U16);
- CVT_VAR (14, N_F64 | key, N_S16);
- CVT_VAR (15, N_F64 | key, N_U16);
- CVT_VAR (16, N_S16, N_F32 | key);
- CVT_VAR (17, N_U16, N_F32 | key);
- CVT_VAR (18, N_S16, N_F64 | key);
- CVT_VAR (19, N_U16, N_F64 | key);
+ CVT_FLAVOUR_VAR;
- return -1;
+ return neon_cvt_flavour_invalid;
#undef CVT_VAR
}
/* Neon-syntax VFP conversions. */
static void
-do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
+do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
{
const char *opname = 0;
@@ -14572,29 +14586,13 @@ do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
/* Conversions with immediate bitshift. */
const char *enc[] =
{
- "ftosls",
- "ftouls",
- "fsltos",
- "fultos",
- NULL,
- NULL,
- NULL,
- NULL,
- "ftosld",
- "ftould",
- "fsltod",
- "fultod",
- "fshtos",
- "fuhtos",
- "fshtod",
- "fuhtod",
- "ftoshs",
- "ftouhs",
- "ftoshd",
- "ftouhd"
+#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
+ CVT_FLAVOUR_VAR
+ NULL
+#undef CVT_VAR
};
- if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
+ if (flavour < (int) ARRAY_SIZE (enc))
{
opname = enc[flavour];
constraint (inst.operands[0].reg != inst.operands[1].reg,
@@ -14608,21 +14606,13 @@ do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
/* Conversions without bitshift. */
const char *enc[] =
{
- "ftosis",
- "ftouis",
- "fsitos",
- "fuitos",
- "NULL",
- "NULL",
- "fcvtsd",
- "fcvtds",
- "ftosid",
- "ftouid",
- "fsitod",
- "fuitod"
+#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
+ CVT_FLAVOUR_VAR
+ NULL
+#undef CVT_VAR
};
- if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
+ if (flavour < (int) ARRAY_SIZE (enc))
opname = enc[flavour];
}
@@ -14634,22 +14624,16 @@ static void
do_vfp_nsyn_cvtz (void)
{
enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
- int flavour = neon_cvt_flavour (rs);
+ enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
const char *enc[] =
{
- "ftosizs",
- "ftouizs",
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- "ftosizd",
- "ftouizd"
+#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
+ CVT_FLAVOUR_VAR
+ NULL
+#undef CVT_VAR
};
- if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
+ if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
do_vfp_nsyn_opcode (enc[flavour]);
}
@@ -14658,12 +14642,15 @@ do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
{
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
- int flavour = neon_cvt_flavour (rs);
+ enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
/* PR11109: Handle round-to-zero for VCVT conversions. */
if (round_to_zero
&& ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
- && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
+ && (flavour == neon_cvt_flavour_s32_f32
+ || flavour == neon_cvt_flavour_u32_f32
+ || flavour == neon_cvt_flavour_s32_f64
+ || flavour == neon_cvt_flavour_u32_f64)
&& (rs == NS_FD || rs == NS_FF))
{
do_vfp_nsyn_cvtz ();
@@ -14671,7 +14658,7 @@ do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
}
/* VFP rather than Neon conversions. */
- if (flavour >= 6)
+ if (flavour >= neon_cvt_flavour_first_fp)
{
do_vfp_nsyn_cvt (rs, flavour);
return;
@@ -14694,7 +14681,7 @@ do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
goto int_encode;
immbits = 32 - inst.operands[2].imm;
NEON_ENCODE (IMMED, inst);
- if (flavour != -1)
+ if (flavour != neon_cvt_flavour_invalid)
inst.instruction |= enctab[flavour];
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
@@ -14719,8 +14706,8 @@ do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
return;
- if (flavour != -1)
- inst.instruction |= enctab[flavour];
+ if (flavour != neon_cvt_flavour_invalid)
+ inst.instruction |= enctab[flavour];
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 16/21] Add support for VRINT instructions.
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (14 preceding siblings ...)
2012-08-23 15:03 ` [RFA/ARM 14/21] Tidy up neon_cvt_flavour Matthew Gretton-Dann
@ 2012-08-23 15:04 ` Matthew Gretton-Dann
2012-08-23 16:40 ` Richard Earnshaw
2012-08-23 15:05 ` [RFA/ARM 18/21] Add support for AES instructions Matthew Gretton-Dann
` (4 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:04 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 941 bytes --]
ARMv8 adds a new VRINT instruction to A32 and T32.
This patch adds support for it.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (NEON_ENC_TAB): Add vrint entries.
(neon_cvt_mode): Add neon_cvt_mode_r.
(do_vrint_1): New function.
(do_vrint_x): Likewise.
(do_vrint_z): Likewise.
(do_vrint_r): Likewise.
(do_vrint_a): Likewise.
(do_vrint_n): Likewise.
(do_vrint_p): Likewise.
(do_vrint_m): Likewise.
(insns): Add VRINT instructions.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a+fpv5.d: Update testcase.
* gas/arm/armv8-a+fpv5.s: Likewise.
* gas/arm/armv8-a+simdv3.d: Likewise.
* gas/arm/armv8-a+simdv3.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (coprocessor_opcodes): Add VRINT.
(neon_opcodes): Likewise.
[-- Attachment #2: 0016-Add-support-for-VRINT-instructions.txt --]
[-- Type: text/x-patch, Size: 12910 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index f7749b3..3c8bd60 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12348,7 +12348,9 @@ struct neon_tab_entry
X(vselgt, 0xe300a00, N_INV, N_INV), \
X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
- X(vcvta, 0xebc0a40, 0x3bb0000, N_INV)
+ X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
+ X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
+ X(vrinta, 0xeb80a40, 0x3ba0400, N_INV)
enum neon_opc
{
@@ -14582,7 +14584,8 @@ enum neon_cvt_mode
neon_cvt_mode_p,
neon_cvt_mode_m,
neon_cvt_mode_z,
- neon_cvt_mode_x
+ neon_cvt_mode_x,
+ neon_cvt_mode_r
};
/* Neon-syntax VFP conversions. */
@@ -16001,6 +16004,125 @@ do_vmaxnm (void)
neon_dyadic_misc (NT_untyped, N_F32, 0);
}
+static void
+do_vrint_1 (enum neon_cvt_mode mode)
+{
+ enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
+ struct neon_type_el et;
+
+ if (rs == NS_NULL)
+ return;
+
+ et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+ if (et.type != NT_invtype)
+ {
+ /* VFP encodings. */
+ if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
+ || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
+ set_it_insn_type (OUTSIDE_IT_INSN);
+
+ NEON_ENCODE (FPV8, inst);
+ if (rs == NS_FF)
+ do_vfp_sp_monadic ();
+ else
+ do_vfp_dp_rd_rm ();
+
+ switch (mode)
+ {
+ case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
+ case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
+ case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
+ case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
+ case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
+ case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
+ case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
+ default: abort ();
+ }
+
+ inst.instruction |= (rs == NS_DD) << 8;
+ do_vfp_cond_or_thumb ();
+ }
+ else
+ {
+ /* Neon encodings (or something broken...). */
+ inst.error = NULL;
+ et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
+
+ if (et.type == NT_invtype)
+ return;
+
+ set_it_insn_type (OUTSIDE_IT_INSN);
+ NEON_ENCODE (FLOAT, inst);
+
+ if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
+ return;
+
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= LOW4 (inst.operands[1].reg);
+ inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+ inst.instruction |= neon_quad (rs) << 6;
+ switch (mode)
+ {
+ case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
+ case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
+ case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
+ case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
+ case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
+ case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
+ case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
+ default: abort ();
+ }
+
+ if (thumb_mode)
+ inst.instruction |= 0xfc000000;
+ else
+ inst.instruction |= 0xf0000000;
+ }
+}
+
+static void
+do_vrintx (void)
+{
+ do_vrint_1 (neon_cvt_mode_x);
+}
+
+static void
+do_vrintz (void)
+{
+ do_vrint_1 (neon_cvt_mode_z);
+}
+
+static void
+do_vrintr (void)
+{
+ do_vrint_1 (neon_cvt_mode_r);
+}
+
+static void
+do_vrinta (void)
+{
+ do_vrint_1 (neon_cvt_mode_a);
+}
+
+static void
+do_vrintn (void)
+{
+ do_vrint_1 (neon_cvt_mode_n);
+}
+
+static void
+do_vrintp (void)
+{
+ do_vrint_1 (neon_cvt_mode_p);
+}
+
+static void
+do_vrintm (void)
+{
+ do_vrint_1 (neon_cvt_mode_m);
+}
+
\f
/* Overall per-instruction processing. */
@@ -18220,6 +18342,13 @@ static const struct asm_opcode insns[] =
nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
+ nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
+ nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
+ nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
+ nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
+ nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
+ nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
+ nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d
index ef54277..e478411 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.d
+++ b/gas/testsuite/gas/arm/armv8-a+fp.d
@@ -36,6 +36,20 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fefd0b60 vcvtn.u32.f64 s1, d16
0[0-9a-f]+ <[^>]+> febefb4f vcvtp.u32.f64 s30, d15
0[0-9a-f]+ <[^>]+> fefffb6f vcvtm.u32.f64 s31, d31
+0[0-9a-f]+ <[^>]+> eeb60ac0 vrintz.f32.f32 s0, s0
+0[0-9a-f]+ <[^>]+> eef70a60 vrintx.f32.f32 s1, s1
+0[0-9a-f]+ <[^>]+> 0eb6fa4f vrintreq.f32.f32 s30, s30
+0[0-9a-f]+ <[^>]+> feb80a40 vrinta.f32.f32 s0, s0
+0[0-9a-f]+ <[^>]+> fef90a60 vrintn.f32.f32 s1, s1
+0[0-9a-f]+ <[^>]+> febafa4f vrintp.f32.f32 s30, s30
+0[0-9a-f]+ <[^>]+> fefbfa6f vrintm.f32.f32 s31, s31
+0[0-9a-f]+ <[^>]+> eeb60bc0 vrintz.f64.f64 d0, d0
+0[0-9a-f]+ <[^>]+> eeb71b41 vrintx.f64.f64 d1, d1
+0[0-9a-f]+ <[^>]+> 0ef6eb6e vrintreq.f64.f64 d30, d30
+0[0-9a-f]+ <[^>]+> feb80b40 vrinta.f64.f64 d0, d0
+0[0-9a-f]+ <[^>]+> feb91b41 vrintn.f64.f64 d1, d1
+0[0-9a-f]+ <[^>]+> fefaeb6e vrintp.f64.f64 d30, d30
+0[0-9a-f]+ <[^>]+> fefbfb6f vrintm.f64.f64 d31, d31
0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
@@ -68,3 +82,17 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fefd 0b60 vcvtn.u32.f64 s1, d16
0[0-9a-f]+ <[^>]+> febe fb4f vcvtp.u32.f64 s30, d15
0[0-9a-f]+ <[^>]+> feff fb6f vcvtm.u32.f64 s31, d31
+0[0-9a-f]+ <[^>]+> eeb6 0ac0 vrintz.f32.f32 s0, s0
+0[0-9a-f]+ <[^>]+> eef7 0a60 vrintx.f32.f32 s1, s1
+0[0-9a-f]+ <[^>]+> eeb6 fa4f vrintr.f32.f32 s30, s30
+0[0-9a-f]+ <[^>]+> feb8 0a40 vrinta.f32.f32 s0, s0
+0[0-9a-f]+ <[^>]+> fef9 0a60 vrintn.f32.f32 s1, s1
+0[0-9a-f]+ <[^>]+> feba fa4f vrintp.f32.f32 s30, s30
+0[0-9a-f]+ <[^>]+> fefb fa6f vrintm.f32.f32 s31, s31
+0[0-9a-f]+ <[^>]+> eeb6 0bc0 vrintz.f64.f64 d0, d0
+0[0-9a-f]+ <[^>]+> eeb7 1b41 vrintx.f64.f64 d1, d1
+0[0-9a-f]+ <[^>]+> eef6 eb6e vrintr.f64.f64 d30, d30
+0[0-9a-f]+ <[^>]+> feb8 0b40 vrinta.f64.f64 d0, d0
+0[0-9a-f]+ <[^>]+> feb9 1b41 vrintn.f64.f64 d1, d1
+0[0-9a-f]+ <[^>]+> fefa eb6e vrintp.f64.f64 d30, d30
+0[0-9a-f]+ <[^>]+> fefb fb6f vrintm.f64.f64 d31, d31
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.s b/gas/testsuite/gas/arm/armv8-a+fp.s
index a95e989..10a391a 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.s
+++ b/gas/testsuite/gas/arm/armv8-a+fp.s
@@ -36,6 +36,20 @@
vcvtn.s32.f64 s1, d16
vcvtp.u32.f64 s30, d15
vcvtm.u32.f64 s31, d31
+ vrintz.f32.f32 s0, s0
+ vrintx.f32.f32 s1, s1
+ vrintreq.f32.f32 s30, s30
+ vrinta.f32.f32 s0, s0
+ vrintn.f32.f32 s1, s1
+ vrintp.f32.f32 s30, s30
+ vrintm.f32.f32 s31, s31
+ vrintz.f64.f64 d0, d0
+ vrintx.f64.f64 d1, d1
+ vrintreq.f64.f64 d30, d30
+ vrinta.f64.f64 d0, d0
+ vrintn.f64.f64 d1, d1
+ vrintp.f64.f64 d30, d30
+ vrintm.f64.f64 d31, d31
.thumb
vseleq.f32 s0, s0, s0
@@ -70,3 +84,17 @@
vcvtn.s32.f64 s1, d16
vcvtp.u32.f64 s30, d15
vcvtm.u32.f64 s31, d31
+ vrintz.f32.f32 s0, s0
+ vrintx.f32.f32 s1, s1
+ vrintr.f32.f32 s30, s30
+ vrinta.f32.f32 s0, s0
+ vrintn.f32.f32 s1, s1
+ vrintp.f32.f32 s30, s30
+ vrintm.f32.f32 s31, s31
+ vrintz.f64.f64 d0, d0
+ vrintx.f64.f64 d1, d1
+ vrintr.f64.f64 d30, d30
+ vrinta.f64.f64 d0, d0
+ vrintn.f64.f64 d1, d1
+ vrintp.f64.f64 d30, d30
+ vrintm.f64.f64 d31, d31
diff --git a/gas/testsuite/gas/arm/armv8-a+simd.d b/gas/testsuite/gas/arm/armv8-a+simd.d
index f10140f..c6a4a5e 100644
--- a/gas/testsuite/gas/arm/armv8-a+simd.d
+++ b/gas/testsuite/gas/arm/armv8-a+simd.d
@@ -28,6 +28,18 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3fb0160 vcvtn.s32.f32 q8, q8
0[0-9a-f]+ <[^>]+> f3bbe2ce vcvtp.u32.f32 q7, q7
0[0-9a-f]+ <[^>]+> f3fbe3ee vcvtm.u32.f32 q15, q15
+0[0-9a-f]+ <[^>]+> f3ba0500 vrinta.f32.f32 d0, d0
+0[0-9a-f]+ <[^>]+> f3fa0420 vrintn.f32.f32 d16, d16
+0[0-9a-f]+ <[^>]+> f3baf68f vrintm.f32.f32 d15, d15
+0[0-9a-f]+ <[^>]+> f3faf7af vrintp.f32.f32 d31, d31
+0[0-9a-f]+ <[^>]+> f3ba04af vrintx.f32.f32 d0, d31
+0[0-9a-f]+ <[^>]+> f3fa058f vrintz.f32.f32 d16, d15
+0[0-9a-f]+ <[^>]+> f3ba0540 vrinta.f32.f32 q0, q0
+0[0-9a-f]+ <[^>]+> f3fa0460 vrintn.f32.f32 q8, q8
+0[0-9a-f]+ <[^>]+> f3bae6ce vrintm.f32.f32 q7, q7
+0[0-9a-f]+ <[^>]+> f3fae7ee vrintp.f32.f32 q15, q15
+0[0-9a-f]+ <[^>]+> f3ba04ee vrintx.f32.f32 q0, q15
+0[0-9a-f]+ <[^>]+> f3fa05ce vrintz.f32.f32 q8, q7
0[0-9a-f]+ <[^>]+> ff00 0f10 vmaxnm.f32 d0, d0, d0
0[0-9a-f]+ <[^>]+> ff40 0fb0 vmaxnm.f32 d16, d16, d16
0[0-9a-f]+ <[^>]+> ff0f ff1f vmaxnm.f32 d15, d15, d15
@@ -52,3 +64,15 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fffb 0160 vcvtn.s32.f32 q8, q8
0[0-9a-f]+ <[^>]+> ffbb e2ce vcvtp.u32.f32 q7, q7
0[0-9a-f]+ <[^>]+> fffb e3ee vcvtm.u32.f32 q15, q15
+0[0-9a-f]+ <[^>]+> ffba 0500 vrinta.f32.f32 d0, d0
+0[0-9a-f]+ <[^>]+> fffa 0420 vrintn.f32.f32 d16, d16
+0[0-9a-f]+ <[^>]+> ffba f68f vrintm.f32.f32 d15, d15
+0[0-9a-f]+ <[^>]+> fffa f7af vrintp.f32.f32 d31, d31
+0[0-9a-f]+ <[^>]+> ffba 04af vrintx.f32.f32 d0, d31
+0[0-9a-f]+ <[^>]+> fffa 058f vrintz.f32.f32 d16, d15
+0[0-9a-f]+ <[^>]+> ffba 0540 vrinta.f32.f32 q0, q0
+0[0-9a-f]+ <[^>]+> fffa 0460 vrintn.f32.f32 q8, q8
+0[0-9a-f]+ <[^>]+> ffba e6ce vrintm.f32.f32 q7, q7
+0[0-9a-f]+ <[^>]+> fffa e7ee vrintp.f32.f32 q15, q15
+0[0-9a-f]+ <[^>]+> ffba 04ee vrintx.f32.f32 q0, q15
+0[0-9a-f]+ <[^>]+> fffa 05ce vrintz.f32.f32 q8, q7
diff --git a/gas/testsuite/gas/arm/armv8-a+simd.s b/gas/testsuite/gas/arm/armv8-a+simd.s
index 0578902..9a08a07 100644
--- a/gas/testsuite/gas/arm/armv8-a+simd.s
+++ b/gas/testsuite/gas/arm/armv8-a+simd.s
@@ -27,6 +27,18 @@
vcvtn.s32.f32 q8, q8
vcvtp.u32.f32 q7, q7
vcvtm.u32.f32 q15, q15
+ vrinta.f32.f32 d0, d0
+ vrintn.f32.f32 d16, d16
+ vrintm.f32.f32 d15, d15
+ vrintp.f32.f32 d31, d31
+ vrintx.f32.f32 d0, d31
+ vrintz.f32.f32 d16, d15
+ vrinta.f32.f32 q0, q0
+ vrintn.f32.f32 q8, q8
+ vrintm.f32.f32 q7, q7
+ vrintp.f32.f32 q15, q15
+ vrintx.f32.f32 q0, q15
+ vrintz.f32.f32 q8, q7
.thumb
vmaxnm.f32 d0, d0, d0
@@ -53,3 +65,15 @@
vcvtn.s32.f32 q8, q8
vcvtp.u32.f32 q7, q7
vcvtm.u32.f32 q15, q15
+ vrinta.f32.f32 d0, d0
+ vrintn.f32.f32 d16, d16
+ vrintm.f32.f32 d15, d15
+ vrintp.f32.f32 d31, d31
+ vrintx.f32.f32 d0, d31
+ vrintz.f32.f32 d16, d15
+ vrinta.f32.f32 q0, q0
+ vrintn.f32.f32 q8, q8
+ vrintm.f32.f32 q7, q7
+ vrintp.f32.f32 q15, q15
+ vrintx.f32.f32 q0, q15
+ vrintz.f32.f32 q8, q7
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 9d77432..60463d1 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -496,6 +496,10 @@ static const struct opcode32 coprocessor_opcodes[] =
{FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
{FPU_VFP_EXT_ARMV8, 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
{FPU_VFP_EXT_ARMV8, 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
+ {FPU_VFP_EXT_ARMV8, 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32.f32\t%y1, %y0"},
+ {FPU_VFP_EXT_ARMV8, 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64.f64\t%z1, %z0"},
+ {FPU_VFP_EXT_ARMV8, 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32.f32\t%y1, %y0"},
+ {FPU_VFP_EXT_ARMV8, 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64.f64\t%z1, %z0"},
/* Generic coprocessor instructions. */
{ 0, SENTINEL_GENERIC_START, 0, "" },
@@ -578,6 +582,7 @@ static const struct opcode32 neon_opcodes[] =
{FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
/* Two registers, miscellaneous. */
+ {FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32.f32\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 18/21] Add support for AES instructions.
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (15 preceding siblings ...)
2012-08-23 15:04 ` [RFA/ARM 16/21] Add support for VRINT instructions Matthew Gretton-Dann
@ 2012-08-23 15:05 ` Matthew Gretton-Dann
2012-08-23 16:43 ` Richard Earnshaw
2012-08-23 15:05 ` [RFA/ARM 17/21] Add support for 16-/64-bit Floating Point conversions Matthew Gretton-Dann
` (3 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:05 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 825 bytes --]
ARMv8 adds several AES instructions for A32 and T32.
This patch adds support for these.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (NEON_ENC_TAB): Add aes entry.
(neon_type_mask): Add N_UNT.
(neon_check_type): Don't always decay typed to untyped sizes.
(do_crypto_2op_1): New function.
(do_aese): Likewise.
(do_aesd): Likewise.
(do_aesmc.8): Likewise.
(do_aesimc.8): Likewise.
(insns): Add AES instructions.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a+crypto.d: New testcase.
* gas/arm/armv8-a+crypto.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (neon_opcodes): Add support for AES instructions.
[-- Attachment #2: 0018-Add-support-for-AES-instructions.txt --]
[-- Type: text/x-patch, Size: 7484 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 6d8d18f..0214d77 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12350,7 +12350,8 @@ struct neon_tab_entry
X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
- X(vrinta, 0xeb80a40, 0x3ba0400, N_INV)
+ X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
+ X(aes, 0x3b00300, N_INV, N_INV)
enum neon_opc
{
@@ -12572,6 +12573,7 @@ enum neon_type_mask
N_KEY = 0x1000000, /* Key element (main type specifier). */
N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
+ N_UNT = 0x8000000, /* Must be explicitly untyped. */
N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
@@ -12999,10 +13001,11 @@ neon_check_type (unsigned els, enum neon_shape ns, ...)
/* If only untyped args are allowed, decay any more specific types to
them. Some instructions only care about signs for some element
sizes, so handle that properly. */
- if ((g_size == 8 && (types_allowed & N_8) != 0)
- || (g_size == 16 && (types_allowed & N_16) != 0)
- || (g_size == 32 && (types_allowed & N_32) != 0)
- || (g_size == 64 && (types_allowed & N_64) != 0))
+ if (((types_allowed & N_UNT) == 0)
+ && ((g_size == 8 && (types_allowed & N_8) != 0)
+ || (g_size == 16 && (types_allowed & N_16) != 0)
+ || (g_size == 32 && (types_allowed & N_32) != 0)
+ || (g_size == 64 && (types_allowed & N_64) != 0)))
g_type = NT_untyped;
if (pass == 0)
@@ -16155,6 +16158,57 @@ do_vrintm (void)
do_vrint_1 (neon_cvt_mode_m);
}
+/* Crypto v1 instructions. */
+static void
+do_crypto_2op_1 (unsigned elttype, int op)
+{
+ set_it_insn_type (OUTSIDE_IT_INSN);
+
+ if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
+ == NT_invtype)
+ return;
+
+ inst.error = NULL;
+
+ NEON_ENCODE (INTEGER, inst);
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= LOW4 (inst.operands[1].reg);
+ inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+ if (op != -1)
+ inst.instruction |= op << 6;
+
+ if (thumb_mode)
+ inst.instruction |= 0xfc000000;
+ else
+ inst.instruction |= 0xf0000000;
+}
+
+static void
+do_aese (void)
+{
+ do_crypto_2op_1 (N_8, 0);
+}
+
+static void
+do_aesd (void)
+{
+ do_crypto_2op_1 (N_8, 1);
+}
+
+static void
+do_aesmc (void)
+{
+ do_crypto_2op_1 (N_8, 2);
+}
+
+static void
+do_aesimc (void)
+{
+ do_crypto_2op_1 (N_8, 3);
+}
+
+
\f
/* Overall per-instruction processing. */
@@ -18382,6 +18436,18 @@ static const struct asm_opcode insns[] =
nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
+ /* Crypto v1 extensions. */
+#undef ARM_VARIANT
+#define ARM_VARIANT & fpu_crypto_ext_armv8
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & fpu_crypto_ext_armv8
+
+ nUF(aese, _aes, 2, (RNQ, RNQ), aese),
+ nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
+ nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
+ nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
+
+
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
#undef THUMB_VARIANT
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.d b/gas/testsuite/gas/arm/armv8-a+crypto.d
new file mode 100644
index 0000000..238f9b6
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.d
@@ -0,0 +1,38 @@
+#name: Valid v8-a+cryptov1
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f3b00300 aese.8 q0, q0
+0[0-9a-f]+ <[^>]+> f3b0e30e aese.8 q7, q7
+0[0-9a-f]+ <[^>]+> f3f00320 aese.8 q8, q8
+0[0-9a-f]+ <[^>]+> f3f0e32e aese.8 q15, q15
+0[0-9a-f]+ <[^>]+> f3b00340 aesd.8 q0, q0
+0[0-9a-f]+ <[^>]+> f3b0e34e aesd.8 q7, q7
+0[0-9a-f]+ <[^>]+> f3f00360 aesd.8 q8, q8
+0[0-9a-f]+ <[^>]+> f3f0e36e aesd.8 q15, q15
+0[0-9a-f]+ <[^>]+> f3b00380 aesmc.8 q0, q0
+0[0-9a-f]+ <[^>]+> f3b0e38e aesmc.8 q7, q7
+0[0-9a-f]+ <[^>]+> f3f003a0 aesmc.8 q8, q8
+0[0-9a-f]+ <[^>]+> f3f0e3ae aesmc.8 q15, q15
+0[0-9a-f]+ <[^>]+> f3b003c0 aesimc.8 q0, q0
+0[0-9a-f]+ <[^>]+> f3b0e3ce aesimc.8 q7, q7
+0[0-9a-f]+ <[^>]+> f3f003e0 aesimc.8 q8, q8
+0[0-9a-f]+ <[^>]+> f3f0e3ee aesimc.8 q15, q15
+0[0-9a-f]+ <[^>]+> ffb0 0300 aese.8 q0, q0
+0[0-9a-f]+ <[^>]+> ffb0 e30e aese.8 q7, q7
+0[0-9a-f]+ <[^>]+> fff0 0320 aese.8 q8, q8
+0[0-9a-f]+ <[^>]+> fff0 e32e aese.8 q15, q15
+0[0-9a-f]+ <[^>]+> ffb0 0340 aesd.8 q0, q0
+0[0-9a-f]+ <[^>]+> ffb0 e34e aesd.8 q7, q7
+0[0-9a-f]+ <[^>]+> fff0 0360 aesd.8 q8, q8
+0[0-9a-f]+ <[^>]+> fff0 e36e aesd.8 q15, q15
+0[0-9a-f]+ <[^>]+> ffb0 0380 aesmc.8 q0, q0
+0[0-9a-f]+ <[^>]+> ffb0 e38e aesmc.8 q7, q7
+0[0-9a-f]+ <[^>]+> fff0 03a0 aesmc.8 q8, q8
+0[0-9a-f]+ <[^>]+> fff0 e3ae aesmc.8 q15, q15
+0[0-9a-f]+ <[^>]+> ffb0 03c0 aesimc.8 q0, q0
+0[0-9a-f]+ <[^>]+> ffb0 e3ce aesimc.8 q7, q7
+0[0-9a-f]+ <[^>]+> fff0 03e0 aesimc.8 q8, q8
+0[0-9a-f]+ <[^>]+> fff0 e3ee aesimc.8 q15, q15
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.s b/gas/testsuite/gas/arm/armv8-a+crypto.s
new file mode 100644
index 0000000..4f01b79
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.s
@@ -0,0 +1,39 @@
+ .syntax unified
+ .arch armv8-a
+ .arch_extension crypto
+
+ .arm
+ aese.8 q0, q0
+ aese.8 q7, q7
+ aese.8 q8, q8
+ aese.8 q15, q15
+ aesd.8 q0, q0
+ aesd.8 q7, q7
+ aesd.8 q8, q8
+ aesd.8 q15, q15
+ aesmc.8 q0, q0
+ aesmc.8 q7, q7
+ aesmc.8 q8, q8
+ aesmc.8 q15, q15
+ aesimc.8 q0, q0
+ aesimc.8 q7, q7
+ aesimc.8 q8, q8
+ aesimc.8 q15, q15
+
+ .thumb
+ aese.8 q0, q0
+ aese.8 q7, q7
+ aese.8 q8, q8
+ aese.8 q15, q15
+ aesd.8 q0, q0
+ aesd.8 q7, q7
+ aesd.8 q8, q8
+ aesd.8 q15, q15
+ aesmc.8 q0, q0
+ aesmc.8 q7, q7
+ aesmc.8 q8, q8
+ aesmc.8 q15, q15
+ aesimc.8 q0, q0
+ aesimc.8 q7, q7
+ aesimc.8 q8, q8
+ aesimc.8 q15, q15
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index c6deac9..ef5c752 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -586,6 +586,10 @@ static const struct opcode32 neon_opcodes[] =
/* Two registers, miscellaneous. */
{FPU_NEON_EXT_ARMV8, 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32.f32\t%12-15,22R, %0-3,5R"},
{FPU_NEON_EXT_ARMV8, 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 17/21] Add support for 16-/64-bit Floating Point conversions.
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (16 preceding siblings ...)
2012-08-23 15:05 ` [RFA/ARM 18/21] Add support for AES instructions Matthew Gretton-Dann
@ 2012-08-23 15:05 ` Matthew Gretton-Dann
2012-08-23 16:42 ` Richard Earnshaw
2012-08-23 15:06 ` [RFA/ARM 20/21] Add support for SHA 3-operand instructions Matthew Gretton-Dann
` (2 subsequent siblings)
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:05 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 921 bytes --]
ARMv8 extends VCVT[TB] to support converting to/from double precision
floats.
This patch adds support for this, in the process it also fixes bugs in
the support for half-precision <-> single-precision conversions.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (el_type_type_check): Add handling for 16-bit
floating point types.
(do_neon_cvttb_2): New function.
(do_neon_cvttb_1): Likewise.
(do_neon_cvtb): Refactor to use do_neon_cvttb_1.
(do_neon_cvtt): Likewise.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a+fp.d: Update testcase.
* gas/arm/armv8-a+fp.s: Likewise.
* gas/arm/half-prec-vfpv3.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (coprocessor_opcodes): Add support for HP/DP
conversions.
[-- Attachment #2: 0017-Add-support-for-16-64-bit-Floating-Point-conversions.txt --]
[-- Type: text/x-patch, Size: 9089 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 3c8bd60..6d8d18f 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12832,7 +12832,7 @@ el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
*size = 8;
- else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
+ else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
*size = 16;
else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
*size = 32;
@@ -12851,7 +12851,7 @@ el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
*type = NT_untyped;
else if ((mask & (N_P8 | N_P16)) != 0)
*type = NT_poly;
- else if ((mask & (N_F32 | N_F64)) != 0)
+ else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
*type = NT_float;
else
return FAIL;
@@ -14888,31 +14888,63 @@ do_neon_cvtm (void)
}
static void
-do_neon_cvtb (void)
+do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
{
- inst.instruction = 0xeb20a40;
+ if (is_double)
+ mark_feature_used (&fpu_vfp_ext_armv8);
- /* The sizes are attached to the mnemonic. */
- if (inst.vectype.el[0].type != NT_invtype
- && inst.vectype.el[0].size == 16)
- inst.instruction |= 0x00010000;
+ encode_arm_vfp_reg (inst.operands[0].reg,
+ (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
+ encode_arm_vfp_reg (inst.operands[1].reg,
+ (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
+ inst.instruction |= to ? 0x10000 : 0;
+ inst.instruction |= t ? 0x80 : 0;
+ inst.instruction |= is_double ? 0x100 : 0;
+ do_vfp_cond_or_thumb ();
+}
- /* Programmer's syntax: the sizes are attached to the operands. */
- else if (inst.operands[0].vectype.type != NT_invtype
- && inst.operands[0].vectype.size == 16)
- inst.instruction |= 0x00010000;
+static void
+do_neon_cvttb_1 (bfd_boolean t)
+{
+ enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
- encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
- encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
- do_vfp_cond_or_thumb ();
+ if (rs == NS_NULL)
+ return;
+ else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
+ {
+ inst.error = NULL;
+ do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
+ }
+ else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
+ {
+ inst.error = NULL;
+ do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
+ }
+ else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
+ {
+ inst.error = NULL;
+ do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
+ }
+ else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
+ {
+ inst.error = NULL;
+ do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
+ }
+ else
+ return;
+}
+
+static void
+do_neon_cvtb (void)
+{
+ do_neon_cvttb_1 (FALSE);
}
static void
do_neon_cvtt (void)
{
- do_neon_cvtb ();
- inst.instruction |= 0x80;
+ do_neon_cvttb_1 (TRUE);
}
static void
@@ -18958,8 +18990,8 @@ static const struct asm_opcode insns[] =
nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
- nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
- nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
+ NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
+ NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
/* NOTE: All VMOV encoding is special-cased! */
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d
index e478411..bb52e0a 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.d
+++ b/gas/testsuite/gas/arm/armv8-a+fp.d
@@ -50,6 +50,14 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> feb91b41 vrintn.f64.f64 d1, d1
0[0-9a-f]+ <[^>]+> fefaeb6e vrintp.f64.f64 d30, d30
0[0-9a-f]+ <[^>]+> fefbfb6f vrintm.f64.f64 d31, d31
+0[0-9a-f]+ <[^>]+> eeb30bc0 vcvtt.f16.f64 s0, d0
+0[0-9a-f]+ <[^>]+> eef30b60 vcvtb.f16.f64 s1, d16
+0[0-9a-f]+ <[^>]+> eeb3fbcf vcvtt.f16.f64 s30, d15
+0[0-9a-f]+ <[^>]+> eef3fb6f vcvtb.f16.f64 s31, d31
+0[0-9a-f]+ <[^>]+> eeb20bc0 vcvtt.f64.f16 d0, s0
+0[0-9a-f]+ <[^>]+> eef20b60 vcvtb.f64.f16 d16, s1
+0[0-9a-f]+ <[^>]+> eeb2fbcf vcvtt.f64.f16 d15, s30
+0[0-9a-f]+ <[^>]+> eef2fb6f vcvtb.f64.f16 d31, s31
0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
@@ -96,3 +104,11 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> feb9 1b41 vrintn.f64.f64 d1, d1
0[0-9a-f]+ <[^>]+> fefa eb6e vrintp.f64.f64 d30, d30
0[0-9a-f]+ <[^>]+> fefb fb6f vrintm.f64.f64 d31, d31
+0[0-9a-f]+ <[^>]+> eeb3 0bc0 vcvtt.f16.f64 s0, d0
+0[0-9a-f]+ <[^>]+> eef3 0b60 vcvtb.f16.f64 s1, d16
+0[0-9a-f]+ <[^>]+> eeb3 fbcf vcvtt.f16.f64 s30, d15
+0[0-9a-f]+ <[^>]+> eef3 fb6f vcvtb.f16.f64 s31, d31
+0[0-9a-f]+ <[^>]+> eeb2 0bc0 vcvtt.f64.f16 d0, s0
+0[0-9a-f]+ <[^>]+> eef2 0b60 vcvtb.f64.f16 d16, s1
+0[0-9a-f]+ <[^>]+> eeb2 fbcf vcvtt.f64.f16 d15, s30
+0[0-9a-f]+ <[^>]+> eef2 fb6f vcvtb.f64.f16 d31, s31
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.s b/gas/testsuite/gas/arm/armv8-a+fp.s
index 10a391a..f99302f 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.s
+++ b/gas/testsuite/gas/arm/armv8-a+fp.s
@@ -50,6 +50,14 @@
vrintn.f64.f64 d1, d1
vrintp.f64.f64 d30, d30
vrintm.f64.f64 d31, d31
+ vcvtt.f16.f64 s0, d0
+ vcvtb.f16.f64 s1, d16
+ vcvtt.f16.f64 s30, d15
+ vcvtb.f16.f64 s31, d31
+ vcvtt.f64.f16 d0, s0
+ vcvtb.f64.f16 d16, s1
+ vcvtt.f64.f16 d15, s30
+ vcvtb.f64.f16 d31, s31
.thumb
vseleq.f32 s0, s0, s0
@@ -98,3 +106,11 @@
vrintn.f64.f64 d1, d1
vrintp.f64.f64 d30, d30
vrintm.f64.f64 d31, d31
+ vcvtt.f16.f64 s0, d0
+ vcvtb.f16.f64 s1, d16
+ vcvtt.f16.f64 s30, d15
+ vcvtb.f16.f64 s31, d31
+ vcvtt.f64.f16 d0, s0
+ vcvtb.f64.f16 d16, s1
+ vcvtt.f64.f16 d15, s30
+ vcvtb.f64.f16 d31, s31
diff --git a/gas/testsuite/gas/arm/half-prec-vfpv3.s b/gas/testsuite/gas/arm/half-prec-vfpv3.s
index acd1508..d658807 100644
--- a/gas/testsuite/gas/arm/half-prec-vfpv3.s
+++ b/gas/testsuite/gas/arm/half-prec-vfpv3.s
@@ -1,20 +1,20 @@
.text
- vcvtt.f32.f32 s0, s1
- vcvtteq.f32.f32 s2, s3
- vcvttne.f32.f32 s2, s3
- vcvttcs.f32.f32 s2, s3
- vcvttcc.f32.f32 s2, s3
- vcvttmi.f32.f32 s2, s3
- vcvttpl.f32.f32 s2, s3
- vcvttvs.f32.f32 s2, s3
- vcvttvc.f32.f32 s2, s3
- vcvtthi.f32.f32 s2, s3
- vcvttls.f32.f32 s2, s3
- vcvttge.f32.f32 s2, s3
- vcvttlt.f32.f32 s2, s3
- vcvttgt.f32.f32 s2, s3
- vcvttle.f32.f32 s2, s3
- vcvttal.f32.f32 s2, s3
+ vcvtt.f32.f16 s0, s1
+ vcvtteq.f32.f16 s2, s3
+ vcvttne.f32.f16 s2, s3
+ vcvttcs.f32.f16 s2, s3
+ vcvttcc.f32.f16 s2, s3
+ vcvttmi.f32.f16 s2, s3
+ vcvttpl.f32.f16 s2, s3
+ vcvttvs.f32.f16 s2, s3
+ vcvttvc.f32.f16 s2, s3
+ vcvtthi.f32.f16 s2, s3
+ vcvttls.f32.f16 s2, s3
+ vcvttge.f32.f16 s2, s3
+ vcvttlt.f32.f16 s2, s3
+ vcvttgt.f32.f16 s2, s3
+ vcvttle.f32.f16 s2, s3
+ vcvttal.f32.f16 s2, s3
vcvtt.f16.f32 s0, s1
vcvtteq.f16.f32 s2, s3
@@ -33,22 +33,22 @@
vcvttle.f16.f32 s2, s3
vcvttal.f16.f32 s2, s3
- vcvtb.f32.f32 s0, s1
- vcvtbeq.f32.f32 s2, s3
- vcvtbne.f32.f32 s2, s3
- vcvtbcs.f32.f32 s2, s3
- vcvtbcc.f32.f32 s2, s3
- vcvtbmi.f32.f32 s2, s3
- vcvtbpl.f32.f32 s2, s3
- vcvtbvs.f32.f32 s2, s3
- vcvtbvc.f32.f32 s2, s3
- vcvtbhi.f32.f32 s2, s3
- vcvtbls.f32.f32 s2, s3
- vcvtbge.f32.f32 s2, s3
- vcvtblt.f32.f32 s2, s3
- vcvtbgt.f32.f32 s2, s3
- vcvtble.f32.f32 s2, s3
- vcvtbal.f32.f32 s2, s3
+ vcvtb.f32.f16 s0, s1
+ vcvtbeq.f32.f16 s2, s3
+ vcvtbne.f32.f16 s2, s3
+ vcvtbcs.f32.f16 s2, s3
+ vcvtbcc.f32.f16 s2, s3
+ vcvtbmi.f32.f16 s2, s3
+ vcvtbpl.f32.f16 s2, s3
+ vcvtbvs.f32.f16 s2, s3
+ vcvtbvc.f32.f16 s2, s3
+ vcvtbhi.f32.f16 s2, s3
+ vcvtbls.f32.f16 s2, s3
+ vcvtbge.f32.f16 s2, s3
+ vcvtblt.f32.f16 s2, s3
+ vcvtbgt.f32.f16 s2, s3
+ vcvtble.f32.f16 s2, s3
+ vcvtbal.f32.f16 s2, s3
vcvtb.f16.f32 s0, s1
vcvtbeq.f16.f32 s2, s3
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 60463d1..c6deac9 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -319,6 +319,8 @@ static const struct opcode32 coprocessor_opcodes[] =
{FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
{FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
/* Half-precision conversion instructions. */
+ {FPU_VFP_EXT_ARMV8, 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
+ {FPU_VFP_EXT_ARMV8, 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
{FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
{FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 19/21] Add support for VMULL.P64
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (18 preceding siblings ...)
2012-08-23 15:06 ` [RFA/ARM 20/21] Add support for SHA 3-operand instructions Matthew Gretton-Dann
@ 2012-08-23 15:06 ` Matthew Gretton-Dann
2012-08-23 16:43 ` Richard Earnshaw
2012-08-23 16:27 ` [RFA/ARM 21/21] Add support for 2-operand SHA instructions Matthew Gretton-Dann
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:06 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 685 bytes --]
ARMv8 adds a new variant to the VMULL instruction in A32/T32.
This patch adds support for this instruction.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (neon_type_mask): Add P64 type.
(type_chk_of_el_type): Handle P64 type.
(el_type_of_type_chk): Likewise.
(do_neon_vmull): Handle VMULL.P64.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a+crypto.d: Update testcase.
* gas/arm/armv8-a+crypto.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (neon_opcodes): Handle VMULL.P64.
[-- Attachment #2: 0019-Add-support-for-VMULL.P64.txt --]
[-- Type: text/x-patch, Size: 5121 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 0214d77..627274c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12570,6 +12570,7 @@ enum neon_type_mask
N_F16 = 0x0040000,
N_F32 = 0x0080000,
N_F64 = 0x0100000,
+ N_P64 = 0x0200000,
N_KEY = 0x1000000, /* Key element (main type specifier). */
N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
@@ -12582,7 +12583,7 @@ enum neon_type_mask
N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
N_UTYP = 0,
- N_MAX_NONSPECIAL = N_F64
+ N_MAX_NONSPECIAL = N_P64
};
#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
@@ -12790,6 +12791,7 @@ type_chk_of_el_type (enum neon_el_type type, unsigned size)
{
case 8: return N_P8;
case 16: return N_P16;
+ case 64: return N_P64;
default: ;
}
break;
@@ -12838,7 +12840,7 @@ el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
*size = 16;
else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
*size = 32;
- else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
+ else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
*size = 64;
else
return FAIL;
@@ -12851,7 +12853,7 @@ el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
*type = NT_integer;
else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
*type = NT_untyped;
- else if ((mask & (N_P8 | N_P16)) != 0)
+ else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
*type = NT_poly;
else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
*type = NT_float;
@@ -15120,13 +15122,26 @@ do_neon_vmull (void)
else
{
struct neon_type_el et = neon_check_type (3, NS_QDD,
- N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
+ N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
+
if (et.type == NT_poly)
NEON_ENCODE (POLY, inst);
else
NEON_ENCODE (INTEGER, inst);
- /* For polynomial encoding, size field must be 0b00 and the U bit must be
- zero. Should be OK as-is. */
+
+ /* For polynomial encoding the U bit must be zero, and the size must
+ be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
+ obviously, as 0b10). */
+ if (et.size == 64)
+ {
+ /* Check we're on the correct architecture. */
+ if (!mark_feature_used (&fpu_crypto_ext_armv8))
+ inst.error =
+ _("Instruction form not available on this architecture.");
+
+ et.size = 32;
+ }
+
neon_mixed_length (et, et.size);
}
}
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.d b/gas/testsuite/gas/arm/armv8-a+crypto.d
index 238f9b6..bfff964 100644
--- a/gas/testsuite/gas/arm/armv8-a+crypto.d
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.d
@@ -4,6 +4,8 @@
.*: +file format .*arm.*
Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f2a00e00 vmull.p64 q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2efeeaf vmull.p64 q15, d31, d31
0[0-9a-f]+ <[^>]+> f3b00300 aese.8 q0, q0
0[0-9a-f]+ <[^>]+> f3b0e30e aese.8 q7, q7
0[0-9a-f]+ <[^>]+> f3f00320 aese.8 q8, q8
@@ -20,6 +22,8 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3b0e3ce aesimc.8 q7, q7
0[0-9a-f]+ <[^>]+> f3f003e0 aesimc.8 q8, q8
0[0-9a-f]+ <[^>]+> f3f0e3ee aesimc.8 q15, q15
+0[0-9a-f]+ <[^>]+> efa0 0e00 vmull.p64 q0, d0, d0
+0[0-9a-f]+ <[^>]+> efef eeaf vmull.p64 q15, d31, d31
0[0-9a-f]+ <[^>]+> ffb0 0300 aese.8 q0, q0
0[0-9a-f]+ <[^>]+> ffb0 e30e aese.8 q7, q7
0[0-9a-f]+ <[^>]+> fff0 0320 aese.8 q8, q8
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.s b/gas/testsuite/gas/arm/armv8-a+crypto.s
index 4f01b79..03b5c41 100644
--- a/gas/testsuite/gas/arm/armv8-a+crypto.s
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.s
@@ -3,6 +3,8 @@
.arch_extension crypto
.arm
+ vmull.p64 q0, d0, d0
+ vmull.p64 q15, d31, d31
aese.8 q0, q0
aese.8 q7, q7
aese.8 q8, q8
@@ -21,6 +23,8 @@
aesimc.8 q15, q15
.thumb
+ vmull.p64 q0, d0, d0
+ vmull.p64 q15, d31, d31
aese.8 q0, q0
aese.8 q7, q7
aese.8 q8, q8
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index ef5c752..c0a6479 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -757,6 +757,7 @@ static const struct opcode32 neon_opcodes[] =
{FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
/* Three registers of different lengths. */
+ {FPU_CRYPTO_EXT_ARMV8, 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 20/21] Add support for SHA 3-operand instructions
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (17 preceding siblings ...)
2012-08-23 15:05 ` [RFA/ARM 17/21] Add support for 16-/64-bit Floating Point conversions Matthew Gretton-Dann
@ 2012-08-23 15:06 ` Matthew Gretton-Dann
2012-08-23 16:45 ` Richard Earnshaw
2012-08-23 15:06 ` [RFA/ARM 19/21] Add support for VMULL.P64 Matthew Gretton-Dann
2012-08-23 16:27 ` [RFA/ARM 21/21] Add support for 2-operand SHA instructions Matthew Gretton-Dann
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 15:06 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 832 bytes --]
ARMv8 adds various SHA 3-operand instructions to A32 and T32.
This patch adds support for them.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
(do_crypto_3op_1): New function.
(do_sha1c): Likewise.
(do_sha1p): Likewise.
(do_sha1m): Likewise.
(do_sha1su0): Likewise.
(do_sha256h): Likewise.
(do_sha256h2): Likewise.
(do_sha256su1): Likewise.
(insns): Add SHA 3 operand instructions.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a+crypto.d: Update testcase.
* gas/arm/armv8-a+crypto.s: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
[-- Attachment #2: 0020-Add-support-for-SHA-3-operand-instructions.txt --]
[-- Type: text/x-patch, Size: 9242 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 627274c..b648bca 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12351,7 +12351,8 @@ struct neon_tab_entry
X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
- X(aes, 0x3b00300, N_INV, N_INV)
+ X(aes, 0x3b00300, N_INV, N_INV), \
+ X(sha3op, 0x2000c00, N_INV, N_INV)
enum neon_opc
{
@@ -16200,6 +16201,21 @@ do_crypto_2op_1 (unsigned elttype, int op)
}
static void
+do_crypto_3op_1 (int u, int op)
+{
+ set_it_insn_type (OUTSIDE_IT_INSN);
+
+ if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
+ N_32 | N_UNT | N_KEY).type == NT_invtype)
+ return;
+
+ inst.error = NULL;
+
+ NEON_ENCODE (INTEGER, inst);
+ neon_three_same (1, u, 8 << op);
+}
+
+static void
do_aese (void)
{
do_crypto_2op_1 (N_8, 0);
@@ -16223,7 +16239,47 @@ do_aesimc (void)
do_crypto_2op_1 (N_8, 3);
}
+static void
+do_sha1c (void)
+{
+ do_crypto_3op_1 (0, 0);
+}
+
+static void
+do_sha1p (void)
+{
+ do_crypto_3op_1 (0, 1);
+}
+
+static void
+do_sha1m (void)
+{
+ do_crypto_3op_1 (0, 2);
+}
+
+static void
+do_sha1su0 (void)
+{
+ do_crypto_3op_1 (0, 3);
+}
+static void
+do_sha256h (void)
+{
+ do_crypto_3op_1 (1, 0);
+}
+
+static void
+do_sha256h2 (void)
+{
+ do_crypto_3op_1 (1, 1);
+}
+
+static void
+do_sha256su1 (void)
+{
+ do_crypto_3op_1 (1, 2);
+}
\f
/* Overall per-instruction processing. */
@@ -18461,7 +18517,13 @@ static const struct asm_opcode insns[] =
nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
-
+ nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
+ nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
+ nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
+ nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
+ nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
+ nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
+ nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.d b/gas/testsuite/gas/arm/armv8-a+crypto.d
index bfff964..f0ed1f4 100644
--- a/gas/testsuite/gas/arm/armv8-a+crypto.d
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.d
@@ -22,6 +22,34 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3b0e3ce aesimc.8 q7, q7
0[0-9a-f]+ <[^>]+> f3f003e0 aesimc.8 q8, q8
0[0-9a-f]+ <[^>]+> f3f0e3ee aesimc.8 q15, q15
+0[0-9a-f]+ <[^>]+> f2000c40 sha1c.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f20eec4e sha1c.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f2400ce0 sha1c.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f24eecee sha1c.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> f2100c40 sha1p.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f21eec4e sha1p.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f2500ce0 sha1p.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f25eecee sha1p.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> f2200c40 sha1m.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f22eec4e sha1m.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f2600ce0 sha1m.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f26eecee sha1m.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> f2300c40 sha1su0.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f23eec4e sha1su0.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f2700ce0 sha1su0.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f27eecee sha1su0.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3000c40 sha256h.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f30eec4e sha256h.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f3400ce0 sha256h.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f34eecee sha256h.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3100c40 sha256h2.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f31eec4e sha256h2.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f3500ce0 sha256h2.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f35eecee sha256h2.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3200c40 sha256su1.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f32eec4e sha256su1.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f3600ce0 sha256su1.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f36eecee sha256su1.32 q15, q15, q15
0[0-9a-f]+ <[^>]+> efa0 0e00 vmull.p64 q0, d0, d0
0[0-9a-f]+ <[^>]+> efef eeaf vmull.p64 q15, d31, d31
0[0-9a-f]+ <[^>]+> ffb0 0300 aese.8 q0, q0
@@ -40,3 +68,31 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ffb0 e3ce aesimc.8 q7, q7
0[0-9a-f]+ <[^>]+> fff0 03e0 aesimc.8 q8, q8
0[0-9a-f]+ <[^>]+> fff0 e3ee aesimc.8 q15, q15
+0[0-9a-f]+ <[^>]+> ef00 0c40 sha1c.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ef0e ec4e sha1c.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ef40 0ce0 sha1c.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ef4e ecee sha1c.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ef10 0c40 sha1p.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ef1e ec4e sha1p.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ef50 0ce0 sha1p.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ef5e ecee sha1p.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ef20 0c40 sha1m.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ef2e ec4e sha1m.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ef60 0ce0 sha1m.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ef6e ecee sha1m.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ef30 0c40 sha1su0.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ef3e ec4e sha1su0.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ef70 0ce0 sha1su0.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ef7e ecee sha1su0.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff00 0c40 sha256h.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff0e ec4e sha256h.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff40 0ce0 sha256h.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff4e ecee sha256h.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff10 0c40 sha256h2.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff1e ec4e sha256h2.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff50 0ce0 sha256h2.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff5e ecee sha256h2.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff20 0c40 sha256su1.32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff2e ec4e sha256su1.32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff60 0ce0 sha256su1.32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff6e ecee sha256su1.32 q15, q15, q15
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.s b/gas/testsuite/gas/arm/armv8-a+crypto.s
index 03b5c41..f6aac5a 100644
--- a/gas/testsuite/gas/arm/armv8-a+crypto.s
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.s
@@ -21,6 +21,35 @@
aesimc.8 q7, q7
aesimc.8 q8, q8
aesimc.8 q15, q15
+ sha1c.32 q0, q0, q0
+ sha1c.32 q7, q7, q7
+ sha1c.32 q8, q8, q8
+ sha1c.32 q15, q15, q15
+ sha1p.32 q0, q0, q0
+ sha1p.32 q7, q7, q7
+ sha1p.32 q8, q8, q8
+ sha1p.32 q15, q15, q15
+ sha1m.32 q0, q0, q0
+ sha1m.32 q7, q7, q7
+ sha1m.32 q8, q8, q8
+ sha1m.32 q15, q15, q15
+ sha1su0.32 q0, q0, q0
+ sha1su0.32 q7, q7, q7
+ sha1su0.32 q8, q8, q8
+ sha1su0.32 q15, q15, q15
+ sha256h.32 q0, q0, q0
+ sha256h.32 q7, q7, q7
+ sha256h.32 q8, q8, q8
+ sha256h.32 q15, q15, q15
+ sha256h2.32 q0, q0, q0
+ sha256h2.32 q7, q7, q7
+ sha256h2.32 q8, q8, q8
+ sha256h2.32 q15, q15, q15
+ sha256su1.32 q0, q0, q0
+ sha256su1.32 q7, q7, q7
+ sha256su1.32 q8, q8, q8
+ sha256su1.32 q15, q15, q15
+
.thumb
vmull.p64 q0, d0, d0
@@ -41,3 +70,31 @@
aesimc.8 q7, q7
aesimc.8 q8, q8
aesimc.8 q15, q15
+ sha1c.32 q0, q0, q0
+ sha1c.32 q7, q7, q7
+ sha1c.32 q8, q8, q8
+ sha1c.32 q15, q15, q15
+ sha1p.32 q0, q0, q0
+ sha1p.32 q7, q7, q7
+ sha1p.32 q8, q8, q8
+ sha1p.32 q15, q15, q15
+ sha1m.32 q0, q0, q0
+ sha1m.32 q7, q7, q7
+ sha1m.32 q8, q8, q8
+ sha1m.32 q15, q15, q15
+ sha1su0.32 q0, q0, q0
+ sha1su0.32 q7, q7, q7
+ sha1su0.32 q8, q8, q8
+ sha1su0.32 q15, q15, q15
+ sha256h.32 q0, q0, q0
+ sha256h.32 q7, q7, q7
+ sha256h.32 q8, q8, q8
+ sha256h.32 q15, q15, q15
+ sha256h2.32 q0, q0, q0
+ sha256h2.32 q7, q7, q7
+ sha256h2.32 q8, q8, q8
+ sha256h2.32 q15, q15, q15
+ sha256su1.32 q0, q0, q0
+ sha256su1.32 q7, q7, q7
+ sha256su1.32 q8, q8, q8
+ sha256su1.32 q15, q15, q15
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index c0a6479..97a96d1 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -625,6 +625,13 @@ static const struct opcode32 neon_opcodes[] =
{FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
/* Three registers of the same length. */
+ {FPU_CRYPTO_EXT_ARMV8, 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
^ permalink raw reply [flat|nested] 43+ messages in thread
* [RFA/ARM 21/21] Add support for 2-operand SHA instructions
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
` (19 preceding siblings ...)
2012-08-23 15:06 ` [RFA/ARM 19/21] Add support for VMULL.P64 Matthew Gretton-Dann
@ 2012-08-23 16:27 ` Matthew Gretton-Dann
2012-08-23 17:07 ` Richard Earnshaw
20 siblings, 1 reply; 43+ messages in thread
From: Matthew Gretton-Dann @ 2012-08-23 16:27 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 696 bytes --]
ARMv8 adds various 2-operand SHA instructions.
This patch adds support for them.
gas/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.
(do_sha1h): New function.
(do_sha1su1): Likewise.
(do_sha256su0): Likewise.
(insns): Add 2 operand SHA instructions.
gas/testsuite/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a+crypto.s: Update testcase.
* gas/arm/armv8-a+crypto.d: Likewise.
opcodes/ChangeLog:
2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
[-- Attachment #2: 0021-Add-support-for-2-operand-SHA-instructions.txt --]
[-- Type: text/x-patch, Size: 5381 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index b648bca..ad4018b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12352,7 +12352,9 @@ struct neon_tab_entry
X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
X(aes, 0x3b00300, N_INV, N_INV), \
- X(sha3op, 0x2000c00, N_INV, N_INV)
+ X(sha3op, 0x2000c00, N_INV, N_INV), \
+ X(sha1h, 0x3b902c0, N_INV, N_INV), \
+ X(sha2op, 0x3ba0380, N_INV, N_INV)
enum neon_opc
{
@@ -16280,6 +16282,24 @@ do_sha256su1 (void)
{
do_crypto_3op_1 (1, 2);
}
+
+static void
+do_sha1h (void)
+{
+ do_crypto_2op_1 (N_32, -1);
+}
+
+static void
+do_sha1su1 (void)
+{
+ do_crypto_2op_1 (N_32, 0);
+}
+
+static void
+do_sha256su0 (void)
+{
+ do_crypto_2op_1 (N_32, 1);
+}
\f
/* Overall per-instruction processing. */
@@ -18524,6 +18544,9 @@ static const struct asm_opcode insns[] =
nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
+ nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
+ nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
+ nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.d b/gas/testsuite/gas/arm/armv8-a+crypto.d
index f0ed1f4..d5b2b4b 100644
--- a/gas/testsuite/gas/arm/armv8-a+crypto.d
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.d
@@ -50,6 +50,18 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f32eec4e sha256su1.32 q7, q7, q7
0[0-9a-f]+ <[^>]+> f3600ce0 sha256su1.32 q8, q8, q8
0[0-9a-f]+ <[^>]+> f36eecee sha256su1.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3b902c0 sha1h.32 q0, q0
+0[0-9a-f]+ <[^>]+> f3b9e2ce sha1h.32 q7, q7
+0[0-9a-f]+ <[^>]+> f3f902e0 sha1h.32 q8, q8
+0[0-9a-f]+ <[^>]+> f3f9e2ee sha1h.32 q15, q15
+0[0-9a-f]+ <[^>]+> f3ba0380 sha1su1.32 q0, q0
+0[0-9a-f]+ <[^>]+> f3bae38e sha1su1.32 q7, q7
+0[0-9a-f]+ <[^>]+> f3fa03a0 sha1su1.32 q8, q8
+0[0-9a-f]+ <[^>]+> f3fae3ae sha1su1.32 q15, q15
+0[0-9a-f]+ <[^>]+> f3ba03c0 sha256su0.32 q0, q0
+0[0-9a-f]+ <[^>]+> f3bae3ce sha256su0.32 q7, q7
+0[0-9a-f]+ <[^>]+> f3fa03e0 sha256su0.32 q8, q8
+0[0-9a-f]+ <[^>]+> f3fae3ee sha256su0.32 q15, q15
0[0-9a-f]+ <[^>]+> efa0 0e00 vmull.p64 q0, d0, d0
0[0-9a-f]+ <[^>]+> efef eeaf vmull.p64 q15, d31, d31
0[0-9a-f]+ <[^>]+> ffb0 0300 aese.8 q0, q0
@@ -96,3 +108,15 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ff2e ec4e sha256su1.32 q7, q7, q7
0[0-9a-f]+ <[^>]+> ff60 0ce0 sha256su1.32 q8, q8, q8
0[0-9a-f]+ <[^>]+> ff6e ecee sha256su1.32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ffb9 02c0 sha1h.32 q0, q0
+0[0-9a-f]+ <[^>]+> ffb9 e2ce sha1h.32 q7, q7
+0[0-9a-f]+ <[^>]+> fff9 02e0 sha1h.32 q8, q8
+0[0-9a-f]+ <[^>]+> fff9 e2ee sha1h.32 q15, q15
+0[0-9a-f]+ <[^>]+> ffba 0380 sha1su1.32 q0, q0
+0[0-9a-f]+ <[^>]+> ffba e38e sha1su1.32 q7, q7
+0[0-9a-f]+ <[^>]+> fffa 03a0 sha1su1.32 q8, q8
+0[0-9a-f]+ <[^>]+> fffa e3ae sha1su1.32 q15, q15
+0[0-9a-f]+ <[^>]+> ffba 03c0 sha256su0.32 q0, q0
+0[0-9a-f]+ <[^>]+> ffba e3ce sha256su0.32 q7, q7
+0[0-9a-f]+ <[^>]+> fffa 03e0 sha256su0.32 q8, q8
+0[0-9a-f]+ <[^>]+> fffa e3ee sha256su0.32 q15, q15
diff --git a/gas/testsuite/gas/arm/armv8-a+crypto.s b/gas/testsuite/gas/arm/armv8-a+crypto.s
index f6aac5a..679f604 100644
--- a/gas/testsuite/gas/arm/armv8-a+crypto.s
+++ b/gas/testsuite/gas/arm/armv8-a+crypto.s
@@ -49,7 +49,18 @@
sha256su1.32 q7, q7, q7
sha256su1.32 q8, q8, q8
sha256su1.32 q15, q15, q15
-
+ sha1h.32 q0, q0
+ sha1h.32 q7, q7
+ sha1h.32 q8, q8
+ sha1h.32 q15, q15
+ sha1su1.32 q0, q0
+ sha1su1.32 q7, q7
+ sha1su1.32 q8, q8
+ sha1su1.32 q15, q15
+ sha256su0.32 q0, q0
+ sha256su0.32 q7, q7
+ sha256su0.32 q8, q8
+ sha256su0.32 q15, q15
.thumb
vmull.p64 q0, d0, d0
@@ -98,3 +109,15 @@
sha256su1.32 q7, q7, q7
sha256su1.32 q8, q8, q8
sha256su1.32 q15, q15, q15
+ sha1h.32 q0, q0
+ sha1h.32 q7, q7
+ sha1h.32 q8, q8
+ sha1h.32 q15, q15
+ sha1su1.32 q0, q0
+ sha1su1.32 q7, q7
+ sha1su1.32 q8, q8
+ sha1su1.32 q15, q15
+ sha256su0.32 q0, q0
+ sha256su0.32 q7, q7
+ sha256su0.32 q8, q8
+ sha256su0.32 q15, q15
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 97a96d1..8a7dc0f 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -590,6 +590,9 @@ static const struct opcode32 neon_opcodes[] =
{FPU_CRYPTO_EXT_ARMV8, 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
{FPU_CRYPTO_EXT_ARMV8, 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
{FPU_CRYPTO_EXT_ARMV8, 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
+ {FPU_CRYPTO_EXT_ARMV8, 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
{FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
{FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 01/21] Add command line and object file support for ARMv8-A
2012-08-23 14:55 ` [RFA/ARM 01/21] Add command line and object file support for ARMv8-A Matthew Gretton-Dann
@ 2012-08-23 16:28 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:28 UTC (permalink / raw)
To: binutils
On 23/08/12 15:54, Matthew Gretton-Dann wrote:
>
> This patch adds the basic infrastructure to support ARMv8 A32/T32
> instruction sets in binutils. It also contains the necessary changes to
> output the correct attributes.
>
> A new architecture is added: -march=armv8-a.
>
> New architecture extensions are added:
> +crypto (Crypto extensions implies +fp+simd)
> +fp (FP)
> +simd (Advanced SIMD Extensions implies +fp)
>
> We also update the attributes emitted by the tools to support these new
> features.
>
> The ABI adds new values to Tag_CPU_arch, Tag_FP_arch, and
> Tag_Advanced_SIMD_arch for ARMv8. It also changes the meaning of
> Tag_FP_HP_extension so that for VFPv4/SIMDv2 the appropriate value is
> now 0 instead of 1.
>
> OK?
>
OK.
R.
> bfd/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * elf32-arm.c (v8): New array.
> (tag_cpu_arch_combine): Add support for ARMv8 attributes.
> (elf32_arm_merge_eabi_attributes): Likewise.
> (VFP_VERSION_COUNT): New define.
>
> binutils/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * readelf.c (arm_attr_tag_CPU_arch): Update for ARMv8.
> (arm_attr_tag_FP_arch): Likewise.
> (arm_attr_tag_Advanced_SIMD_arch): Likewise.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.h (arm_ext_v8): New variable.
> (fpu_vfp_ext_armv8): Likewise.
> (fpu_neon_ext_armv8): Likewise.
> (fpu_crypto_ext_armv8): Likewise.
> (arm_archs): Add armv8-a.
> (arm_extensions): Add crypto, fp, and simd.
> (arm_fpus): Add fp-armv8, neon-fp-armv8, crypto-neon-fp-armv8.
> (cpu_arch_ver): Add support for ARMv8.
> (aeabi_set_public_sttributes): Likewise.
> * doc/c-arm.texi (ARM Options): Document new architecture and
> extension options for ARMv8.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/attr-march-all.d: Update for change in expected
> output.
> * gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
> * gas/arm/attr-mfpu-vfpv4.d: Likewise.
> * gas/arm/attr-march-armv8-a+crypto.d: New testcase.
> * gas/arm/attr-march-armv8-a+fp.d: Likewise.
> * gas/arm/attr-march-armv8-a+simd.d: Likewise.
> * gas/arm/attr-march-armv8-a.d: Likewise.
>
> include/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * elf/arm.h (TAG_CPU_ARCH_V8): New define.
> (MAX_TAG_CPU_ARCH): Update.
> * opcode/arm.h (ARM_EXT_V8): New define.
> (FPU_VFP_EXT_ARMV8): Likewise.
> (FPU_NEON_EXT_ARMV8): Likewise.
> (FPU_CRYPTO_EXT_ARMV8): Likewise.
> (ARM_AEXT_V8A): Likewise.
> (FPU_VFP_ARMV8): Likwise.
> (FPU_NEON_ARMV8): Likewise.
> (FPU_CRYPTO_ARMV8): Likewise.
> (FPU_ARCH_VFP_ARMV8): Likewise.
> (FPU_ARCH_NEON_VFP_ARMV8): Likewise.
> (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8): Likewise.
> (ARM_ARCH_V8A): Likwise.
> (ARM_ARCH_V8A_FP): Likewise.
> (ARM_ARCH_V8A_SIMD): Likewise.
> (ARM_ARCH_V8A_CRYPTO): Likewise.
>
> ld/testsuite/ChangeLog:
>
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * ld-arm/arm-elf.exp: Add new testcases.
> * ld-arm/attr-merge-vfp-3.d: Update for change in expected
> output.
> * ld-arm/attr-merge-vfp-3r.d: Likewise.
> * ld-arm/attr-merge-vfp-4.d: Likewise.
> * ld-arm/attr-merge-vfp-4r.d: Likewise.
> * ld-arm/attr-merge-vfp-5.d: Likewise.
> * ld-arm/attr-merge-vfp-5r.d: Likewise.
> * ld-arm/attr-merge-vfp-7.d: New testcase.
> * ld-arm/attr-merge-vfp-7r.d: Likewise.
> * ld-arm/attr-merge-vfp-armv8-hard.s: Likewise.
> * ld-arm/attr-merge-vfp-armv8.s: Likewise.
>
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 02/21] Mark SWP as obsolete.
2012-08-23 14:56 ` [RFA/ARM 02/21] Mark SWP as obsolete Matthew Gretton-Dann
@ 2012-08-23 16:29 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:29 UTC (permalink / raw)
To: binutils
On 23/08/12 15:55, Matthew Gretton-Dann wrote:
>
> ARMv8 obsoletes the SWP{B} instructions.
>
> This patch updates the assembler to error in this case.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (check_obsolete): New function.
> (do_rd_rm_rn): Check swp{b} for obsoletion.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a-bad.d: New testcase.
> * gas/arm/armv8-a-bad.l: Likewise.
> * gas/arm/armv8-a-bad.s: Likewise.
> * gas/arm/depr-swp.l: Update for change in expected output.
> * gas/arm/depr-swp.s: Add additional test.
>
> include/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * opcode/arm.h (ARM_CPU_IS_ANY): New define.
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 03/21] Warn on deprecated Co-processor register accesses
2012-08-23 14:56 ` [RFA/ARM 03/21] Warn on deprecated Co-processor register accesses Matthew Gretton-Dann
@ 2012-08-23 16:30 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:30 UTC (permalink / raw)
To: binutils
On 23/08/12 15:55, Matthew Gretton-Dann wrote:
> ARMv8 deprecates some cp15 and cp14 coprocessor register accesses.
>
> This patch causes the assembler to warn when these registers are
> accessed.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (deprecated_coproc_regs_s): New structure.
> (deprecated_coproc_regs): New variable.
> (deprecated_coproc_reg_count): Likewise.
> (do_co_reg): Error on obsolete & warn on deprecated registers.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a-bad.l: Update testcase.
> * gas/arm/armv8-a-bad.s: Likewise.
>
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 04/21] Warn on deprecated IT blocks.
2012-08-23 14:57 ` [RFA/ARM 04/21] Warn on deprecated IT blocks Matthew Gretton-Dann
@ 2012-08-23 16:31 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:31 UTC (permalink / raw)
To: binutils
On 23/08/12 15:56, Matthew Gretton-Dann wrote:
>
> ARMv8 deprecates various forms of IT blocks. This patch adds warnings
> for these cases.
>
> The IT block forms deprecated are:
> * Those with more than one instruction in the IT block
> * Those with a 32-bit instruction in the IT block
> * Various 16-bit instructions (mostly involving PC).
>
> This patch does not change the handling of automatic IT block generation.
> This is to be done in a later patch.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (do_t_it): Fully initialise now_it.
> (new_automatic_it_block): Likewise.
> (handle_it_block): Record whether current instruction is
> conditionally executed.
> * config/tc-arm.c (depr_insn_mask): New structure.
> (depr_it_insns): New variable.
> (it_fsm_post_encode): Warn on deprecated uses.
> * config/tc-arm.h (current_it): Add new fields.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a-it-bad.d: New testcase.
> * gas/arm/armv8-a-it-bad.l: Likewise.
> * gas/arm/armv8-a-it-bad.s: Likewise.
> * gas/arm/ldr-t-bad.s: Update testcase.
> * gas/arm/ldr-t.d: Likewise.
> * gas/arm/ldr-t.s: Likewise.
> * gas/arm/neon-cond-bad-inc.s: Likewise.
> * gas/arm/sp-pc-validations-bad-t: Likewise.
> * gas/arm/vfp-fma-inc.s: Likewise.
> * gas/arm/vfp-neon-syntax-inc.s: Likewise.
>
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 05/21] Warn that SETEND is deprecated.
2012-08-23 14:57 ` [RFA/ARM 05/21] Warn that SETEND is deprecated Matthew Gretton-Dann
@ 2012-08-23 16:32 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:32 UTC (permalink / raw)
To: binutils
On 23/08/12 15:56, Matthew Gretton-Dann wrote:
>
> ARMv8 deprecates the SETEND instruction.
>
> This patch causes the assembler to warn when it encounters SETEND.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (do_setend): Warn on deprecated SETEND.
> (do_t_setend): Likewise.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a-bad.l: Update
> * gas/arm/armv8-a-bad.s: Likewise.
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 06/21] Add support diagnosing UNPREDICTABLE conditional instructions
2012-08-23 14:58 ` [RFA/ARM 06/21] Add support diagnosing UNPREDICTABLE conditional instructions Matthew Gretton-Dann
@ 2012-08-23 16:32 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:32 UTC (permalink / raw)
To: binutils
On 23/08/12 15:57, Matthew Gretton-Dann wrote:
>
> Some of the new instructions in ARMv8 are UNPREDICTABLE when executed
> in an IT block (these are all SIMD/FP instructions).
>
> This patch adds infrastructure to support diagnosing these instructions
> in the disassembler.
>
> Note that the repurposing of %u in the opcode16 table is fine as it has
> never been used previously.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
>
> * arm-dis.c (COND_UNCOND): New constant.
> (print_insn_coprocessor): Add support for %u format specifier.
> (print_insn_neon): Likewise.
>
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 07/21] Add support for new options to DMB/DSB
2012-08-23 14:59 ` [RFA/ARM 07/21] Add support for new options to DMB/DSB Matthew Gretton-Dann
@ 2012-08-23 16:33 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:33 UTC (permalink / raw)
To: binutils
On 23/08/12 15:58, Matthew Gretton-Dann wrote:
> ARMv8 adds new options to DMB/DSB in A32/T32.
>
> We do a bit of re-engineering in opcodes/arm-dis.c to common up the
> decode of the options to DMB/DSB.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (asm_barrier_opt): Add arch field.
> (mark_feature_used): New function.
> (parse_barrier): Check specified option is valid for the
> specified architecture.
> (UL_BARRIER): New macro.
> (barrier_opt_names): Update for new barrier options.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a-barrier.s: New testcase.
> * gas/arm/armv8-a-barrier-arm.d: Likewise.
> * gas/arm/armv8-a-barrier-thumb.d: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (data_barrier_option): New function.
> (print_insn_arm): Use data_barrier_option.
> (print_insn_thumb32): Use data_barrier_option.
>
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 08/21] Add support for SEVL
2012-08-23 14:59 ` [RFA/ARM 08/21] Add support for SEVL Matthew Gretton-Dann
@ 2012-08-23 16:33 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:33 UTC (permalink / raw)
To: binutils
On 23/08/12 15:58, Matthew Gretton-Dann wrote:
>
> ARMv8 adds the SEVL instruction to A32 and T32.
>
> This patch adds support for it.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (T16_32_TAB): Add _sevl.
> (insns): Add SEVL.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a.s: New testcase.
> * gas/arm/armv8-a.d: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (arm_opcodes): Add SEVL.
> (thumb_opcodes): Likewise.
> (thumb32_opcodes): Likewise.
>
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 09/21] Add support for DCPS instruction.
2012-08-23 15:00 ` [RFA/ARM 09/21] Add support for DCPS instruction Matthew Gretton-Dann
@ 2012-08-23 16:34 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:34 UTC (permalink / raw)
To: binutils
On 23/08/12 15:59, Matthew Gretton-Dann wrote:
>
> ARMv8 adds a DCPS instruction to T32 (in debug mode).
>
> This patch adds support for it.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (insns): Add DCPS instruction.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a.d: Update.
> * gas/arm/armv8-a.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
>
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 11/21] Add support for LDRA and STRL instructions.
2012-08-23 15:01 ` [RFA/ARM 11/21] Add support for LDRA and STRL instructions Matthew Gretton-Dann
@ 2012-08-23 16:35 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:35 UTC (permalink / raw)
To: binutils
On 23/08/12 16:00, Matthew Gretton-Dann wrote:
>
> ARMv8 adds LDRA and STRL instructions (and variants) in A32 and T32.
>
> This patch adds support for them.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (do_rm_rn): New function.
> (do_strlex): Likewise.
> (do_t_strlex): Likewise.
> (insns): Add support for LDRA/STRL instructions.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a-bad.l: Update testcase.
> * gas/arm/armv8-a-bad.s: Likewise.
> * gas/arm/armv8-a.d: Likewise.
> * gas/arm/armv8-a.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
> (thumb32_opcodes): Likewise.
> (print_arm_insn): Add support for %<>T formatter.
>
OK
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 10/21] Add support for HLT
2012-08-23 15:00 ` [RFA/ARM 10/21] Add support for HLT Matthew Gretton-Dann
@ 2012-08-23 16:35 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:35 UTC (permalink / raw)
To: binutils
On 23/08/12 15:59, Matthew Gretton-Dann wrote:
>
> ARMv8 adds a HLT instruction in A32 and T32.
>
> This patch adds support for it.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (do_t_bkpt_hlt1): New function.
> (do_t_hlt): New function.
> (do_t_bkpt): Use do_t_bkpt_hlt1.
> (insns): Add HLT.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a-bad.l: Update for HLT.
> * gas/arm/armv8-a-bad.s: Likewise.
> * gas/arm/armv8-a.d: Likewise.
> * gas/arm/armv8-a.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (arm_opcodes): Add HLT.
> (thumb_opcodes): Likewise.
>
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 12/21] Add support for VSEL.
2012-08-23 15:01 ` [RFA/ARM 12/21] Add support for VSEL Matthew Gretton-Dann
@ 2012-08-23 16:36 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:36 UTC (permalink / raw)
To: binutils
On 23/08/12 16:00, Matthew Gretton-Dann wrote:
>
> ARMv8 adds a VSEL instruction to A32/T32.
>
> This patch adds support for it.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.
> (NEON_ENC_FPV8_): New define.
> (do_vfp_nsyn_fpv8): New function.
> (do_vsel): Likewise.
> (insns): Add VSEL instructions.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a+fp.d: New testcase.
> * gas/arm/armv8-a+fp.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (coprocessor_opcodes): Add VSEL.
> (print_insn_coprocessor): Add new %<>c bitfield format
> specifier.
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 13/21] Add support for VMAXNM/VMINNM instructions.
2012-08-23 15:02 ` [RFA/ARM 13/21] Add support for VMAXNM/VMINNM instructions Matthew Gretton-Dann
@ 2012-08-23 16:37 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:37 UTC (permalink / raw)
To: binutils
On 23/08/12 16:01, Matthew Gretton-Dann wrote:
>
> ARMv8 adds VMAXNM and VMINNM instructions in A32 and T32.
>
> This patch adds support for them.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.
> (vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator.
> (vfp_or_neon_is_neon): Add check for SIMD for ARMv8.
> (do_maxnm): New function.
> (insns): Add vmaxnm, vminnm entries.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/testsuite/gas/armv8-a+fp.d: Update testcase.
> * gas/testsuite/gas/armv8-a+fp.s: Likewise.
> * gas/testsuite/gas/armv8-a+simd.d: New testcase.
> * gas/testsuite/gas/armv8-a+simd.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
> (neon_opcodes): Likewise.
>
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 14/21] Tidy up neon_cvt_flavour
2012-08-23 15:03 ` [RFA/ARM 14/21] Tidy up neon_cvt_flavour Matthew Gretton-Dann
@ 2012-08-23 16:38 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:38 UTC (permalink / raw)
To: binutils
On 23/08/12 16:01, Matthew Gretton-Dann wrote:
>
> This is a tidy-up check in which creates an enum neon_cvt_flavour, and
> moves all the data which depends on it into one large 'table'. This was
> done to make the code understandable for adding the new VCVT variants.
>
> gas/ChangeLog:
>
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm>
>
> * config/tc-arm.c (CVT_FLAVOUR_VAR): New define.
> (CVT_VAR): New helper define.
> (neon_cvt_flavour): New enumeration, function renamed...
> (get_neon_cvt_flavour): ...to this.
> (do_vfp_nsyn_cvt): Update to use new neon_cvt_flavour.
> (do_vfp_nsyn_cvtz): Likewise.
> (do_neon_cvt_1): Likewise.
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 15/21] Add support for VCVT[ANPM]
2012-08-23 15:03 ` [RFA/ARM 15/21] Add support for VCVT[ANPM] Matthew Gretton-Dann
@ 2012-08-23 16:39 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:39 UTC (permalink / raw)
To: binutils
On 23/08/12 16:02, Matthew Gretton-Dann wrote:
>
> ARMv8 adds new VCVT variants, VCVT[ANPM] to A32 and T32.
>
> This patch adds support for them.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (NEON_ENC_TAB): Add vcvta entry.
> (neon_cvt_mode): New enumeration.
> (do_vfp_nsyn_cvt_fpv8): New function.
> (do_neon_cvt_1): Add support for new conversions.
> (do_neon_cvtr): Use neon_cvt_mode enumerator.
> (do_neon_cvt): Likewise.
> (do_neon_cvta): New function.
> (do_neon_cvtn): Likewise.
> (do_neon_cvtp): Likewise.
> (do_neon_cvtm): Likewise.
> (insns): Add new VCVT instructions.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a+fp.d: Update testcase.
> * gas/arm/armv8-a+fp.s: Likewise.
> * gas/arm/armv8-a+simd.d: Likewise.
> * gas/arm/armv8-a+simd.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
> variants.
> (neon_opcodes): Likewise.
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 16/21] Add support for VRINT instructions.
2012-08-23 15:04 ` [RFA/ARM 16/21] Add support for VRINT instructions Matthew Gretton-Dann
@ 2012-08-23 16:40 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:40 UTC (permalink / raw)
To: binutils
On 23/08/12 16:03, Matthew Gretton-Dann wrote:
>
> ARMv8 adds a new VRINT instruction to A32 and T32.
>
> This patch adds support for it.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (NEON_ENC_TAB): Add vrint entries.
> (neon_cvt_mode): Add neon_cvt_mode_r.
> (do_vrint_1): New function.
> (do_vrint_x): Likewise.
> (do_vrint_z): Likewise.
> (do_vrint_r): Likewise.
> (do_vrint_a): Likewise.
> (do_vrint_n): Likewise.
> (do_vrint_p): Likewise.
> (do_vrint_m): Likewise.
> (insns): Add VRINT instructions.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a+fpv5.d: Update testcase.
> * gas/arm/armv8-a+fpv5.s: Likewise.
> * gas/arm/armv8-a+simdv3.d: Likewise.
> * gas/arm/armv8-a+simdv3.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (coprocessor_opcodes): Add VRINT.
> (neon_opcodes): Likewise.
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 17/21] Add support for 16-/64-bit Floating Point conversions.
2012-08-23 15:05 ` [RFA/ARM 17/21] Add support for 16-/64-bit Floating Point conversions Matthew Gretton-Dann
@ 2012-08-23 16:42 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:42 UTC (permalink / raw)
To: binutils
On 23/08/12 16:04, Matthew Gretton-Dann wrote:
>
> ARMv8 extends VCVT[TB] to support converting to/from double precision
> floats.
>
> This patch adds support for this, in the process it also fixes bugs in
> the support for half-precision <-> single-precision conversions.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (el_type_type_check): Add handling for 16-bit
> floating point types.
> (do_neon_cvttb_2): New function.
> (do_neon_cvttb_1): Likewise.
> (do_neon_cvtb): Refactor to use do_neon_cvttb_1.
> (do_neon_cvtt): Likewise.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a+fp.d: Update testcase.
> * gas/arm/armv8-a+fp.s: Likewise.
> * gas/arm/half-prec-vfpv3.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
> conversions.
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 18/21] Add support for AES instructions.
2012-08-23 15:05 ` [RFA/ARM 18/21] Add support for AES instructions Matthew Gretton-Dann
@ 2012-08-23 16:43 ` Richard Earnshaw
2012-08-23 17:46 ` Richard Earnshaw
0 siblings, 1 reply; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:43 UTC (permalink / raw)
To: binutils
On 23/08/12 16:04, Matthew Gretton-Dann wrote:
>
> ARMv8 adds several AES instructions for A32 and T32.
>
> This patch adds support for these.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (NEON_ENC_TAB): Add aes entry.
> (neon_type_mask): Add N_UNT.
> (neon_check_type): Don't always decay typed to untyped sizes.
> (do_crypto_2op_1): New function.
> (do_aese): Likewise.
> (do_aesd): Likewise.
> (do_aesmc.8): Likewise.
> (do_aesimc.8): Likewise.
> (insns): Add AES instructions.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a+crypto.d: New testcase.
> * gas/arm/armv8-a+crypto.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (neon_opcodes): Add support for AES instructions.
>
OK, apart from:
> /* Overall per-instruction processing. */
It looks like you've got a tab, rather than two spaces at the end of
this comment.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 19/21] Add support for VMULL.P64
2012-08-23 15:06 ` [RFA/ARM 19/21] Add support for VMULL.P64 Matthew Gretton-Dann
@ 2012-08-23 16:43 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:43 UTC (permalink / raw)
To: binutils
On 23/08/12 16:05, Matthew Gretton-Dann wrote:
>
> ARMv8 adds a new variant to the VMULL instruction in A32/T32.
>
> This patch adds support for this instruction.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (neon_type_mask): Add P64 type.
> (type_chk_of_el_type): Handle P64 type.
> (el_type_of_type_chk): Likewise.
> (do_neon_vmull): Handle VMULL.P64.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a+crypto.d: Update testcase.
> * gas/arm/armv8-a+crypto.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (neon_opcodes): Handle VMULL.P64.
>
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 20/21] Add support for SHA 3-operand instructions
2012-08-23 15:06 ` [RFA/ARM 20/21] Add support for SHA 3-operand instructions Matthew Gretton-Dann
@ 2012-08-23 16:45 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 16:45 UTC (permalink / raw)
To: binutils
On 23/08/12 16:05, Matthew Gretton-Dann wrote:
>
> ARMv8 adds various SHA 3-operand instructions to A32 and T32.
>
> This patch adds support for them.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
> (do_crypto_3op_1): New function.
> (do_sha1c): Likewise.
> (do_sha1p): Likewise.
> (do_sha1m): Likewise.
> (do_sha1su0): Likewise.
> (do_sha256h): Likewise.
> (do_sha256h2): Likewise.
> (do_sha256su1): Likewise.
> (insns): Add SHA 3 operand instructions.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a+crypto.d: Update testcase.
> * gas/arm/armv8-a+crypto.s: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 21/21] Add support for 2-operand SHA instructions
2012-08-23 16:27 ` [RFA/ARM 21/21] Add support for 2-operand SHA instructions Matthew Gretton-Dann
@ 2012-08-23 17:07 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 17:07 UTC (permalink / raw)
To: binutils
On 23/08/12 16:06, Matthew Gretton-Dann wrote:
>
> ARMv8 adds various 2-operand SHA instructions.
>
> This patch adds support for them.
>
> gas/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.
> (do_sha1h): New function.
> (do_sha1su1): Likewise.
> (do_sha256su0): Likewise.
> (insns): Add 2 operand SHA instructions.
>
> gas/testsuite/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * gas/arm/armv8-a+crypto.s: Update testcase.
> * gas/arm/armv8-a+crypto.d: Likewise.
>
> opcodes/ChangeLog:
> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>
> * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
>
>
OK.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [RFA/ARM 18/21] Add support for AES instructions.
2012-08-23 16:43 ` Richard Earnshaw
@ 2012-08-23 17:46 ` Richard Earnshaw
0 siblings, 0 replies; 43+ messages in thread
From: Richard Earnshaw @ 2012-08-23 17:46 UTC (permalink / raw)
To: Richard Earnshaw; +Cc: binutils
On 23/08/12 17:42, Richard Earnshaw wrote:
> On 23/08/12 16:04, Matthew Gretton-Dann wrote:
>>
>> ARMv8 adds several AES instructions for A32 and T32.
>>
>> This patch adds support for these.
>>
>> gas/ChangeLog:
>> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>>
>> * config/tc-arm.c (NEON_ENC_TAB): Add aes entry.
>> (neon_type_mask): Add N_UNT.
>> (neon_check_type): Don't always decay typed to untyped sizes.
>> (do_crypto_2op_1): New function.
>> (do_aese): Likewise.
>> (do_aesd): Likewise.
>> (do_aesmc.8): Likewise.
>> (do_aesimc.8): Likewise.
>> (insns): Add AES instructions.
>>
>> gas/testsuite/ChangeLog:
>> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>>
>> * gas/arm/armv8-a+crypto.d: New testcase.
>> * gas/arm/armv8-a+crypto.s: Likewise.
>>
>> opcodes/ChangeLog:
>> 2012-08-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
>>
>> * arm-dis.c (neon_opcodes): Add support for AES instructions.
>>
>
> OK, apart from:
>
>
>> /* Overall per-instruction processing. */
>
> It looks like you've got a tab, rather than two spaces at the end of
> this comment.
>
>
>
>
Hmm, just realized, that wasn't a line that was changed, so the problem
is pre-existing. Perhaps you could fix it anyway.
R.
^ permalink raw reply [flat|nested] 43+ messages in thread
end of thread, other threads:[~2012-08-23 17:07 UTC | newest]
Thread overview: 43+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <cover.1345733341.git.matthew.gretton-dann@arm.com>
2012-08-23 14:55 ` [RFA/ARM 01/21] Add command line and object file support for ARMv8-A Matthew Gretton-Dann
2012-08-23 16:28 ` Richard Earnshaw
2012-08-23 14:56 ` [RFA/ARM 03/21] Warn on deprecated Co-processor register accesses Matthew Gretton-Dann
2012-08-23 16:30 ` Richard Earnshaw
2012-08-23 14:56 ` [RFA/ARM 02/21] Mark SWP as obsolete Matthew Gretton-Dann
2012-08-23 16:29 ` Richard Earnshaw
2012-08-23 14:57 ` [RFA/ARM 04/21] Warn on deprecated IT blocks Matthew Gretton-Dann
2012-08-23 16:31 ` Richard Earnshaw
2012-08-23 14:57 ` [RFA/ARM 05/21] Warn that SETEND is deprecated Matthew Gretton-Dann
2012-08-23 16:32 ` Richard Earnshaw
2012-08-23 14:58 ` [RFA/ARM 06/21] Add support diagnosing UNPREDICTABLE conditional instructions Matthew Gretton-Dann
2012-08-23 16:32 ` Richard Earnshaw
2012-08-23 14:59 ` [RFA/ARM 08/21] Add support for SEVL Matthew Gretton-Dann
2012-08-23 16:33 ` Richard Earnshaw
2012-08-23 14:59 ` [RFA/ARM 07/21] Add support for new options to DMB/DSB Matthew Gretton-Dann
2012-08-23 16:33 ` Richard Earnshaw
2012-08-23 15:00 ` [RFA/ARM 09/21] Add support for DCPS instruction Matthew Gretton-Dann
2012-08-23 16:34 ` Richard Earnshaw
2012-08-23 15:00 ` [RFA/ARM 10/21] Add support for HLT Matthew Gretton-Dann
2012-08-23 16:35 ` Richard Earnshaw
2012-08-23 15:01 ` [RFA/ARM 11/21] Add support for LDRA and STRL instructions Matthew Gretton-Dann
2012-08-23 16:35 ` Richard Earnshaw
2012-08-23 15:01 ` [RFA/ARM 12/21] Add support for VSEL Matthew Gretton-Dann
2012-08-23 16:36 ` Richard Earnshaw
2012-08-23 15:02 ` [RFA/ARM 13/21] Add support for VMAXNM/VMINNM instructions Matthew Gretton-Dann
2012-08-23 16:37 ` Richard Earnshaw
2012-08-23 15:03 ` [RFA/ARM 15/21] Add support for VCVT[ANPM] Matthew Gretton-Dann
2012-08-23 16:39 ` Richard Earnshaw
2012-08-23 15:03 ` [RFA/ARM 14/21] Tidy up neon_cvt_flavour Matthew Gretton-Dann
2012-08-23 16:38 ` Richard Earnshaw
2012-08-23 15:04 ` [RFA/ARM 16/21] Add support for VRINT instructions Matthew Gretton-Dann
2012-08-23 16:40 ` Richard Earnshaw
2012-08-23 15:05 ` [RFA/ARM 18/21] Add support for AES instructions Matthew Gretton-Dann
2012-08-23 16:43 ` Richard Earnshaw
2012-08-23 17:46 ` Richard Earnshaw
2012-08-23 15:05 ` [RFA/ARM 17/21] Add support for 16-/64-bit Floating Point conversions Matthew Gretton-Dann
2012-08-23 16:42 ` Richard Earnshaw
2012-08-23 15:06 ` [RFA/ARM 20/21] Add support for SHA 3-operand instructions Matthew Gretton-Dann
2012-08-23 16:45 ` Richard Earnshaw
2012-08-23 15:06 ` [RFA/ARM 19/21] Add support for VMULL.P64 Matthew Gretton-Dann
2012-08-23 16:43 ` Richard Earnshaw
2012-08-23 16:27 ` [RFA/ARM 21/21] Add support for 2-operand SHA instructions Matthew Gretton-Dann
2012-08-23 17:07 ` Richard Earnshaw
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