From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14892 invoked by alias); 12 Apr 2019 10:41:02 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 13386 invoked by uid 89); 12 Apr 2019 10:41:00 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.7 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH,SPF_PASS autolearn=ham version=3.3.1 spammy=SUCCESS X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 12 Apr 2019 10:40:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1699D15AB; Fri, 12 Apr 2019 03:40:57 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6E34F3F718; Fri, 12 Apr 2019 03:40:56 -0700 (PDT) Subject: Re: [PATCH, binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline To: binutils@sourceware.org References: Cc: nickc@redhat.com From: "Andre Vieira (lists)" Message-ID: <50dde9f1-b18c-bd46-f69a-f0b668d9ad22@arm.com> Date: Fri, 12 Apr 2019 10:41:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/mixed; boundary="------------9A9AA53C6253D68CE1A1C5FD" X-IsSubscribed: yes X-SW-Source: 2019-04/txt/msg00149.txt.bz2 This is a multi-part message in MIME format. --------------9A9AA53C6253D68CE1A1C5FD Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-length: 2235 Hi, Fixed some testisms highlighted by Nick. This OK? *** gas/ChangeLog *** 2019-04-12 Sudakshina Das Andre Vieira * config/tc-arm.c (T16_32_TAB): New entries for bf. (do_t_branch_future): New. (insns): New instruction for bf. * testsuite/gas/arm/armv8_1-m-bf.d: New. * testsuite/gas/arm/armv8_1-m-bf.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.l: New. * testsuite/gas/arm/armv8_1-m-bf-bad.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.s: New. *** ld/ChangeLog *** 2019-04-12 Sudakshina Das * testsuite/ld-arm/bf.s: New. * testsuite/ld-arm/bf.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das * arm-dis.c (thumb32_opcodes): New instructions for bf. On 04/04/2019 14:37, Andre Vieira (lists) wrote: > Hi > > This patch is part of a series of patches to add support for Armv8.1-M > Mainline instructions to binutils. > > This patch adds the BF instruction. > > Testing: Added new tests for the valid instructions operands. Testsuite > shows no regression when run for arm-none-eabi targets. > > Thanks > Sudi > > > ChangeLog entries are as follows : > > *** gas/ChangeLog *** > > 2019-04-04  Sudakshina Das  > >     * config/tc-arm.c (T16_32_TAB): New entries for bf. >     (do_t_branch_future): New. >     (insns): New instruction for bf. >     * testsuite/gas/arm/armv8_1-m-bf.d: New. >     * testsuite/gas/arm/armv8_1-m-bf.s: New. >     * testsuite/gas/arm/armv8_1-m-bf-bad.s: New >     * testsuite/gas/arm/armv8_1-m-bf-bad.l: New >     * testsuite/gas/arm/armv8_1-m-bf-bad.d: New > > *** ld/ChangeLog *** > > 2019-04-04  Sudakshina Das  > >     * testsuite/ld-arm/bf.s: New. >     * testsuite/ld-arm/bf.d: New. >     * testsuite/ld-arm/arm-elf.exp: Add above test. > > *** opcodes/ChangeLog *** > > 2019-04-04  Sudakshina Das  > >     * arm-dis.c (thumb32_opcodes): New instructions for bf. --------------9A9AA53C6253D68CE1A1C5FD Content-Type: text/x-patch; name="6.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="6.patch" Content-length: 9277 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index d3a21d63575c194051606bb723a224d3c10334e9..caba2736c16c9dbd61ca1a7637cc171682058d13 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -10505,6 +10505,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) X(_asrs, 1000, fa50f000), \ X(_b, e000, f000b000), \ X(_bcond, d000, f0008000), \ + X(_bf, 0000, f040e001), \ X(_bic, 4380, ea200000), \ X(_bics, 4380, ea300000), \ X(_cmn, 42c0, eb100f00), \ @@ -13320,6 +13321,51 @@ v8_1_branch_value_check (int val, int nbits, int is_signed) return SUCCESS; } +/* For branches in Armv8.1-M Mainline. */ +static void +do_t_branch_future (void) +{ + unsigned long insn = inst.instruction; + + inst.instruction = THUMB_OP32 (inst.instruction); + if (inst.operands[0].hasreloc == 0) + { + if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL) + as_bad (BAD_BRANCH_OFF); + + inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23; + } + else + { + inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5; + inst.relocs[0].pc_rel = 1; + } + + switch (insn) + { + case T_MNEM_bf: + if (inst.operands[1].hasreloc == 0) + { + int val = inst.operands[1].imm; + if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL) + as_bad (BAD_BRANCH_OFF); + + int immA = (val & 0x0001f000) >> 12; + int immB = (val & 0x00000ffc) >> 2; + int immC = (val & 0x00000002) >> 1; + inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11); + } + else + { + inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17; + inst.relocs[1].pc_rel = 1; + } + break; + + default: abort (); + } +} + /* Neon instruction encoder helpers. */ /* Encodings for the different types for various Neon opcodes. */ @@ -19538,6 +19584,11 @@ static struct asm_barrier_opt barrier_opt_names[] = { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \ NULL, do_##te } +/* T_MNEM_xyz enumerator variants of ToC. */ +#define toC(mnem, top, nops, ops, te) \ + { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \ + do_##te } + /* Legacy mnemonics that always have conditional infix after the third character. */ #define CL(mnem, op, nops, ops, ae) \ @@ -21623,6 +21674,11 @@ static const struct asm_opcode insns[] = #define THUMB_VARIANT & arm_ext_v8m_main ToC("vlldm", ec300a00, 1, (RRnpc), rn), ToC("vlstm", ec200a00, 1, (RRnpc), rn), + + /* Armv8.1-M Mainline instructions. */ +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v8_1m_main + toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future), }; #undef ARM_VARIANT #undef THUMB_VARIANT @@ -21633,8 +21689,10 @@ static const struct asm_opcode insns[] = #undef cCE #undef cCL #undef C3E +#undef C3 #undef CE #undef CM +#undef CL #undef UE #undef UF #undef UT @@ -21650,6 +21708,9 @@ static const struct asm_opcode insns[] = #undef OPS5 #undef OPS6 #undef do_0 +#undef ToC +#undef toC +#undef ToU /* MD interface: bits in the object file. */ diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..d61aad79e9a6faa26a733245b3769b867f5e126d --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.d @@ -0,0 +1,4 @@ +#name: Invalid Armv8.1-M Mainline BF instructions +#source: armv8_1-m-bf-bad.s +#as: -march=armv8.1-m.main +#error_output: armv8_1-m-bf-bad.l diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..3f7ed80a6d07a4a2c05e8968e95c26d66eae2fab --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.l @@ -0,0 +1,9 @@ +.*: Assembler messages: +.*:6: Error: branch out of range or not a multiple of 2 +.*:7: Error: branch out of range or not a multiple of 2 +.*:8: Error: branch out of range or not a multiple of 2 +.*:9: Error: branch out of range or not a multiple of 2 +.*:11: Error: branch out of range or not a multiple of 2 +.*:12: Error: branch out of range or not a multiple of 2 +.*:13: Error: branch out of range or not a multiple of 2 +.*:14: Error: branch out of range or not a multiple of 2 diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..43ef4b1bf92fa42956f2fdabd29eeec7bcf168fb --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-bad.s @@ -0,0 +1,14 @@ + .syntax unified + .text + .thumb +foo: + # OP0 : Unsigned, 5-bit, even + bf 0, 36 + bf -2, 36 + bf 3, 36 + bf 32, 36 + # OP1 : signed, 17-bit, even + bf 2, -5 + bf 2, 5 + bf 2, 65536 + bf 2, -65538 diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d new file mode 100644 index 0000000000000000000000000000000000000000..e429c136f2ea7818de2a7479a21f0cc6bc0702e1 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d @@ -0,0 +1,10 @@ +#name: Valid Armv8.1-M Mainline BF instruction with relocation +#as: -march=armv8.1-m.main +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-pe *-wince-* + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f0df e7ff bf 2, 00000000 <.target> + 0: R_ARM_THM_BF16 .target diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.s b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.s new file mode 100644 index 0000000000000000000000000000000000000000..c11c9c177a4483589e4477f2e151ae8b742b019a --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.s @@ -0,0 +1,5 @@ + .syntax unified + .text + .thumb +foo: + bf 2, .target diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.d b/gas/testsuite/gas/arm/armv8_1-m-bf.d new file mode 100644 index 0000000000000000000000000000000000000000..dd30b2a2ff1d35cd58299813614ec5a79cbcdadf --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf.d @@ -0,0 +1,13 @@ +#name: Valid Armv8.1-M Mainline BF instruction +#as: -march=armv8.1-m.main +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a +0[0-9a-f]+ <[^>]+> 4609 mov r1, r1 +0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c +0[0-9a-f]+ <[^>]+> 460a mov r2, r1 +0[0-9a-f]+ <[^>]+> 4613 mov r3, r2 +0[0-9a-f]+ <[^>]+> 4614 mov r4, r2 diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.s b/gas/testsuite/gas/arm/armv8_1-m-bf.s new file mode 100644 index 0000000000000000000000000000000000000000..8c6dac748dc1fef96e54bc38c9abe4e13b7ef2ab --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf.s @@ -0,0 +1,12 @@ + .syntax unified + .text + .thumb +foo: + bf 2, 6 + mov r1, r1 + bf .LBranch, .LB2 + mov r2, r1 +.LB2: + mov r3, r2 +.LBranch: + mov r4, r2 diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp index 450a76b7082be883d0bbc818420edd2d6a762e6e..ef3a49c23742f4c43c78e73aa692928ba3d56123 100644 --- a/ld/testsuite/ld-arm/arm-elf.exp +++ b/ld/testsuite/ld-arm/arm-elf.exp @@ -667,6 +667,10 @@ set armeabitests_nonacl { {{objdump -d armv4-bx.d}} "armv4-bx"} + {"Armv8.1-M Mainline BF" "-r -Ttext 0x1000 --section-start .foo=0x1001000" "" "-march=armv8.1-m.main" {bf.s} + {{objdump -dr bf.d}} + "bf"} + {"R_ARM_THM_JUMP24 Relocation veneers: Short 1" "--no-fix-arm1176 --section-start destsect=0x00009000 --section-start .text=0x8000" "" "-march=armv7-a -mthumb" diff --git a/ld/testsuite/ld-arm/bf.d b/ld/testsuite/ld-arm/bf.d new file mode 100644 index 0000000000000000000000000000000000000000..658120abb693ba7b86c669a5b8a6fb3e3e335e37 --- /dev/null +++ b/ld/testsuite/ld-arm/bf.d @@ -0,0 +1,14 @@ + +.*: file format elf32-.*arm + + +Disassembly of section .text: + +00001000 <_start>: + 1000: f0df e7ff bf 2, 1001000 + 1000: R_ARM_THM_BF16 bar + +Disassembly of section .foo: + +01001000 : + 1001000: 4770 bx lr diff --git a/ld/testsuite/ld-arm/bf.s b/ld/testsuite/ld-arm/bf.s new file mode 100644 index 0000000000000000000000000000000000000000..164a90d04b4e995add2c54beee31e63fbdc5c12d --- /dev/null +++ b/ld/testsuite/ld-arm/bf.s @@ -0,0 +1,19 @@ + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func + +_start: + bf 2, bar + +@ We will place the section .foo at 0x1001000. + + .section .foo, "xa" + .thumb_func + +bar: + bx lr + diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 71443d3ea41966309d4516754eb8f2e38e3e6df0..966a4d4d92fa660b1754c4c703648ec008efcfb0 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2747,6 +2747,11 @@ static const struct opcode16 thumb_opcodes[] = makes heavy use of special-case bit patterns. */ static const struct opcode32 thumb32_opcodes[] = { + /* Armv8.1-M Mainline instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf040e001, 0xf860f001, "bf%c\t%G, %W"}, + + /* ARMv8-M and ARMv8-M Security Extensions instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), --------------9A9AA53C6253D68CE1A1C5FD--