From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 6625538A8145 for ; Thu, 20 Oct 2022 09:28:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6625538A8145 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id BDC4E300089; Thu, 20 Oct 2022 09:28:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1666258133; bh=MGjjAtofhE6Ai2oDjLokUBs2cW0GuvduJsSG0JqLG4I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=U2lVN5o3zYb2839/Tyw0exh40Qi5UX6ySQ8CAyTJWjce67CkMpFN/oZWv7QPEU1ln ZsY/QVoG9dV4hLt5sjsweWiNuA8sVRcdbfl9RgqAJ4cVurnvfvguwuaP/16V4pyMDQ af7wl/SWztimaMek4AGmXRKRAtBIm5Si9gGEEPi8= From: Tsukasa OI To: Tsukasa OI , Andrew Burgess , Mike Frysinger , Nick Clifton Cc: binutils@sourceware.org Subject: [PATCH 13/40] sim/frv: Initialize some variables Date: Thu, 20 Oct 2022 09:25:59 +0000 Message-Id: <51a03f7097921cc48954210cf99e370ae8982ec8.1666257885.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This commit is strongly related to "cpu/frv: Initialize some variables" and applies corresponding changes to sim/frv/sem.c. Note: This commit touches CGEN-generated files directly. Modifying cpu/frv.cpu (which is done) and regenerating with CGEN is the best way to prevent this issue from happening again but there is another known regression in CGEN to resolve. --- sim/frv/sem.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sim/frv/sem.c b/sim/frv/sem.c index cc7cbeee318..28610f4eac7 100644 --- a/sim/frv/sem.c +++ b/sim/frv/sem.c @@ -3054,6 +3054,7 @@ SEM_FN_NAME (frvbf,cmpb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { QI tmp_cc; + tmp_cc = 0; if (EQBI (EQSI (ANDSI (GET_H_GR (FLD (f_GRi)), 0xff000000), ANDSI (GET_H_GR (FLD (f_GRj)), 0xff000000)), 0)) { tmp_cc = ANDQI (tmp_cc, 7); } else { @@ -4545,6 +4546,7 @@ SEM_FN_NAME (frvbf,lddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { SI tmp_address; + tmp_address = 0; if (NESI (FLD (f_GRk), 0)) { { tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); @@ -4591,6 +4593,7 @@ SEM_FN_NAME (frvbf,nlddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (tmp_do_op) { { SI tmp_address; + tmp_address = 0; if (NESI (FLD (f_GRk), 0)) { { tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); @@ -6706,6 +6709,7 @@ SEM_FN_NAME (frvbf,clddu) (SIM_CPU *current_cpu, SEM_ARG sem_arg) if (EQQI (CPU (h_cccr[FLD (f_CCi)]), ORSI (FLD (f_cond), 2))) { { SI tmp_address; + tmp_address = 0; if (NESI (FLD (f_GRk), 0)) { { tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -- 2.34.1