From: "Jan Beulich" <JBeulich@suse.com>
To: "H.J. Lu" <hjl.tools@gmail.com>
Cc: <kirill.yukhin@intel.com>,<binutils@sourceware.org>
Subject: [PATCH 5/6] x86/MPX: fix operand size handling
Date: Tue, 08 Oct 2013 14:43:00 -0000 [thread overview]
Message-ID: <5254364802000078000F9A5D@nat28.tlf.novell.com> (raw)
In-Reply-To: <5254349502000078000F9A3D@nat28.tlf.novell.com>
[-- Attachment #1: Type: text/plain, Size: 5069 bytes --]
All MPX instructions in 64-bit mode ignore REX.W, which means we neither
need to encode this bit nor should disassemble with 32-bit register
operands.
No MPX instructions would ever take a 16-bit register operand.
gas/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (process_suffix): Warn about 32-bit register operands
to MPX instructions in 64-bit mode.
opcodes/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
default case.
(OP_E_register): Move v_bnd_mode alongside m_mode.
* i386-opc.h (REGNAM_RAX): New.
* i386-opc.tbl (bndcl, bndcu, bndcn): Drop Reg16. Add NoRex64.
* i386-tbl.h: Re-generate.
--- 2013-10-07/gas/config/tc-i386.c
+++ 2013-10-07/gas/config/tc-i386.c
@@ -5073,8 +5078,24 @@ process_suffix (void)
{
/* We take i.suffix from the last register operand specified,
Destination register type is more significant than source
- register type. crc32 in SSE4.2 prefers source register
- type. */
+ register type. */
+
+ /* MPX instructions need no suffix, but may need a warning. */
+ if (i.tm.cpu_flags.bitfield.cpumpx)
+ {
+#if REGISTER_WARNINGS
+ if (flag_code == CODE_64BIT && !quiet_warnings
+ && i.tm.operand_types[0].bitfield.reg64
+ && i.types[0].bitfield.reg32)
+ as_warn (_("using `%s%s' instead of `%s%s' for `%s'"),
+ register_prefix,
+ (i.op[0].regs + REGNAM_RAX - REGNAM_EAX)->reg_name,
+ register_prefix, i.op[0].regs->reg_name, i.tm.name);
+#endif
+ return 1;
+ }
+
+ /* crc32 in SSE4.2 prefers source register type. */
if (i.tm.base_opcode == 0xf20f38f1)
{
if (i.types[0].bitfield.reg16)
--- 2013-10-07/opcodes/i386-dis.c
+++ 2013-10-07/opcodes/i386-dis.c
@@ -13800,7 +13801,6 @@ intel_operand_size (int bytemode, int si
}
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
USED_REX (REX_W);
@@ -14082,6 +14082,7 @@ intel_operand_size (int bytemode, int si
abort ();
oappend ("WORD PTR ");
break;
+ case v_bnd_mode:
default:
break;
}
@@ -14121,6 +14122,7 @@ OP_E_register (int bytemode, int sizefla
names = names64;
break;
case m_mode:
+ case v_bnd_mode:
names = address_mode == mode_64bit ? names64 : names32;
break;
case bnd_mode:
@@ -14135,7 +14137,6 @@ OP_E_register (int bytemode, int sizefla
bytemode = v_mode;
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
case dqb_mode:
--- 2013-10-07/opcodes/i386-opc.h
+++ 2013-10-07/opcodes/i386-opc.h
@@ -835,6 +835,7 @@ reg_entry;
#define REGNAM_AL 1
#define REGNAM_AX 25
#define REGNAM_EAX 41
+#define REGNAM_RAX 57
extern const reg_entry i386_regtab[];
extern const unsigned int i386_regtab_size;
--- 2013-10-07/opcodes/i386-opc.tbl
+++ 2013-10-07/opcodes/i386-opc.tbl
@@ -3064,9 +3064,9 @@ bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|N
bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND, RegBND }
bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND }
-bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
[-- Attachment #2: binutils-mainline-x86-MPX-operand-size.patch --]
[-- Type: text/plain, Size: 7532 bytes --]
All MPX instructions in 64-bit mode ignore REX.W, which means we neither
need to encode this bit nor should disassemble with 32-bit register
operands.
No MPX instructions would ever take a 16-bit register operand.
gas/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (process_suffix): Warn about 32-bit register operands
to MPX instructions in 64-bit mode.
opcodes/
2013-10-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
default case.
(OP_E_register): Move v_bnd_mode alongside m_mode.
* i386-opc.h (REGNAM_RAX): New.
* i386-opc.tbl (bndcl, bndcu, bndcn): Drop Reg16. Add NoRex64.
* i386-tbl.h: Re-generate.
--- 2013-10-07/gas/config/tc-i386.c
+++ 2013-10-07/gas/config/tc-i386.c
@@ -5073,8 +5078,24 @@ process_suffix (void)
{
/* We take i.suffix from the last register operand specified,
Destination register type is more significant than source
- register type. crc32 in SSE4.2 prefers source register
- type. */
+ register type. */
+
+ /* MPX instructions need no suffix, but may need a warning. */
+ if (i.tm.cpu_flags.bitfield.cpumpx)
+ {
+#if REGISTER_WARNINGS
+ if (flag_code == CODE_64BIT && !quiet_warnings
+ && i.tm.operand_types[0].bitfield.reg64
+ && i.types[0].bitfield.reg32)
+ as_warn (_("using `%s%s' instead of `%s%s' for `%s'"),
+ register_prefix,
+ (i.op[0].regs + REGNAM_RAX - REGNAM_EAX)->reg_name,
+ register_prefix, i.op[0].regs->reg_name, i.tm.name);
+#endif
+ return 1;
+ }
+
+ /* crc32 in SSE4.2 prefers source register type. */
if (i.tm.base_opcode == 0xf20f38f1)
{
if (i.types[0].bitfield.reg16)
--- 2013-10-07/opcodes/i386-dis.c
+++ 2013-10-07/opcodes/i386-dis.c
@@ -13800,7 +13801,6 @@ intel_operand_size (int bytemode, int si
}
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
USED_REX (REX_W);
@@ -14082,6 +14082,7 @@ intel_operand_size (int bytemode, int si
abort ();
oappend ("WORD PTR ");
break;
+ case v_bnd_mode:
default:
break;
}
@@ -14121,6 +14122,7 @@ OP_E_register (int bytemode, int sizefla
names = names64;
break;
case m_mode:
+ case v_bnd_mode:
names = address_mode == mode_64bit ? names64 : names32;
break;
case bnd_mode:
@@ -14135,7 +14137,6 @@ OP_E_register (int bytemode, int sizefla
bytemode = v_mode;
/* FALLTHRU */
case v_mode:
- case v_bnd_mode:
case v_swap_mode:
case dq_mode:
case dqb_mode:
--- 2013-10-07/opcodes/i386-opc.h
+++ 2013-10-07/opcodes/i386-opc.h
@@ -835,6 +835,7 @@ reg_entry;
#define REGNAM_AL 1
#define REGNAM_AX 25
#define REGNAM_EAX 41
+#define REGNAM_RAX 57
extern const reg_entry i386_regtab[];
extern const unsigned int i386_regtab_size;
--- 2013-10-07/opcodes/i386-opc.tbl
+++ 2013-10-07/opcodes/i386-opc.tbl
@@ -3064,9 +3064,9 @@ bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|N
bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND, RegBND }
bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND }
-bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
-bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
+bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
--- 2013-10-07/opcodes/i386-tbl.h
+++ 2013-10-07/opcodes/i386-tbl.h
@@ -53915,10 +53915,10 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
- { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -53930,10 +53930,10 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
- { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -53945,10 +53945,10 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
- 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
- { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ { { { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
next prev parent reply other threads:[~2013-10-08 14:43 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-08 14:36 [PATCH 0/6] x86: various MPX fixes Jan Beulich
2013-10-08 14:41 ` [PATCH 1/6] x86/MPX: testsuite adjustments Jan Beulich
2013-10-08 14:41 ` [PATCH 2/6] x86/MPX: fix address size handling Jan Beulich
2013-10-08 15:15 ` H.J. Lu
2013-10-08 15:20 ` Jan Beulich
2013-10-08 15:32 ` H.J. Lu
2013-10-09 7:30 ` Jan Beulich
2013-10-09 15:45 ` H.J. Lu
2013-10-10 12:27 ` Jan Beulich
2013-10-10 15:18 ` H.J. Lu
2013-10-08 14:42 ` [PATCH 3/6] x86/MPX: suppress base/index swapping in Intel mode for bndmk, bndldx, and bndstx Jan Beulich
2013-10-08 15:16 ` H.J. Lu
2013-10-08 15:23 ` Jan Beulich
2013-10-08 15:34 ` H.J. Lu
2013-10-08 16:00 ` Jan Beulich
2013-10-08 16:19 ` H.J. Lu
2013-10-09 7:15 ` acceptance rules (was: Re: [PATCH 3/6] x86/MPX: suppress base/index swapping ...) Jan Beulich
2013-10-09 16:45 ` H.J. Lu
2013-10-08 14:43 ` [PATCH 4/6] x86/MPX: bndmk, bndldx, and bndstx only allow a memory operand Jan Beulich
2013-10-08 15:28 ` H.J. Lu
2013-10-09 7:24 ` Jan Beulich
2013-10-09 15:17 ` H.J. Lu
2013-10-08 14:43 ` Jan Beulich [this message]
2013-10-08 15:45 ` [PATCH 5/6] x86/MPX: fix operand size handling H.J. Lu
2013-10-09 7:36 ` Jan Beulich
2013-10-09 15:51 ` H.J. Lu
2013-10-10 13:14 ` Jan Beulich
2013-10-10 15:14 ` H.J. Lu
2013-10-12 15:58 ` H.J. Lu
2013-10-12 17:12 ` H.J. Lu
2013-10-08 14:44 ` [PATCH 6/6] x86/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressing Jan Beulich
2013-10-08 16:13 ` H.J. Lu
2013-10-09 7:40 ` Jan Beulich
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