From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2577 invoked by alias); 9 Oct 2013 07:36:29 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 2568 invoked by uid 89); 9 Oct 2013 07:36:29 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: nat28.tlf.novell.com Received: from nat28.tlf.novell.com (HELO nat28.tlf.novell.com) (130.57.49.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 09 Oct 2013 07:36:28 +0000 Received: from EMEA1-MTA by nat28.tlf.novell.com with Novell_GroupWise; Wed, 09 Oct 2013 08:36:27 +0100 Message-Id: <5255239602000078000F9DE5@nat28.tlf.novell.com> Date: Wed, 09 Oct 2013 07:36:00 -0000 From: "Jan Beulich" To: "H.J. Lu" Cc: ,"Binutils" Subject: Re: [PATCH 5/6] x86/MPX: fix operand size handling References: <5254349502000078000F9A3D@nat28.tlf.novell.com> <5254364802000078000F9A5D@nat28.tlf.novell.com> In-Reply-To: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-SW-Source: 2013-10/txt/msg00108.txt.bz2 >>> On 08.10.13 at 17:45, "H.J. Lu" wrote: > On Tue, Oct 8, 2013 at 7:43 AM, Jan Beulich wrote: >> All MPX instructions in 64-bit mode ignore REX.W, which means we neither >> need to encode this bit nor should disassemble with 32-bit register >> operands. >> >> No MPX instructions would ever take a 16-bit register operand. >> >> gas/ >> 2013-10-08 Jan Beulich >> >> * tc-i386.c (process_suffix): Warn about 32-bit register operands >> to MPX instructions in 64-bit mode. >=20 > I think it should be an error. I can certainly change that - a warning just seemed a better match to hardware ignoring operand size here. >> opcodes/ >> 2013-10-08 Jan Beulich >> >> * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the >> default case. >> (OP_E_register): Move v_bnd_mode alongside m_mode. >> * i386-opc.h (REGNAM_RAX): New. >> * i386-opc.tbl (bndcl, bndcu, bndcn): Drop Reg16. Add NoRex64. >> * i386-tbl.h: Re-generate. >> >=20 > Should we also remove Disp16? Yes, we certainly could, but then also from the other MPX instructions. Logically this would belong into the address size fix patch though. Jan