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From: jiawei@iscas.ac.cn
To: christoph.muellner@vrull.eu
Cc: "binutils@sourceware.org" <binutils@sourceware.org>,
	 "Nelson Chu" <nelson@rivosinc.com>
Subject: Re: [RFC PATCH 0/6] RISC-V: Add support for vector crypto extensions
Date: Mon, 26 Dec 2022 19:51:50 +0800 (GMT+08:00)	[thread overview]
Message-ID: <533cd366.4c5b6.1854e46550b.Coremail.jiawei@iscas.ac.cn> (raw)

[-- Attachment #1: Type: text/plain, Size: 3132 bytes --]




I have some questions, since all vector cryptography extensions base on the vector registers, do we

need to add imply info or check info.




And if the vector version is available, should it also enable scalar version at the same time?







On Thu, Dec 22, 2022 at 1:08 AM Christoph Muellner
<christoph.muellner@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> This series add support for the vector crypto extensions:
> * Zvkb
> * Zvkg
> * Zvkh[a,b]
> * Zvkn
> * Zvksed
> * Zvksh
>
> The implementation follows the version 20221220 of the specification,
> which can be found here:
>   https://github.com/riscv/riscv-crypto/releases/tag/v20221220
>
> Note, that this specification is not frozen yet, meaning that
> incompatible changes are possible.
> Therefore, this patchset is marked as RFC and should not be considered
> for upstream inclusion.
>
> All extensions come with (passing) tests.
>
> A branch with all patches applied can be found in this GitHub repo:
>   https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk
>
> Christoph Müllner (6):
>   RISC-V: Add Zvkb ISA extension support
>   RISC-V: Add Zvkg ISA extension support
>   RISC-V: Add Zvkh[a,b] ISA extension support
>   RISC-V: Add Zvkn ISA extension support
>   RISC-V: Add Zvksed ISA extension support
>   RISC-V: Add Zvksh ISA extension support
>
>  bfd/elfxx-riscv.c                     |  38 +++++++++
>  gas/config/tc-riscv.c                 |  13 +++
>  gas/testsuite/gas/riscv/zvkb.d        |  36 ++++++++
>  gas/testsuite/gas/riscv/zvkb.s        |  28 +++++++
>  gas/testsuite/gas/riscv/zvkg.d        |   9 ++
>  gas/testsuite/gas/riscv/zvkg.s        |   1 +
>  gas/testsuite/gas/riscv/zvkha.d       |  12 +++
>  gas/testsuite/gas/riscv/zvkha_zvkhb.s |   3 +
>  gas/testsuite/gas/riscv/zvkhb.d       |  12 +++
>  gas/testsuite/gas/riscv/zvkn.d        |  21 +++++
>  gas/testsuite/gas/riscv/zvkn.s        |  13 +++
>  gas/testsuite/gas/riscv/zvksed.d      |  12 +++
>  gas/testsuite/gas/riscv/zvksed.s      |   4 +
>  gas/testsuite/gas/riscv/zvksh.d       |  11 +++
>  gas/testsuite/gas/riscv/zvksh.s       |   3 +
>  include/opcode/riscv-opc.h            | 114 ++++++++++++++++++++++++++
>  include/opcode/riscv.h                |  12 +++
>  opcodes/riscv-dis.c                   |   4 +
>  opcodes/riscv-opc.c                   |  46 +++++++++++
>  19 files changed, 392 insertions(+)
>  create mode 100644 gas/testsuite/gas/riscv/zvkb.d
>  create mode 100644 gas/testsuite/gas/riscv/zvkb.s
>  create mode 100644 gas/testsuite/gas/riscv/zvkg.d
>  create mode 100644 gas/testsuite/gas/riscv/zvkg.s
>  create mode 100644 gas/testsuite/gas/riscv/zvkha.d
>  create mode 100644 gas/testsuite/gas/riscv/zvkha_zvkhb.s
>  create mode 100644 gas/testsuite/gas/riscv/zvkhb.d
>  create mode 100644 gas/testsuite/gas/riscv/zvkn.d
>  create mode 100644 gas/testsuite/gas/riscv/zvkn.s
>  create mode 100644 gas/testsuite/gas/riscv/zvksed.d
>  create mode 100644 gas/testsuite/gas/riscv/zvksed.s
>  create mode 100644 gas/testsuite/gas/riscv/zvksh.d
>  create mode 100644 gas/testsuite/gas/riscv/zvksh.s
>
> --
> 2.38.1
>




             reply	other threads:[~2022-12-26 11:51 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-26 11:51 jiawei [this message]
  -- strict thread matches above, loose matches on Subject: below --
2022-12-21 17:07 Christoph Muellner
2022-12-22  2:46 ` Kito Cheng

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