From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [RFC PATCH 1/1] RISC-V: Implement extension variants
Date: Sat, 1 Oct 2022 05:27:31 +0000 [thread overview]
Message-ID: <53a265a1f14d17a6f7b106082f610994c5d546e0.1664602025.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1664602025.git.research_trasio@irq.a4lg.com>
If there is a instruction with multiple variants with different
requirements and the assembler fails to parse all variants, there is a case
that needs to refer ALL variants to generate proper diagnostics.
If an instruction with INSN_HAS_EXT_VARS fails on all variants, the
assembler now has a chance to modify the instruction class for proper
diagnostics. A typical use of this feature is to select _wider_ instruction
class when necessary.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add empty INSN_HAS_EXT_VARS
handling.
include/ChangeLog:
* opcode/riscv.h (INSN_HAS_EXT_VARS): New.
---
gas/config/tc-riscv.c | 27 +++++++++++++++++++++++++--
include/opcode/riscv.h | 5 +++++
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5e6fca3de9f..f83b0ff3dad 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2376,6 +2376,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
unsigned int regno;
const struct percent_op_match *p;
struct riscv_ip_error error;
+ enum riscv_insn_class insn_class;
error.msg = "unrecognized opcode";
error.statement = str;
error.missing_ext = NULL;
@@ -2402,8 +2403,30 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class))
{
- error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as,
- insn->insn_class);
+ insn_class = insn->insn_class;
+ if (insn->pinfo != INSN_MACRO && insn->pinfo & INSN_HAS_EXT_VARS)
+ {
+ /* If an instruction is not supported for example, there is a
+ case where some extensions (that is not related to the last
+ "same name" variants) should be printed for diagnostics.
+
+ For instance, if parsing "fmin.d" fails on both 'D' and
+ 'Zdinx' variants, we have to require 'D' or 'Zdinx', not just
+ 'Zdinx', the last "fmin.d" variant in riscv_opcodes.
+
+ For instructions with INSN_HAS_EXT_VARS, we should rewrite the
+ instruction class (from a specific one to a generic one)
+ to provide proper error output.
+ */
+ switch (insn_class)
+ {
+ default:
+ break;
+ }
+ }
+ if (!riscv_multi_subset_supports (&riscv_rps_as, insn_class))
+ error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as,
+ insn_class);
continue;
}
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index dd2569f6d55..3cfe132babe 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -496,6 +496,11 @@ struct riscv_opcode
#define INSN_8_BYTE 0x00000040
#define INSN_16_BYTE 0x00000050
+/* Instruction has different entry that shares the name but differs
+ in extension requirements (extension variants). Those instructions must be
+ taken care if we should print an "extension required" error. */
+#define INSN_HAS_EXT_VARS 0x00000080
+
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff
--
2.34.1
next prev parent reply other threads:[~2022-10-01 5:27 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-01 5:27 [RFC PATCH 0/1] RISC-V: Implement "extension variants" for diagnostics Tsukasa OI
2022-10-01 5:27 ` Tsukasa OI [this message]
2022-10-01 7:21 ` Nelson Chu
2022-10-01 8:25 ` Tsukasa OI
2022-10-06 11:12 ` Nelson Chu
2022-10-06 12:08 ` Tsukasa OI
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