From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 90852 invoked by alias); 16 Apr 2015 14:16:44 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 90838 invoked by uid 89); 16 Apr 2015 14:16:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail.emea.novell.com Received: from mail.emea.novell.com (HELO mail.emea.novell.com) (130.57.118.101) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Thu, 16 Apr 2015 14:16:38 +0000 Received: from EMEA1-MTA by mail.emea.novell.com with Novell_GroupWise; Thu, 16 Apr 2015 15:16:35 +0100 Message-Id: <552FE0630200007800072CD0@mail.emea.novell.com> Date: Thu, 16 Apr 2015 14:16:00 -0000 From: "Jan Beulich" To: Cc: "H.J. Lu" Subject: [PATCH] x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part85B1F253.1__=" X-SW-Source: 2015-04/txt/msg00250.txt.bz2 This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part85B1F253.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Content-length: 16577 As pointed out before, the documentation mandates the rounding mode to follow the GPR, so gas should accept such input. As the brojen code got released already we sadly will need to continue to also accept the badly ordered operands. gas/testsuite/ 2015-04-16 Jan Beulich * gas/i386/avx512f-intel.d: Adjust expectations on operand order. * gas/i386/evex-lig256-intel.d: Likewise. * gas/i386/evex-lig512-intel.d: Likewise. * gas/i386/x86-64-avx512f-intel.d: Likewise. * gas/i386/x86-64-evex-lig256-intel.d: Likewise. * gas/i386/x86-64-evex-lig512-intel.d: Likewise. opcodes/ 2015-04-16 Jan Beulich * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. * i386-tbl.h: Regenerate. --- 2015-04-16/gas/testsuite/gas/i386/avx512f.s +++ 2015-04-16/gas/testsuite/gas/i386/avx512f.s @@ -9904,14 +9904,14 @@ _start: vcvtsd2ss xmm6{k7}, xmm5, QWORD PTR [edx-1032] # AVX512F =20 =20 - vcvtsi2ss xmm6, xmm5, {rn-sae}, eax # AVX512F - vcvtsi2ss xmm6, xmm5, {ru-sae}, eax # AVX512F - vcvtsi2ss xmm6, xmm5, {rd-sae}, eax # AVX512F - vcvtsi2ss xmm6, xmm5, {rz-sae}, eax # AVX512F - vcvtsi2ss xmm6, xmm5, {rn-sae}, ebp # AVX512F - vcvtsi2ss xmm6, xmm5, {ru-sae}, ebp # AVX512F - vcvtsi2ss xmm6, xmm5, {rd-sae}, ebp # AVX512F - vcvtsi2ss xmm6, xmm5, {rz-sae}, ebp # AVX512F + vcvtsi2ss xmm6, xmm5, eax, {rn-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, eax, {ru-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, eax, {rd-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, eax, {rz-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, ebp, {rn-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, ebp, {ru-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, ebp, {rd-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, ebp, {rz-sae} # AVX512F =20 vcvtss2sd xmm6{k7}, xmm5, xmm4 # AVX512F vcvtss2sd xmm6{k7}{z}, xmm5, xmm4 # AVX512F @@ -13704,15 +13704,15 @@ _start: vcvtusi2sd xmm6, xmm5, DWORD PTR [edx-516] # AVX512F =20 vcvtusi2ss xmm6, xmm5, eax # AVX512F - vcvtusi2ss xmm6, xmm5, {rn-sae}, eax # AVX512F - vcvtusi2ss xmm6, xmm5, {ru-sae}, eax # AVX512F - vcvtusi2ss xmm6, xmm5, {rd-sae}, eax # AVX512F - vcvtusi2ss xmm6, xmm5, {rz-sae}, eax # AVX512F + vcvtusi2ss xmm6, xmm5, eax, {rn-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, eax, {ru-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, eax, {rd-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, eax, {rz-sae} # AVX512F vcvtusi2ss xmm6, xmm5, ebp # AVX512F - vcvtusi2ss xmm6, xmm5, {rn-sae}, ebp # AVX512F - vcvtusi2ss xmm6, xmm5, {ru-sae}, ebp # AVX512F - vcvtusi2ss xmm6, xmm5, {rd-sae}, ebp # AVX512F - vcvtusi2ss xmm6, xmm5, {rz-sae}, ebp # AVX512F + vcvtusi2ss xmm6, xmm5, ebp, {rn-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, ebp, {ru-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, ebp, {rd-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, ebp, {rz-sae} # AVX512F vcvtusi2ss xmm6, xmm5, DWORD PTR [ecx] # AVX512F vcvtusi2ss xmm6, xmm5, DWORD PTR [esp+esi*8-123456] # AVX512F vcvtusi2ss xmm6, xmm5, DWORD PTR [edx+508] # AVX512F Disp8 --- 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512f.s +++ 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512f.s @@ -10339,15 +10339,15 @@ _start: vcvtsi2sd xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F =20 vcvtsi2sd xmm30, xmm29, rax # AVX512F - vcvtsi2sd xmm30, xmm29, {rn-sae}, rax # AVX512F - vcvtsi2sd xmm30, xmm29, {ru-sae}, rax # AVX512F - vcvtsi2sd xmm30, xmm29, {rd-sae}, rax # AVX512F - vcvtsi2sd xmm30, xmm29, {rz-sae}, rax # AVX512F + vcvtsi2sd xmm30, xmm29, rax, {rn-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, rax, {ru-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, rax, {rd-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, rax, {rz-sae} # AVX512F vcvtsi2sd xmm30, xmm29, r8 # AVX512F - vcvtsi2sd xmm30, xmm29, {rn-sae}, r8 # AVX512F - vcvtsi2sd xmm30, xmm29, {ru-sae}, r8 # AVX512F - vcvtsi2sd xmm30, xmm29, {rd-sae}, r8 # AVX512F - vcvtsi2sd xmm30, xmm29, {rz-sae}, r8 # AVX512F + vcvtsi2sd xmm30, xmm29, r8, {rn-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, r8, {ru-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, r8, {rd-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, r8, {rz-sae} # AVX512F vcvtsi2sd xmm30, xmm29, QWORD PTR [rcx] # AVX512F vcvtsi2sd xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtsi2sd xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8 @@ -10356,20 +10356,20 @@ _start: vcvtsi2sd xmm30, xmm29, QWORD PTR [rdx-1032] # AVX512F =20 vcvtsi2ss xmm30, xmm29, eax # AVX512F - vcvtsi2ss xmm30, xmm29, {rn-sae}, eax # AVX512F - vcvtsi2ss xmm30, xmm29, {ru-sae}, eax # AVX512F - vcvtsi2ss xmm30, xmm29, {rd-sae}, eax # AVX512F - vcvtsi2ss xmm30, xmm29, {rz-sae}, eax # AVX512F + vcvtsi2ss xmm30, xmm29, eax, {rn-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, eax, {ru-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, eax, {rd-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, eax, {rz-sae} # AVX512F vcvtsi2ss xmm30, xmm29, ebp # AVX512F - vcvtsi2ss xmm30, xmm29, {rn-sae}, ebp # AVX512F - vcvtsi2ss xmm30, xmm29, {ru-sae}, ebp # AVX512F - vcvtsi2ss xmm30, xmm29, {rd-sae}, ebp # AVX512F - vcvtsi2ss xmm30, xmm29, {rz-sae}, ebp # AVX512F + vcvtsi2ss xmm30, xmm29, ebp, {rn-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, ebp, {ru-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, ebp, {rd-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, ebp, {rz-sae} # AVX512F vcvtsi2ss xmm30, xmm29, r13d # AVX512F - vcvtsi2ss xmm30, xmm29, {rn-sae}, r13d # AVX512F - vcvtsi2ss xmm30, xmm29, {ru-sae}, r13d # AVX512F - vcvtsi2ss xmm30, xmm29, {rd-sae}, r13d # AVX512F - vcvtsi2ss xmm30, xmm29, {rz-sae}, r13d # AVX512F + vcvtsi2ss xmm30, xmm29, r13d, {rn-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r13d, {ru-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r13d, {rd-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r13d, {rz-sae} # AVX512F vcvtsi2ss xmm30, xmm29, DWORD PTR [rcx] # AVX512F vcvtsi2ss xmm30, xmm29, DWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtsi2ss xmm30, xmm29, DWORD PTR [rdx+508] # AVX512F Disp8 @@ -10378,15 +10378,15 @@ _start: vcvtsi2ss xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F =20 vcvtsi2ss xmm30, xmm29, rax # AVX512F - vcvtsi2ss xmm30, xmm29, {rn-sae}, rax # AVX512F - vcvtsi2ss xmm30, xmm29, {ru-sae}, rax # AVX512F - vcvtsi2ss xmm30, xmm29, {rd-sae}, rax # AVX512F - vcvtsi2ss xmm30, xmm29, {rz-sae}, rax # AVX512F + vcvtsi2ss xmm30, xmm29, rax, {rn-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, rax, {ru-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, rax, {rd-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, rax, {rz-sae} # AVX512F vcvtsi2ss xmm30, xmm29, r8 # AVX512F - vcvtsi2ss xmm30, xmm29, {rn-sae}, r8 # AVX512F - vcvtsi2ss xmm30, xmm29, {ru-sae}, r8 # AVX512F - vcvtsi2ss xmm30, xmm29, {rd-sae}, r8 # AVX512F - vcvtsi2ss xmm30, xmm29, {rz-sae}, r8 # AVX512F + vcvtsi2ss xmm30, xmm29, r8, {rn-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r8, {ru-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r8, {rd-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r8, {rz-sae} # AVX512F vcvtsi2ss xmm30, xmm29, QWORD PTR [rcx] # AVX512F vcvtsi2ss xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtsi2ss xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8 @@ -14409,15 +14409,15 @@ _start: vcvtusi2sd xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F =20 vcvtusi2sd xmm30, xmm29, rax # AVX512F - vcvtusi2sd xmm30, xmm29, {rn-sae}, rax # AVX512F - vcvtusi2sd xmm30, xmm29, {ru-sae}, rax # AVX512F - vcvtusi2sd xmm30, xmm29, {rd-sae}, rax # AVX512F - vcvtusi2sd xmm30, xmm29, {rz-sae}, rax # AVX512F + vcvtusi2sd xmm30, xmm29, rax, {rn-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, rax, {ru-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, rax, {rd-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, rax, {rz-sae} # AVX512F vcvtusi2sd xmm30, xmm29, r8 # AVX512F - vcvtusi2sd xmm30, xmm29, {rn-sae}, r8 # AVX512F - vcvtusi2sd xmm30, xmm29, {ru-sae}, r8 # AVX512F - vcvtusi2sd xmm30, xmm29, {rd-sae}, r8 # AVX512F - vcvtusi2sd xmm30, xmm29, {rz-sae}, r8 # AVX512F + vcvtusi2sd xmm30, xmm29, r8, {rn-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, r8, {ru-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, r8, {rd-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, r8, {rz-sae} # AVX512F vcvtusi2sd xmm30, xmm29, QWORD PTR [rcx] # AVX512F vcvtusi2sd xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtusi2sd xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8 @@ -14426,20 +14426,20 @@ _start: vcvtusi2sd xmm30, xmm29, QWORD PTR [rdx-1032] # AVX512F =20 vcvtusi2ss xmm30, xmm29, eax # AVX512F - vcvtusi2ss xmm30, xmm29, {rn-sae}, eax # AVX512F - vcvtusi2ss xmm30, xmm29, {ru-sae}, eax # AVX512F - vcvtusi2ss xmm30, xmm29, {rd-sae}, eax # AVX512F - vcvtusi2ss xmm30, xmm29, {rz-sae}, eax # AVX512F + vcvtusi2ss xmm30, xmm29, eax, {rn-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, eax, {ru-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, eax, {rd-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, eax, {rz-sae} # AVX512F vcvtusi2ss xmm30, xmm29, ebp # AVX512F - vcvtusi2ss xmm30, xmm29, {rn-sae}, ebp # AVX512F - vcvtusi2ss xmm30, xmm29, {ru-sae}, ebp # AVX512F - vcvtusi2ss xmm30, xmm29, {rd-sae}, ebp # AVX512F - vcvtusi2ss xmm30, xmm29, {rz-sae}, ebp # AVX512F + vcvtusi2ss xmm30, xmm29, ebp, {rn-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, ebp, {ru-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, ebp, {rd-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, ebp, {rz-sae} # AVX512F vcvtusi2ss xmm30, xmm29, r13d # AVX512F - vcvtusi2ss xmm30, xmm29, {rn-sae}, r13d # AVX512F - vcvtusi2ss xmm30, xmm29, {ru-sae}, r13d # AVX512F - vcvtusi2ss xmm30, xmm29, {rd-sae}, r13d # AVX512F - vcvtusi2ss xmm30, xmm29, {rz-sae}, r13d # AVX512F + vcvtusi2ss xmm30, xmm29, r13d, {rn-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r13d, {ru-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r13d, {rd-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r13d, {rz-sae} # AVX512F vcvtusi2ss xmm30, xmm29, DWORD PTR [rcx] # AVX512F vcvtusi2ss xmm30, xmm29, DWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtusi2ss xmm30, xmm29, DWORD PTR [rdx+508] # AVX512F Disp8 @@ -14448,15 +14448,15 @@ _start: vcvtusi2ss xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F =20 vcvtusi2ss xmm30, xmm29, rax # AVX512F - vcvtusi2ss xmm30, xmm29, {rn-sae}, rax # AVX512F - vcvtusi2ss xmm30, xmm29, {ru-sae}, rax # AVX512F - vcvtusi2ss xmm30, xmm29, {rd-sae}, rax # AVX512F - vcvtusi2ss xmm30, xmm29, {rz-sae}, rax # AVX512F + vcvtusi2ss xmm30, xmm29, rax, {rn-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, rax, {ru-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, rax, {rd-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, rax, {rz-sae} # AVX512F vcvtusi2ss xmm30, xmm29, r8 # AVX512F - vcvtusi2ss xmm30, xmm29, {rn-sae}, r8 # AVX512F - vcvtusi2ss xmm30, xmm29, {ru-sae}, r8 # AVX512F - vcvtusi2ss xmm30, xmm29, {rd-sae}, r8 # AVX512F - vcvtusi2ss xmm30, xmm29, {rz-sae}, r8 # AVX512F + vcvtusi2ss xmm30, xmm29, r8, {rn-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r8, {ru-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r8, {rd-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r8, {rz-sae} # AVX512F vcvtusi2ss xmm30, xmm29, QWORD PTR [rcx] # AVX512F vcvtusi2ss xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtusi2ss xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8 --- 2015-04-16/opcodes/i386-opc.tbl +++ 2015-04-16/opcodes/i386-opc.tbl @@ -3648,18 +3648,24 @@ vcvtsd2ss, 4, 0xF25A, None, 1, CpuAVX512 vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|Ve= xVVVV=3D1|VexW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_= qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp= 32S|Vec_Disp8, RegXMM, RegXMM } vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|Disp8MemShift=3D3|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp= 8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM } +vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegX= MM } vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|V= exVVVV=3D1|VexW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No= _qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Dis= p32S|Vec_Disp8, RegXMM, RegXMM } vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|Disp8MemShift=3D3|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp= 8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM } +vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegX= MM } =20 vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|Ve= xVVVV=3D1|VexW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_= qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp= 32S|Vec_Disp8, RegXMM, RegXMM } vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|Ve= xVVVV=3D1|VexW=3D1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Stat= icRounding|SAE, { Reg32, Imm8, RegXMM, RegXMM } +vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|Ve= xVVVV=3D1|VexW=3D1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Stat= icRounding|SAE|IntelSyntax, { Imm8, Reg32, RegXMM, RegXMM } vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|Disp8MemShift=3D3|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp= 8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM } +vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegX= MM } vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|V= exVVVV=3D1|VexW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No= _qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Dis= p32S|Vec_Disp8, RegXMM, RegXMM } vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|V= exVVVV=3D1|VexW=3D1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Sta= ticRounding|SAE, { Reg32, Imm8, RegXMM, RegXMM } +vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|V= exVVVV=3D1|VexW=3D1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Sta= ticRounding|SAE|IntelSyntax, { Imm8, Reg32, RegXMM, RegXMM } vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|Disp8MemShift=3D3|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp= 8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM } +vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegX= MM } =20 vcvtss2sd, 3, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=3D4|Masking=3D3|VexO= pcode=3D0|VexVVVV=3D1|VexW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Dis= p8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } vcvtss2sd, 4, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=3D4|Masking=3D3|VexO= pcode=3D0|VexVVVV=3D1|VexW=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM } --=__Part85B1F253.1__= Content-Type: text/plain; name="binutils-master-x86-AVX512F-scalar-convert-asm.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="binutils-master-x86-AVX512F-scalar-convert-asm.patch" Content-length: 26799 x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} As pointed out before, the documentation mandates the rounding mode to follow the GPR, so gas should accept such input. As the brojen code got released already we sadly will need to continue to also accept the badly ordered operands. gas/testsuite/ 2015-04-16 Jan Beulich * gas/i386/avx512f-intel.d: Adjust expectations on operand order. * gas/i386/evex-lig256-intel.d: Likewise. * gas/i386/evex-lig512-intel.d: Likewise. * gas/i386/x86-64-avx512f-intel.d: Likewise. * gas/i386/x86-64-evex-lig256-intel.d: Likewise. * gas/i386/x86-64-evex-lig512-intel.d: Likewise. opcodes/ 2015-04-16 Jan Beulich * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. * i386-tbl.h: Regenerate. --- 2015-04-16/gas/testsuite/gas/i386/avx512f.s +++ 2015-04-16/gas/testsuite/gas/i386/avx512f.s @@ -9904,14 +9904,14 @@ _start: vcvtsd2ss xmm6{k7}, xmm5, QWORD PTR [edx-1032] # AVX512F =20 =20 - vcvtsi2ss xmm6, xmm5, {rn-sae}, eax # AVX512F - vcvtsi2ss xmm6, xmm5, {ru-sae}, eax # AVX512F - vcvtsi2ss xmm6, xmm5, {rd-sae}, eax # AVX512F - vcvtsi2ss xmm6, xmm5, {rz-sae}, eax # AVX512F - vcvtsi2ss xmm6, xmm5, {rn-sae}, ebp # AVX512F - vcvtsi2ss xmm6, xmm5, {ru-sae}, ebp # AVX512F - vcvtsi2ss xmm6, xmm5, {rd-sae}, ebp # AVX512F - vcvtsi2ss xmm6, xmm5, {rz-sae}, ebp # AVX512F + vcvtsi2ss xmm6, xmm5, eax, {rn-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, eax, {ru-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, eax, {rd-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, eax, {rz-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, ebp, {rn-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, ebp, {ru-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, ebp, {rd-sae} # AVX512F + vcvtsi2ss xmm6, xmm5, ebp, {rz-sae} # AVX512F =20 vcvtss2sd xmm6{k7}, xmm5, xmm4 # AVX512F vcvtss2sd xmm6{k7}{z}, xmm5, xmm4 # AVX512F @@ -13704,15 +13704,15 @@ _start: vcvtusi2sd xmm6, xmm5, DWORD PTR [edx-516] # AVX512F =20 vcvtusi2ss xmm6, xmm5, eax # AVX512F - vcvtusi2ss xmm6, xmm5, {rn-sae}, eax # AVX512F - vcvtusi2ss xmm6, xmm5, {ru-sae}, eax # AVX512F - vcvtusi2ss xmm6, xmm5, {rd-sae}, eax # AVX512F - vcvtusi2ss xmm6, xmm5, {rz-sae}, eax # AVX512F + vcvtusi2ss xmm6, xmm5, eax, {rn-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, eax, {ru-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, eax, {rd-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, eax, {rz-sae} # AVX512F vcvtusi2ss xmm6, xmm5, ebp # AVX512F - vcvtusi2ss xmm6, xmm5, {rn-sae}, ebp # AVX512F - vcvtusi2ss xmm6, xmm5, {ru-sae}, ebp # AVX512F - vcvtusi2ss xmm6, xmm5, {rd-sae}, ebp # AVX512F - vcvtusi2ss xmm6, xmm5, {rz-sae}, ebp # AVX512F + vcvtusi2ss xmm6, xmm5, ebp, {rn-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, ebp, {ru-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, ebp, {rd-sae} # AVX512F + vcvtusi2ss xmm6, xmm5, ebp, {rz-sae} # AVX512F vcvtusi2ss xmm6, xmm5, DWORD PTR [ecx] # AVX512F vcvtusi2ss xmm6, xmm5, DWORD PTR [esp+esi*8-123456] # AVX512F vcvtusi2ss xmm6, xmm5, DWORD PTR [edx+508] # AVX512F Disp8 --- 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512f.s +++ 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512f.s @@ -10339,15 +10339,15 @@ _start: vcvtsi2sd xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F =20 vcvtsi2sd xmm30, xmm29, rax # AVX512F - vcvtsi2sd xmm30, xmm29, {rn-sae}, rax # AVX512F - vcvtsi2sd xmm30, xmm29, {ru-sae}, rax # AVX512F - vcvtsi2sd xmm30, xmm29, {rd-sae}, rax # AVX512F - vcvtsi2sd xmm30, xmm29, {rz-sae}, rax # AVX512F + vcvtsi2sd xmm30, xmm29, rax, {rn-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, rax, {ru-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, rax, {rd-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, rax, {rz-sae} # AVX512F vcvtsi2sd xmm30, xmm29, r8 # AVX512F - vcvtsi2sd xmm30, xmm29, {rn-sae}, r8 # AVX512F - vcvtsi2sd xmm30, xmm29, {ru-sae}, r8 # AVX512F - vcvtsi2sd xmm30, xmm29, {rd-sae}, r8 # AVX512F - vcvtsi2sd xmm30, xmm29, {rz-sae}, r8 # AVX512F + vcvtsi2sd xmm30, xmm29, r8, {rn-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, r8, {ru-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, r8, {rd-sae} # AVX512F + vcvtsi2sd xmm30, xmm29, r8, {rz-sae} # AVX512F vcvtsi2sd xmm30, xmm29, QWORD PTR [rcx] # AVX512F vcvtsi2sd xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtsi2sd xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8 @@ -10356,20 +10356,20 @@ _start: vcvtsi2sd xmm30, xmm29, QWORD PTR [rdx-1032] # AVX512F =20 vcvtsi2ss xmm30, xmm29, eax # AVX512F - vcvtsi2ss xmm30, xmm29, {rn-sae}, eax # AVX512F - vcvtsi2ss xmm30, xmm29, {ru-sae}, eax # AVX512F - vcvtsi2ss xmm30, xmm29, {rd-sae}, eax # AVX512F - vcvtsi2ss xmm30, xmm29, {rz-sae}, eax # AVX512F + vcvtsi2ss xmm30, xmm29, eax, {rn-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, eax, {ru-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, eax, {rd-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, eax, {rz-sae} # AVX512F vcvtsi2ss xmm30, xmm29, ebp # AVX512F - vcvtsi2ss xmm30, xmm29, {rn-sae}, ebp # AVX512F - vcvtsi2ss xmm30, xmm29, {ru-sae}, ebp # AVX512F - vcvtsi2ss xmm30, xmm29, {rd-sae}, ebp # AVX512F - vcvtsi2ss xmm30, xmm29, {rz-sae}, ebp # AVX512F + vcvtsi2ss xmm30, xmm29, ebp, {rn-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, ebp, {ru-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, ebp, {rd-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, ebp, {rz-sae} # AVX512F vcvtsi2ss xmm30, xmm29, r13d # AVX512F - vcvtsi2ss xmm30, xmm29, {rn-sae}, r13d # AVX512F - vcvtsi2ss xmm30, xmm29, {ru-sae}, r13d # AVX512F - vcvtsi2ss xmm30, xmm29, {rd-sae}, r13d # AVX512F - vcvtsi2ss xmm30, xmm29, {rz-sae}, r13d # AVX512F + vcvtsi2ss xmm30, xmm29, r13d, {rn-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r13d, {ru-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r13d, {rd-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r13d, {rz-sae} # AVX512F vcvtsi2ss xmm30, xmm29, DWORD PTR [rcx] # AVX512F vcvtsi2ss xmm30, xmm29, DWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtsi2ss xmm30, xmm29, DWORD PTR [rdx+508] # AVX512F Disp8 @@ -10378,15 +10378,15 @@ _start: vcvtsi2ss xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F =20 vcvtsi2ss xmm30, xmm29, rax # AVX512F - vcvtsi2ss xmm30, xmm29, {rn-sae}, rax # AVX512F - vcvtsi2ss xmm30, xmm29, {ru-sae}, rax # AVX512F - vcvtsi2ss xmm30, xmm29, {rd-sae}, rax # AVX512F - vcvtsi2ss xmm30, xmm29, {rz-sae}, rax # AVX512F + vcvtsi2ss xmm30, xmm29, rax, {rn-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, rax, {ru-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, rax, {rd-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, rax, {rz-sae} # AVX512F vcvtsi2ss xmm30, xmm29, r8 # AVX512F - vcvtsi2ss xmm30, xmm29, {rn-sae}, r8 # AVX512F - vcvtsi2ss xmm30, xmm29, {ru-sae}, r8 # AVX512F - vcvtsi2ss xmm30, xmm29, {rd-sae}, r8 # AVX512F - vcvtsi2ss xmm30, xmm29, {rz-sae}, r8 # AVX512F + vcvtsi2ss xmm30, xmm29, r8, {rn-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r8, {ru-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r8, {rd-sae} # AVX512F + vcvtsi2ss xmm30, xmm29, r8, {rz-sae} # AVX512F vcvtsi2ss xmm30, xmm29, QWORD PTR [rcx] # AVX512F vcvtsi2ss xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtsi2ss xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8 @@ -14409,15 +14409,15 @@ _start: vcvtusi2sd xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F =20 vcvtusi2sd xmm30, xmm29, rax # AVX512F - vcvtusi2sd xmm30, xmm29, {rn-sae}, rax # AVX512F - vcvtusi2sd xmm30, xmm29, {ru-sae}, rax # AVX512F - vcvtusi2sd xmm30, xmm29, {rd-sae}, rax # AVX512F - vcvtusi2sd xmm30, xmm29, {rz-sae}, rax # AVX512F + vcvtusi2sd xmm30, xmm29, rax, {rn-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, rax, {ru-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, rax, {rd-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, rax, {rz-sae} # AVX512F vcvtusi2sd xmm30, xmm29, r8 # AVX512F - vcvtusi2sd xmm30, xmm29, {rn-sae}, r8 # AVX512F - vcvtusi2sd xmm30, xmm29, {ru-sae}, r8 # AVX512F - vcvtusi2sd xmm30, xmm29, {rd-sae}, r8 # AVX512F - vcvtusi2sd xmm30, xmm29, {rz-sae}, r8 # AVX512F + vcvtusi2sd xmm30, xmm29, r8, {rn-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, r8, {ru-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, r8, {rd-sae} # AVX512F + vcvtusi2sd xmm30, xmm29, r8, {rz-sae} # AVX512F vcvtusi2sd xmm30, xmm29, QWORD PTR [rcx] # AVX512F vcvtusi2sd xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtusi2sd xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8 @@ -14426,20 +14426,20 @@ _start: vcvtusi2sd xmm30, xmm29, QWORD PTR [rdx-1032] # AVX512F =20 vcvtusi2ss xmm30, xmm29, eax # AVX512F - vcvtusi2ss xmm30, xmm29, {rn-sae}, eax # AVX512F - vcvtusi2ss xmm30, xmm29, {ru-sae}, eax # AVX512F - vcvtusi2ss xmm30, xmm29, {rd-sae}, eax # AVX512F - vcvtusi2ss xmm30, xmm29, {rz-sae}, eax # AVX512F + vcvtusi2ss xmm30, xmm29, eax, {rn-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, eax, {ru-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, eax, {rd-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, eax, {rz-sae} # AVX512F vcvtusi2ss xmm30, xmm29, ebp # AVX512F - vcvtusi2ss xmm30, xmm29, {rn-sae}, ebp # AVX512F - vcvtusi2ss xmm30, xmm29, {ru-sae}, ebp # AVX512F - vcvtusi2ss xmm30, xmm29, {rd-sae}, ebp # AVX512F - vcvtusi2ss xmm30, xmm29, {rz-sae}, ebp # AVX512F + vcvtusi2ss xmm30, xmm29, ebp, {rn-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, ebp, {ru-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, ebp, {rd-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, ebp, {rz-sae} # AVX512F vcvtusi2ss xmm30, xmm29, r13d # AVX512F - vcvtusi2ss xmm30, xmm29, {rn-sae}, r13d # AVX512F - vcvtusi2ss xmm30, xmm29, {ru-sae}, r13d # AVX512F - vcvtusi2ss xmm30, xmm29, {rd-sae}, r13d # AVX512F - vcvtusi2ss xmm30, xmm29, {rz-sae}, r13d # AVX512F + vcvtusi2ss xmm30, xmm29, r13d, {rn-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r13d, {ru-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r13d, {rd-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r13d, {rz-sae} # AVX512F vcvtusi2ss xmm30, xmm29, DWORD PTR [rcx] # AVX512F vcvtusi2ss xmm30, xmm29, DWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtusi2ss xmm30, xmm29, DWORD PTR [rdx+508] # AVX512F Disp8 @@ -14448,15 +14448,15 @@ _start: vcvtusi2ss xmm30, xmm29, DWORD PTR [rdx-516] # AVX512F =20 vcvtusi2ss xmm30, xmm29, rax # AVX512F - vcvtusi2ss xmm30, xmm29, {rn-sae}, rax # AVX512F - vcvtusi2ss xmm30, xmm29, {ru-sae}, rax # AVX512F - vcvtusi2ss xmm30, xmm29, {rd-sae}, rax # AVX512F - vcvtusi2ss xmm30, xmm29, {rz-sae}, rax # AVX512F + vcvtusi2ss xmm30, xmm29, rax, {rn-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, rax, {ru-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, rax, {rd-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, rax, {rz-sae} # AVX512F vcvtusi2ss xmm30, xmm29, r8 # AVX512F - vcvtusi2ss xmm30, xmm29, {rn-sae}, r8 # AVX512F - vcvtusi2ss xmm30, xmm29, {ru-sae}, r8 # AVX512F - vcvtusi2ss xmm30, xmm29, {rd-sae}, r8 # AVX512F - vcvtusi2ss xmm30, xmm29, {rz-sae}, r8 # AVX512F + vcvtusi2ss xmm30, xmm29, r8, {rn-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r8, {ru-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r8, {rd-sae} # AVX512F + vcvtusi2ss xmm30, xmm29, r8, {rz-sae} # AVX512F vcvtusi2ss xmm30, xmm29, QWORD PTR [rcx] # AVX512F vcvtusi2ss xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234] # AVX512F vcvtusi2ss xmm30, xmm29, QWORD PTR [rdx+1016] # AVX512F Disp8 --- 2015-04-16/opcodes/i386-opc.tbl +++ 2015-04-16/opcodes/i386-opc.tbl @@ -3648,18 +3648,24 @@ vcvtsd2ss, 4, 0xF25A, None, 1, CpuAVX512 vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|Ve= xVVVV=3D1|VexW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_= qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp= 32S|Vec_Disp8, RegXMM, RegXMM } vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|Disp8MemShift=3D3|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp= 8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM } +vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegX= MM } vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|V= exVVVV=3D1|VexW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No= _qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Dis= p32S|Vec_Disp8, RegXMM, RegXMM } vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|Disp8MemShift=3D3|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp= 8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM } +vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegX= MM } =20 vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|Ve= xVVVV=3D1|VexW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_= qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp= 32S|Vec_Disp8, RegXMM, RegXMM } vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|Ve= xVVVV=3D1|VexW=3D1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Stat= icRounding|SAE, { Reg32, Imm8, RegXMM, RegXMM } +vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|Ve= xVVVV=3D1|VexW=3D1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Stat= icRounding|SAE|IntelSyntax, { Imm8, Reg32, RegXMM, RegXMM } vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|Disp8MemShift=3D3|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp= 8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM } +vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegX= MM } vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|V= exVVVV=3D1|VexW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No= _qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Dis= p32S|Vec_Disp8, RegXMM, RegXMM } vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|V= exVVVV=3D1|VexW=3D1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Sta= ticRounding|SAE, { Reg32, Imm8, RegXMM, RegXMM } +vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=3D4|VexOpcode=3D0|V= exVVVV=3D1|VexW=3D1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Sta= ticRounding|SAE|IntelSyntax, { Imm8, Reg32, RegXMM, RegXMM } vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|Disp8MemShift=3D3|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp= 8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM } +vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=3D4|VexOpcode= =3D0|VexVVVV=3D1|VexW=3D2|VecESize=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegX= MM } =20 vcvtss2sd, 3, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=3D4|Masking=3D3|VexO= pcode=3D0|VexVVVV=3D1|VexW=3D1|Disp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Dis= p8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM } vcvtss2sd, 4, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=3D4|Masking=3D3|VexO= pcode=3D0|VexVVVV=3D1|VexW=3D1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM } --- 2015-04-16/opcodes/i386-tbl.h +++ 2015-04-16/opcodes/i386-tbl.h @@ -36698,6 +36698,28 @@ const insn_template i386_optab[] =3D { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { "vcvtsi2sd", 4, 0xF22A, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 4, 0, 1, 0, 1, 1, 0, 0, 0, 0, + 0, 1 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { "vcvtsi2ss", 3, 0xf32a, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -36777,6 +36799,28 @@ const insn_template i386_optab[] =3D { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { "vcvtsi2ss", 4, 0xF32A, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, + 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 1, 1, 0, 0, 0, 0, + 0, 1 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { "vcvtsi2ss", 3, 0xF32A, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, @@ -36818,6 +36862,28 @@ const insn_template i386_optab[] =3D { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { "vcvtsi2ss", 4, 0xF32A, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 4, 0, 1, 0, 1, 1, 0, 0, 0, 0, + 0, 1 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { "vcvtss2sd", 3, 0xf35a, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -76662,6 +76728,28 @@ const insn_template i386_optab[] =3D { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { "vcvtusi2sd", 4, 0xF27B, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 4, 0, 1, 0, 1, 1, 0, 0, 0, 0, + 0, 1 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { "vcvtusi2ss", 3, 0xF37B, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, @@ -76703,6 +76791,28 @@ const insn_template i386_optab[] =3D { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { "vcvtusi2ss", 4, 0xF37B, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, + 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 1, 1, 0, 0, 0, 0, + 0, 1 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { "vcvtusi2ss", 3, 0xF37B, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, @@ -76744,6 +76854,28 @@ const insn_template i386_optab[] =3D { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, + { "vcvtusi2ss", 4, 0xF37B, None, 1, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, + 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 4, 0, 1, 0, 1, 1, 0, 0, 0, 0, + 0, 1 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { "vcvtss2usi", 2, 0xF379, None, 1, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, --=__Part85B1F253.1__=--