From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 17821 invoked by alias); 20 Apr 2015 10:34:02 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 17802 invoked by uid 89); 20 Apr 2015 10:34:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 20 Apr 2015 10:33:59 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-17.uk.mimecast.lan; Mon, 20 Apr 2015 11:33:56 +0100 Received: from [10.2.207.14] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 20 Apr 2015 11:33:56 +0100 Message-ID: <5534D613.9020109@arm.com> Date: Mon, 20 Apr 2015 10:34:00 -0000 From: Renlin Li User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: "binutils@sourceware.org" CC: Nicholas Clifton , Ramana.Radhakrishnan@arm.com, Marcus Shawcroft Subject: [GAS][AARCH64]Don't try to align insn in non-executale section. X-MC-Unique: YsS8vom_Truar-LFOMQkkQ-1 Content-Type: multipart/mixed; boundary="------------020705010302030506010702" X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg00298.txt.bz2 This is a multi-part message in MIME format. --------------020705010302030506010702 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Content-length: 1396 Hi all, After my previous patch, instruction will always try to align itself in=20 non-text section. https://sourceware.org/ml/binutils/2015-03/msg00389.html However, this is not required. Only the text section has strict=20 alignment requirements. For other section, just leave as it is. This fixes the latest Linux kernel build with aarch64 tool-chain. We have got the following assembler in kernel code.=20 .altinstr_replacement is not a executable section. with the previous=20 patch, gas will try to align the ldarb insn, creating a new frag which=20 is different for the one .L663 in. ".if" directive later complains about this: '''Error: non-constant=20 expression in ".if" statement''' 661: ldrb w3, [x1] 662: .pushsection .altinstructions,"a" .word 661b - . .word 663f - . .hword 1 .byte 662b-661b .byte 664f-663f .popsection .pushsection .altinstr_replacement, "a" 663: ldarb w3, [x1] 664: .popsection .if ((664b-663b) !=3D (662b-661b)) .error "Alternatives instruction length mismatch" .endif With the patch, the behavior should be restored. Binuitls regression=20 test runs Okay. Okay to commit? Regards, Renlin Li gas/ChangeLog: 2015-04-20 Renlin Li * config/tc-aarch64.c (s_aarch64_inst): Don't align code for non-text section. (md_assemble): Likewise, move the align code outside the loop. --------------020705010302030506010702 Content-Type: text/x-patch; name=patch.diff Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="patch.diff" Content-length: 2160 diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 5492ff4..9e4738a 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -1858,10 +1858,9 @@ s_aarch64_inst (int ignored ATTRIBUTE_UNUSED) /* Sections are assumed to start aligned. In executable section, there i= s no MAP_DATA symbol pending. So we only align the address during MAP_DATA --> MAP_INSN transition. - For other sections, this is not guaranteed, align it anyway. */ + For other sections, this is not guaranteed. */ enum mstate mapstate =3D seg_info (now_seg)->tc_segment_info_data.mapsta= te; - if (!need_pass_2 && ((subseg_text_p (now_seg) && mapstate =3D=3D MAP_DAT= A) - || !subseg_text_p (now_seg))) + if (!need_pass_2 && subseg_text_p (now_seg) && mapstate =3D=3D MAP_DATA) frag_align_code (2, 0); =20 #ifdef OBJ_ELF @@ -5690,6 +5689,14 @@ md_assemble (char *str) =20 init_operand_error_report (); =20 + /* Sections are assumed to start aligned. In executable section, there i= s no + MAP_DATA symbol pending. So we only align the address during + MAP_DATA --> MAP_INSN transition. + For other sections, this is not guaranteed. */ + enum mstate mapstate =3D seg_info (now_seg)->tc_segment_info_data.mapsta= te; + if (!need_pass_2 && subseg_text_p (now_seg) && mapstate =3D=3D MAP_DATA) + frag_align_code (2, 0); + saved_cond =3D inst.cond; reset_aarch64_instruction (&inst); inst.cond =3D saved_cond; @@ -5705,15 +5712,6 @@ md_assemble (char *str) dump_opcode_operands (opcode); #endif /* DEBUG_AARCH64 */ =20 - /* Sections are assumed to start aligned. In executable section, there= is no - MAP_DATA symbol pending. So we only align the address during - MAP_DATA --> MAP_INSN transition. - For other sections, this is not guaranteed, align it anyway. */ - enum mstate mapstate =3D seg_info (now_seg)->tc_segment_info_data.maps= tate; - if (!need_pass_2 && ((subseg_text_p (now_seg) && mapstate =3D=3D MAP_D= ATA) - || !subseg_text_p (now_seg))) - frag_align_code (2, 0); - mapping_state (MAP_INSN); =20 inst_base =3D &inst.base; --------------020705010302030506010702--