From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 52680 invoked by alias); 24 Apr 2015 16:24:51 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 52665 invoked by uid 89); 24 Apr 2015 16:24:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.1 required=5.0 tests=AWL,BAYES_40,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 24 Apr 2015 16:24:48 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6B38D29 for ; Fri, 24 Apr 2015 09:24:25 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A5973F21B; Fri, 24 Apr 2015 09:24:45 -0700 (PDT) Message-ID: <553A6E4C.5010603@foss.arm.com> Date: Fri, 24 Apr 2015 16:24:00 -0000 From: Richard Earnshaw User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: binutils@sourceware.org Subject: ARM: Don't tail-pad over-aligned sections Content-Type: multipart/mixed; boundary="------------020106020501080707080204" X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg00388.txt.bz2 This is a multi-part message in MIME format. --------------020106020501080707080204 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: 8bit Content-length: 4525 Some recent hand-written assembler files have started to make use of functions that are aligned to cache line boundaries. This has highlighted an issue with gas where the section containing the over-aligned function is then tail-padded at the end to the level of the over-alignment, even though the following section has a less strict alignment. GAS for ARM currently tail-pads sections out to the natural alignment of the section. If the section contains over-alignment to permit alignment of branches, this causes the section to be padded out to that alignment as well, so even if the code following has minimal alignment constraints the space is still padded out with NOPs. This patch changes that behaviour as follows: 1) non-code sections are not padded out at all - this appears to be the normal behaviour in gas if HANDLE_ALIGN is not defined 2) Code sections are padded out to the lower of the natural alignment of the section and 4 bytes. This permits thumb1 sections with no alignment limits to retain their unpadded behaviour, while maintining existing padding behaviour for traditional thumb code that has 4-byte alignment. Note that the linker will pad code sections with 0 rather than NOPs, so code that drops through from one linker section to another might silently change behaviour after this change if it really does rely on code padding. The desire to try to keep thumb padding to 4-byte boundaries is due to the worry that this change might otherwise break concatenation of code sequences to form a larger whole. While this is probably undefined in practice, this change should allow for maximum backwards compatibility while still achieving the overall desire of not overly padding objects. It's still possible to forcibly pad out a section to a particuar alignment by putting an explicit alignment directive at the end of the section. This change causes a degree of disruption in the testsuite. I think all the changes are benign, but one change is worthy of note. The armthumb-lib test for v4t no-longer has a 16-byte aligned entry point. The reason for this is that the entry point is a veneer, not the address of the function itself. In the past it was just a co-incidence that this address was also 16-byte aligned but the test seems to have been written on the assumption that it was required. I can think of no reason why that should be the case (and indeed, I can think of a very good one why it shouldn't - if multiple functions had this behaviour, then a shared library would end up with very sparse entry veneers wasting lots of space). Furthermore, taking the address of a function in a shared library isn't gauranteed to return the actual address of the function itself, just the address of an entry point for it, which might even be a PLT slot in another DSO or the main image itself - so there is no way that applications can usefully rely on this aligned nature. The other testsuite issues have mostly been fixed by skipping over the unspecified padding elements. Regression tested on arm-eabi and pushed to trunk. R. [ARM]: Don't tail-pad over-aligned functions to the alignment boundary. 2015-04/24 Richard Earnshaw gas/ * config/tc-arm.h (arm_min): New function. (SUB_SEGMENT_ALIGN): Define. gas/testsuite/ * gas/arm/align64.d: Delete trailing padding NOPs. ld/testsuite/ * ld-arm/armthumb-lib.d: Regenerate expected output. * ld-arm/armthumb-lib.d: Likewise. * ld-arm/armthumb-lib.sym: Likewise. * ld-arm/cortex-a8-fix-b-rel-arm.d: Likewise. * ld-arm/cortex-a8-fix-b-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-b.d: Likewise. * ld-arm/cortex-a8-fix-bcc-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-bcc.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-arm.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-plt.d: Likewise. * ld-arm/cortex-a8-fix-bl-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-bl.d: Likewise. * ld-arm/cortex-a8-fix-blx-bcond.d: Likewise. * ld-arm/cortex-a8-fix-blx-rel-arm.d: Likewise. * ld-arm/cortex-a8-fix-blx-rel-thumb.d: Likewise. * ld-arm/cortex-a8-fix-blx.d: Likewise. * ld-arm/cortex-a8-fix-hdr.d: Likewise. * ld-arm/farcall-mixed-app-v5.d: Likewise. * ld-arm/farcall-mixed-app.d: Likewise. * ld-arm/farcall-mixed-lib-v4t.d: Likewise. * ld-arm/farcall-mixed-lib.d: Likewise. * ld-arm/mixed-app-v5.d: Likewise. * ld-arm/mixed-app.d: Likewise. * ld-arm/mixed-lib.d: Likewise. --------------020106020501080707080204 Content-Type: text/plain; charset=UTF-8; name="tailpad-arm.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="tailpad-arm.patch" Content-length: 22378 diff --git a/gas/config/tc-arm.h b/gas/config/tc-arm.h index b604f04..2216267 100644 --- a/gas/config/tc-arm.h +++ b/gas/config/tc-arm.h @@ -236,10 +236,19 @@ struct arm_frag_type #endif }; =20 +static inline int +arm_min (int am_p1, int am_p2) +{ + return am_p1 < am_p2 ? am_p1 : am_p2; +} + #define TC_FRAG_TYPE struct arm_frag_type /* NOTE: max_chars is a local variable from frag_var / frag_variant. */ #define TC_FRAG_INIT(fragp) arm_init_frag (fragp, max_chars) #define HANDLE_ALIGN(fragp) arm_handle_align (fragp) +#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) \ + ((!(FRCHAIN)->frch_next && subseg_text_p (SEG)) \ + ? arm_min (2, get_recorded_alignment (SEG)) : 0) =20 #define md_do_align(N, FILL, LEN, MAX, LABEL) \ if (FILL =3D=3D NULL && (N) !=3D 0 && ! need_pass_2 && subseg_text_p (no= w_seg)) \ diff --git a/gas/testsuite/gas/arm/align64.d b/gas/testsuite/gas/arm/align6= 4.d index cee7442..ee67c82 100644 --- a/gas/testsuite/gas/arm/align64.d +++ b/gas/testsuite/gas/arm/align64.d @@ -52,18 +52,3 @@ Disassembly of section .text: 00000078 e1a00000.*nop.* 0000007c e1a00000.*nop.* 00000080 e3a00004.*mov.*r0, #4 -00000084 e1a00000.*nop.* -00000088 e1a00000.*nop.* -0000008c e1a00000.*nop.* -00000090 e1a00000.*nop.* -00000094 e1a00000.*nop.* -00000098 e1a00000.*nop.* -0000009c e1a00000.*nop.* -000000a0 e1a00000.*nop.* -000000a4 e1a00000.*nop.* -000000a8 e1a00000.*nop.* -000000ac e1a00000.*nop.* -000000b0 e1a00000.*nop.* -000000b4 e1a00000.*nop.* -000000b8 e1a00000.*nop.* -000000bc e1a00000.*nop.* diff --git a/gdb/python/py-value.c b/gdb/python/py-value.c index 6622d11..b79fbb5 100644 --- a/ld/testsuite/ld-arm/armthumb-lib.d +++ b/ld/testsuite/ld-arm/armthumb-lib.d @@ -31,15 +31,9 @@ Disassembly of section .text: .* <__real_lib_func2>: .*: 4770 bx lr .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) =20 .* : .*: e59fc004 ldr ip, \[pc, #4\] ; .* .*: e08cc00f add ip, ip, pc .*: e12fff1c bx ip - .*: ffffffe5 .* + .*: fffffff1 .* diff --git a/ld/testsuite/ld-arm/armthumb-lib.sym b/ld/testsuite/ld-arm/arm= thumb-lib.sym index f1358e2..3714e80 100644 --- a/ld/testsuite/ld-arm/armthumb-lib.sym +++ b/ld/testsuite/ld-arm/armthumb-lib.sym @@ -11,5 +11,5 @@ Symbol table for image: +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +9 __end__ +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +9 __bss_start +.. +..: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND app_func2 - +.. +..: .......0 +2 +FUNC +GLOBAL +DEFAULT +6 lib_func2 + +.. +..: .......[048c] +2 +FUNC +GLOBAL +DEFAULT +6 lib_func2 +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +9 _bss_end__ diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d b/ld/testsuite/l= d-arm/cortex-a8-fix-b-rel-arm.d index 195a51b..3e52a49 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d @@ -6,7 +6,7 @@ Disassembly of section \.text: =20 00008f00 : 8f00: e12fff1e bx lr - 8f04: e320f000 nop \{0\} +#... =20 00008f08 <_start>: 8f08: bf00 nop @@ -75,7 +75,7 @@ Disassembly of section \.text: 9002: eb01 0002 add\.w r0, r1, r2 9006: f000 b803 b\.w 9010 <__targetfn_from_thumb> 900a: 4770 bx lr - 900c: f3af 8000 nop\.w +#... =20 00009010 <__targetfn_from_thumb>: 9010: 4778 bx pc diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d b/ld/testsuite= /ld-arm/cortex-a8-fix-b-rel-thumb.d index 60a254b..6660c75 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d @@ -6,8 +6,7 @@ Disassembly of section \.text: =20 00008f00 : 8f00: 4770 bx lr - 8f02: bf00 nop - 8f04: f3af 8000 nop\.w +#... =20 00008f08 <_start>: 8f08: bf00 nop @@ -76,5 +75,5 @@ Disassembly of section \.text: 9002: eb01 0002 add\.w r0, r1, r2 9006: f7ff bf7b b\.w 8f00 900a: 4770 bx lr - 900c: f3af 8000 nop\.w +#... 9010: f7ff bf76 b\.w 8f00 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b.d b/ld/testsuite/ld-arm/co= rtex-a8-fix-b.d index b2d4481..580e696 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-b.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-b.d @@ -71,5 +71,5 @@ Disassembly of section \.text: 8ffa: eb01 0002 add\.w r0, r1, r2 8ffe: f000 b803 b\.w 9008 <_start\+0x108> 9002: 4770 bx lr - 9004: f3af 8000 nop\.w +#... 9008: f7ff bfeb b\.w 8fe2 <_start\+0xe2> diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d b/ld/testsui= te/ld-arm/cortex-a8-fix-bcc-rel-thumb.d index 27a7fd4..ee8b99f 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d @@ -6,8 +6,7 @@ Disassembly of section \.text: =20 00008f00 : 8f00: 4770 bx lr - 8f02: bf00 nop - 8f04: f3af 8000 nop\.w +#... =20 00008f08 <_start>: 8f08: bf00 nop @@ -76,7 +75,7 @@ Disassembly of section \.text: 9002: eb01 0002 add\.w r0, r1, r2 9006: f53f af7b bmi\.w 8f00 900a: 4770 bx lr - 900c: f3af 8000 nop\.w +#... 9010: d401 bmi\.n 9016 <_start\+0x10e> 9012: f7ff bff6 b\.w 9002 <_start\+0xfa> 9016: f7ff bf73 b\.w 8f00 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d b/ld/testsuite/ld-arm/= cortex-a8-fix-bcc.d index 44b8110..a8b8e10 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d @@ -71,7 +71,7 @@ Disassembly of section \.text: 8ffa: eb01 0002 add\.w r0, r1, r2 8ffe: f000 b803 b\.w 9008 <_start\+0x108> 9002: 4770 bx lr - 9004: f3af 8000 nop\.w +#... 9008: d301 bcc\.n 900e <_start\+0x10e> 900a: f7ff bffa b\.w 9002 <_start\+0x102> 900e: f7ff bfe8 b\.w 8fe2 <_start\+0xe2> diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d b/ld/testsuite/= ld-arm/cortex-a8-fix-bl-rel-arm.d index fcb3bab..9385990 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d @@ -6,7 +6,7 @@ Disassembly of section \.text: =20 00008f00 : 8f00: e12fff1e bx lr - 8f04: e320f000 nop \{0\} +#... =20 00008f08 <_start>: 8f08: bf00 nop @@ -75,5 +75,5 @@ Disassembly of section \.text: 9002: eb01 0002 add\.w r0, r1, r2 9006: f7ff ef7c blx 8f00 900a: 4770 bx lr - 900c: f3af 8000 nop\.w +#... 9010: eaffffba b 8f00 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d b/ld/testsuite/= ld-arm/cortex-a8-fix-bl-rel-plt.d index ba1f537..c504f79 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d @@ -20,7 +20,7 @@ Disassembly of section \.text: 00008f00 : 8f00: 4770 bx lr 8f02: bf00 nop - 8f04: f3af 8000 nop\.w +#... =20 00008f08 <_start>: 8f08: bf00 nop @@ -89,5 +89,5 @@ Disassembly of section \.text: 9002: eb01 0002 add\.w r0, r1, r2 9006: f7ff ef06 blx 8e14 900a: 4770 bx lr - 900c: f3af 8000 nop\.w +#... 9010: eaffff7f b 8e14 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d b/ld/testsuit= e/ld-arm/cortex-a8-fix-bl-rel-thumb.d index 8cbd3e0..6c97df9 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d @@ -6,8 +6,7 @@ Disassembly of section \.text: =20 00008f00 : 8f00: 4770 bx lr - 8f02: bf00 nop - 8f04: f3af 8000 nop\.w +#... =20 00008f08 <_start>: 8f08: bf00 nop @@ -76,5 +75,5 @@ Disassembly of section \.text: 9002: eb01 0002 add\.w r0, r1, r2 9006: f7ff ff7b bl 8f00 900a: 4770 bx lr - 900c: f3af 8000 nop\.w +#... 9010: f7ff bf76 b\.w 8f00 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl.d b/ld/testsuite/ld-arm/c= ortex-a8-fix-bl.d index 50dcd4f..528a8d3 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-bl.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl.d @@ -71,5 +71,5 @@ Disassembly of section \.text: 8ffa: eb01 0002 add\.w r0, r1, r2 8ffe: f000 f803 bl 9008 <_start\+0x108> 9002: 4770 bx lr - 9004: f3af 8000 nop\.w +#... 9008: f7ff bfeb b\.w 8fe2 <_start\+0xe2> diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d b/ld/testsuite/l= d-arm/cortex-a8-fix-blx-bcond.d index 692a606..9157b83 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d @@ -1100,7 +1100,7 @@ Disassembly of section \.text: 9ffa: eb01 0002 add\.w r0, r1, r2 9ffe: f000 e804 blx a008 a002: 4770 bx lr - a004: f3af 8000 nop\.w +#... a008: eaffffba b 9ef8 a00c: d101 bne\.n a012 a00e: f7fe bff8 b\.w 9002 <_start\+0x102> diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d b/ld/testsuite= /ld-arm/cortex-a8-fix-blx-rel-arm.d index fcb3bab..9385990 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d @@ -6,7 +6,7 @@ Disassembly of section \.text: =20 00008f00 : 8f00: e12fff1e bx lr - 8f04: e320f000 nop \{0\} +#... =20 00008f08 <_start>: 8f08: bf00 nop @@ -75,5 +75,5 @@ Disassembly of section \.text: 9002: eb01 0002 add\.w r0, r1, r2 9006: f7ff ef7c blx 8f00 900a: 4770 bx lr - 900c: f3af 8000 nop\.w +#... 9010: eaffffba b 8f00 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d b/ld/testsui= te/ld-arm/cortex-a8-fix-blx-rel-thumb.d index 8cbd3e0..6c97df9 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d @@ -6,8 +6,7 @@ Disassembly of section \.text: =20 00008f00 : 8f00: 4770 bx lr - 8f02: bf00 nop - 8f04: f3af 8000 nop\.w +#... =20 00008f08 <_start>: 8f08: bf00 nop @@ -76,5 +75,5 @@ Disassembly of section \.text: 9002: eb01 0002 add\.w r0, r1, r2 9006: f7ff ff7b bl 8f00 900a: 4770 bx lr - 900c: f3af 8000 nop\.w +#... 9010: f7ff bf76 b\.w 8f00 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx.d b/ld/testsuite/ld-arm/= cortex-a8-fix-blx.d index 4805256..788e0a3 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-blx.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx.d @@ -75,5 +75,5 @@ Disassembly of section \.text: 9002: eb01 0002 add\.w r0, r1, r2 9006: f7ff ef7c blx 8f00 900a: 4770 bx lr - 900c: f3af 8000 nop\.w +#... 9010: eaffffba b 8f00 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-hdr.d b/ld/testsuite/ld-arm/= cortex-a8-fix-hdr.d index 027d2a1..9d4c3de 100644 --- a/ld/testsuite/ld-arm/cortex-a8-fix-hdr.d +++ b/ld/testsuite/ld-arm/cortex-a8-fix-hdr.d @@ -19,6 +19,6 @@ Disassembly of section \.text: ff6: bf00 nop ff8: bf00 nop ffa: ea81 0002 eor.w r0, r1, r2 - ffe: f000 b80f b.w 1020 <_start\+0x40> + ffe: f000 b803 b.w 1008 <_start\+0x28> #... - 1020: f7ff bfde b.w fe0 <_start> + 1008: f7ff bf.. b.w fe0 <_start> diff --git a/ld/testsuite/ld-arm/farcall-mixed-app-v5.d b/ld/testsuite/ld-a= rm/farcall-mixed-app-v5.d index 7466883..ea0e823 100644 --- a/ld/testsuite/ld-arm/farcall-mixed-app-v5.d +++ b/ld/testsuite/ld-arm/farcall-mixed-app-v5.d @@ -39,8 +39,7 @@ Disassembly of section .text: .*: bd00 pop {pc} .*: 4770 bx lr .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) +#... =20 .* <__app_func_veneer>: .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__app_func_veneer\+0x4> @@ -51,8 +50,8 @@ Disassembly of section .far_arm: .* : .*: e1a0c00d mov ip, sp .*: e92dd800 push {fp, ip, lr, pc} - .*: eb000008 bl .* <__lib_func1_veneer> - .*: eb000009 bl .* <__lib_func2_veneer> + .*: eb0000.. bl .* <__lib_func1_veneer> + .*: eb0000.. bl .* <__lib_func2_veneer> .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .*: e1a00000 nop ; \(mov r0, r0\) @@ -60,15 +59,13 @@ Disassembly of section .far_arm: =20 .* : .*: e12fff1e bx lr - .*: e1a00000 nop ; \(mov r0, r0\) - .*: e1a00000 nop ; \(mov r0, r0\) - .*: e1a00000 nop ; \(mov r0, r0\) +#... =20 .* <__lib_func1_veneer>: - .*: e51ff004 ldr pc, \[pc, #-4\] ; 2100034 <__lib_func1_veneer\+0x4> + .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func1_veneer\+0x4> .*: 000081e8 .word 0x000081e8 .* <__lib_func2_veneer>: - .*: e51ff004 ldr pc, \[pc, #-4\] ; 210003c <__lib_func2_veneer\+0x4> + .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func2_veneer\+0x4> .*: 000081dc .word 0x000081dc =20 Disassembly of section .far_thumb: @@ -79,8 +76,7 @@ Disassembly of section .far_thumb: .*: bd00 pop {pc} .*: 4770 bx lr .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) +#... =20 .* <__lib_func2_from_thumb>: .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200014 <__lib_func2_from_thumb\+0x4> diff --git a/ld/testsuite/ld-arm/farcall-mixed-app.d b/ld/testsuite/ld-arm/= farcall-mixed-app.d index 6fa799d..86127ef 100644 --- a/ld/testsuite/ld-arm/farcall-mixed-app.d +++ b/ld/testsuite/ld-arm/farcall-mixed-app.d @@ -41,8 +41,7 @@ Disassembly of section .text: .*: bd00 pop {pc} .*: 4770 bx lr .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) +#... =20 .* <__app_func_veneer>: .*: e51ff004 ldr pc, \[pc, #-4\] ; 8234 <__app_func_veneer\+0x4> @@ -53,8 +52,8 @@ Disassembly of section .far_arm: .* : .*: e1a0c00d mov ip, sp .*: e92dd800 push {fp, ip, lr, pc} - .*: eb000008 bl .* <__lib_func1_veneer> - .*: eb000009 bl .* <__lib_func2_veneer> + .*: eb000006 bl .* <__lib_func1_veneer> + .*: eb000007 bl .* <__lib_func2_veneer> .*: e89d6800 ldm sp, {fp, sp, lr} .*: e12fff1e bx lr .*: e1a00000 nop ; \(mov r0, r0\) @@ -62,15 +61,13 @@ Disassembly of section .far_arm: =20 .* : .*: e12fff1e bx lr - .*: e1a00000 nop ; \(mov r0, r0\) - .*: e1a00000 nop ; \(mov r0, r0\) - .*: e1a00000 nop ; \(mov r0, r0\) +#... =20 .* <__lib_func1_veneer>: - .*: e51ff004 ldr pc, \[pc, #-4\] ; 2100034 <__lib_func1_veneer\+0x4> + .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func1_veneer\+0x4> .*: 000081ec .word 0x000081ec .* <__lib_func2_veneer>: - .*: e51ff004 ldr pc, \[pc, #-4\] ; 210003c <__lib_func2_veneer\+0x4> + .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__lib_func2_veneer\+0x4> .*: 000081e0 .word 0x000081e0 =20 Disassembly of section .far_thumb: @@ -81,8 +78,7 @@ Disassembly of section .far_thumb: .*: bd00 pop {pc} .*: 4770 bx lr .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) +#... =20 .* <__lib_func2_from_thumb>: .*: 4778 bx pc diff --git a/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d b/ld/testsuite/ld-= arm/farcall-mixed-lib-v4t.d index 54f4fab..e2dbc1b 100644 --- a/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d +++ b/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d @@ -50,55 +50,47 @@ Disassembly of section .text: ... =20 .* <__real_lib_func2>: - .*: f000 f80e bl 1000330 <__app_func_from_thumb> - .*: f000 f81c bl 1000350 <__app_func_weak_from_thumb> - .*: f000 f822 bl 1000360 <__lib_func3_from_thumb> - .*: f000 f810 bl 1000340 <__lib_func4_from_thumb> + .*: f000 f8.. bl .* <__app_func_from_thumb> + .*: f000 f8.. bl .* <__app_func_weak_from_thumb> + .*: f000 f8.. bl .* <__lib_func3_from_thumb> + .*: f000 f8.. bl .* <__lib_func4_from_thumb> .*: 4770 bx lr - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) +#... =20 .* <__app_func_from_thumb>: .*: 4778 bx pc .*: 46c0 nop ; \(mov r8, r8\) - .*: e59fc000 ldr ip, \[pc\] ; 100033c <__app_func_from_thumb\+0xc> + .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0xc> .*: e08cf00f add pc, ip, pc - .*: feffff68 .word 0xfeffff68 + .*: feffff.. .word 0xfeffff.. =20 .* <__lib_func4_from_thumb>: .*: 4778 bx pc .*: 46c0 nop ; \(mov r8, r8\) - .*: e59fc000 ldr ip, \[pc\] ; 100034c <__lib_func4_from_thumb\+0xc> + .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func4_from_thumb\+0xc> .*: e08cf00f add pc, ip, pc - .*: feffff88 .word 0xfeffff88 + .*: feffff.. .word 0xfeffff.. =20 .* <__app_func_weak_from_thumb>: .*: 4778 bx pc .*: 46c0 nop ; \(mov r8, r8\) - .*: e59fc000 ldr ip, \[pc\] ; 100035c <__app_func_weak_from_thumb\+0xc> + .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0xc> .*: e08cf00f add pc, ip, pc - .*: feffff58 .word 0xfeffff58 + .*: feffff.. .word 0xfeffff.. =20 .* <__lib_func3_from_thumb>: .*: 4778 bx pc .*: 46c0 nop ; \(mov r8, r8\) - .*: e59fc000 ldr ip, \[pc\] ; 100036c <__lib_func3_from_thumb\+0xc> + .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func3_from_thumb\+0xc> .*: e08cf00f add pc, ip, pc - .*: feffff58 .word 0xfeffff58 + .*: feffff.. .word 0xfeffff.. ... =20 .* <__real_lib_func3>: .*: f000 f80e bl 2000390 <__app_func_from_thumb> .*: f000 f804 bl 2000380 <__app_func_weak_from_thumb> .*: 4770 bx lr - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) +#... =20 .* <__app_func_weak_from_thumb>: .*: 4778 bx pc diff --git a/ld/testsuite/ld-arm/farcall-mixed-lib.d b/ld/testsuite/ld-arm/= farcall-mixed-lib.d index 8524e90..b736983 100644 --- a/ld/testsuite/ld-arm/farcall-mixed-lib.d +++ b/ld/testsuite/ld-arm/farcall-mixed-lib.d @@ -42,47 +42,40 @@ Disassembly of section .text: ... =20 .* : - .*: f000 e820 blx 1000344 <__app_func_from_thumb> - .*: f000 e812 blx 100032c <__app_func_weak_from_thumb> - .*: f000 e80a blx 1000320 <__lib_func3_from_thumb> - .*: f000 e814 blx 1000338 <__lib_func4_from_thumb> + .*: f000 e8.. blx .* <__app_func_from_thumb> + .*: f000 e8.. blx .* <__app_func_weak_from_thumb> + .*: f000 e8.. blx .* <__lib_func3_from_thumb> + .*: f000 e8.. blx .* <__lib_func4_from_thumb> .*: 4770 bx lr - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop.* +#... =20 .* <__lib_func3_from_thumb>: - .*: e59fc000 ldr ip, \[pc\] ; 1000328 <__lib_func3_from_thumb\+0x8> + .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func3_from_thumb\+0x8> .*: e08ff00c add pc, pc, ip - .*: feffff90 .word 0xfeffff90 + .*: feffff.. .word 0xfeffff.. =20 .* <__app_func_weak_from_thumb>: - .*: e59fc000 ldr ip, \[pc\] ; 1000334 <__app_func_weak_from_thumb\+0x8> + .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_weak_from_thumb\+0x8> .*: e08ff00c add pc, pc, ip - .*: feffff78 .word 0xfeffff78 + .*: feffff.. .word 0xfeffff.. =20 .* <__lib_func4_from_thumb>: - .*: e59fc000 ldr ip, \[pc\] ; 1000340 <__lib_func4_from_thumb\+0x8> + .*: e59fc000 ldr ip, \[pc\] ; .* <__lib_func4_from_thumb\+0x8> .*: e08ff00c add pc, pc, ip - .*: feffff84 .word 0xfeffff84 + .*: feffff.. .word 0xfeffff.. =20 .* <__app_func_from_thumb>: - .*: e59fc000 ldr ip, \[pc\] ; 100034c <__app_func_from_thumb\+0x8> + .*: e59fc000 ldr ip, \[pc\] ; .* <__app_func_from_thumb\+0x8> .*: e08ff00c add pc, pc, ip - .*: feffff54 .word 0xfeffff54 + .*: feffff.. .word 0xfeffff.. ... =20 .* : .*: f000 e80c blx 200037c <__app_func_from_thumb> .*: f000 e804 blx 2000370 <__app_func_weak_from_thumb> .*: 4770 bx lr - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) +#... =20 .* <__app_func_weak_from_thumb>: .*: e59fc000 ldr ip, \[pc\] ; 2000378 <__app_func_weak_from_thumb\+0x8> diff --git a/ld/testsuite/ld-arm/mixed-app-v5.d b/ld/testsuite/ld-arm/mixed= -app-v5.d index 1091a80..0ad39e6 100644 --- a/ld/testsuite/ld-arm/mixed-app-v5.d +++ b/ld/testsuite/ld-arm/mixed-app-v5.d @@ -53,6 +53,4 @@ Disassembly of section .text: .*: f7ff efc. blx .* .*: bd00 pop {pc} .*: 4770 bx lr - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) +#... diff --git a/ld/testsuite/ld-arm/mixed-app.d b/ld/testsuite/ld-arm/mixed-ap= p.d index 5fdd9f4..6083161 100644 --- a/ld/testsuite/ld-arm/mixed-app.d +++ b/ld/testsuite/ld-arm/mixed-app.d @@ -55,6 +55,4 @@ Disassembly of section .text: .*: f7ff ffc. bl .* .*: bd00 pop {pc} .*: 4770 bx lr - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) +#... diff --git a/ld/testsuite/ld-arm/mixed-lib.d b/ld/testsuite/ld-arm/mixed-li= b.d index 29d29e9..271692c 100644 --- a/ld/testsuite/ld-arm/mixed-lib.d +++ b/ld/testsuite/ld-arm/mixed-lib.d @@ -30,10 +30,4 @@ Disassembly of section .text: =20 .* : .*: 4770 bx lr - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) - .*: 46c0 nop ; \(mov r8, r8\) +#... --------------020106020501080707080204--