From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 78142 invoked by alias); 6 May 2015 07:44:40 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 78131 invoked by uid 89); 6 May 2015 07:44:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail.emea.novell.com Received: from mail.emea.novell.com (HELO mail.emea.novell.com) (130.57.118.101) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 06 May 2015 07:44:38 +0000 Received: from EMEA1-MTA by mail.emea.novell.com with Novell_GroupWise; Wed, 06 May 2015 08:44:35 +0100 Message-Id: <5549E2820200007800076F5F@mail.emea.novell.com> Date: Wed, 06 May 2015 07:44:00 -0000 From: "Jan Beulich" To: "H.J. Lu" Cc: "Kirill Yukhin" , "Binutils" ,"H. Peter Anvin" Subject: Re: [PATCH] x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} References: <552FE0630200007800072CD0@mail.emea.novell.com> <55390A6A0200007800075263@mail.emea.novell.com> <554906C70200007800076D28@mail.emea.novell.com> In-Reply-To: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-SW-Source: 2015-05/txt/msg00031.txt.bz2 >>> On 05.05.15 at 18:10, wrote: > On Tue, May 5, 2015 at 9:07 AM, Jan Beulich wrote: >>>>> On 23.04.15 at 15:17, wrote: >>> On Thu, Apr 23, 2015 at 6:06 AM, Jan Beulich wrote: >>>>>>> On 23.04.15 at 14:39, wrote: >>>>> It is not OK. >>>> >>>> ... I guess as the Intel syntax maintainer I could decide to ignore >>>> this. >>> >>> MASM AVX512 compatibility isn't our goal. Compatible with NASM is >>> a good ideal. Peter, Kirill, let's work it out. >>> >>> Adding Peter for NASM and Kirill for GAS. >> >> Not having seen any response from them at all, I think applying >> at least the assembler side (which leaves the current bogus >> operand order available) should really not be controversial. As >> to the disassembler side, I continue to think that Intel syntax >> disassembly should preferably match the Intel manual, especially >> when there is no other implementation to use as reference. >> >> Thoughts? >> >=20 > Since there is no MASM AVX512 compatibility to speak of, > please don't apply those patches Please don't just repeat yourself, but give a reason I can understand to override the intention to conform with the Intel manual. I'm certainly hesitant to commit changes that can't be agreed upon, but as said before I don't feel tied to your disapproval of the changes. Jan