From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 59645 invoked by alias); 12 May 2015 14:59:54 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 59549 invoked by uid 89); 12 May 2015 14:59:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail.emea.novell.com Received: from mail.emea.novell.com (HELO mail.emea.novell.com) (130.57.118.101) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 May 2015 14:59:52 +0000 Received: from EMEA1-MTA by mail.emea.novell.com with Novell_GroupWise; Tue, 12 May 2015 15:59:49 +0100 Message-Id: <5552318402000078000798A8@mail.emea.novell.com> Date: Tue, 12 May 2015 14:59:00 -0000 From: "Jan Beulich" To: "H.J. Lu" Cc: "Binutils" Subject: Re: [committed, PATCH] Remove Disp16|Disp32 from 64-bit direct branches References: <20150511212331.GA1838@intel.com> <5551F4E70200007800079575@mail.emea.novell.com> <55520C440200007800079718@mail.emea.novell.com> <555216370200007800079773@mail.emea.novell.com> In-Reply-To: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-SW-Source: 2015-05/txt/msg00089.txt.bz2 >>> On 12.05.15 at 15:37, wrote: > On Tue, May 12, 2015 at 6:03 AM, Jan Beulich wrote: >>>>> On 12.05.15 at 14:37, wrote: >>> On Tue, May 12, 2015 at 5:20 AM, Jan Beulich wrote: >>>>>>> On 12.05.15 at 13:54, wrote: >>>>> On Tue, May 12, 2015 at 3:41 AM, Jan Beulich wrot= e: >>>>>>>>> On 11.05.15 at 23:23, wrote: >>>>>>> Disp16 and Disp32 aren't supported by direct branches in 64-bit mod= e. >>>>>>> This patch removes them from 64-bit direct branches. >>>>>> >>>>>> See the recent discussion regarding callw - these can certainly have >>>>>> 16-bit displacements on AMD CPUs. And while disassembly may just >>>>>> get "disturbed" by getting this wrong, assembly will produce bad >>>>>> code if you don't account for both cases (or refuse to assemble >>>>>> such mnemonics if they would require size overrides to be added). >>>>>> >>>>>> Apart from that I wonder why you do this for CALL and JMP, but not >>>>>> for Jcc, JCXZ, JRCXZ, LOOP, and LOOPcc. >>>>>> >>>>>> But first of all - please don't bias x86 binutils towards only suppo= rting >>>>>> Intel hardware. >>>>> >>>>> Can you generate call/jmp with 16-bit displacement in 64-bit mode? >>>> >>>> Didn't check whether there is a mechanism currently; of course I >>>> would expect "data16 jmp