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Date: Mon, 18 May 2015 11:48:00 -0000
From: "Jan Beulich" <JBeulich@suse.com>
To: "H.J. Lu" <hjl.tools@gmail.com>
Cc: "Maciej W. Rozycki" <macro@linux-mips.org>, "Binutils" <binutils@sourceware.org>,"Michael Matz" <matz@suse.de>
Subject: Re: [committed, PATCH] Remove Disp16|Disp32 from 64-bit direct branches
References: <20150511212331.GA1838@intel.com> <55520C440200007800079718@mail.emea.novell.com> <CAMe9rOpOx=SSUZnCFimn4fBzFqNRDch8QYLn3Os_y7EfQH65Qw@mail.gmail.com> <5552318402000078000798A8@mail.emea.novell.com> <CAMe9rOoqcr7aE8dr6E44KUK6JLrNMNcDNFFWhcb6K+14M=Y+=w@mail.gmail.com> <555233B602000078000798EF@mail.emea.novell.com> <CAMe9rOrOS+K0R+r1jHCNwAkgrhjftHUOGt_wTuP8wRYcPdifmQ@mail.gmail.com> <555235930200007800079911@mail.emea.novell.com> <alpine.LSU.2.20.1505121736050.4883@wotan.suse.de> <CAMe9rOo76QirYvEH=tX7BDBws3z=g0O8c+A1wSp+19yaNXUk1w@mail.gmail.com> <alpine.LSU.2.20.1505121745550.27315@wotan.suse.de> <CAMe9rOqM+cojMqoz9Kwb_KedgZG-14_xFaV2mk=hNEQGUkDWVw@mail.gmail.com> <alpine.LSU.2.20.1505121803030.27315@wotan.suse.de> <CAMe9rOqECoP=-Bz4neR1LnFsnPO94axMuSpEiOzjmJzbNgA_kA@mail.gmail.com> <alpine.LSU.2.20.1505131430230.27315@wotan.suse.de> <CAMe9rOrjt5e8qqOqqCOsuDfhtVSb2atwiqoF5HN_3aSBzsOgyQ@mail.gmail.com> <alpine.LFD.2.11.1505131738000.1538@eddie.linux-mips.org> <CAMe9rOo-K21Gs9prT6Tb4nX80VRi2bA26mGonnr7=vt8W1NFKA@mail.gmail.com> <5555B0C2020000780007A5FB@mail.emea.novell.com> <CAMe9rOpq4TVpb_jVZU-sVpOkupm-gJQjYg8QnFTNkjYRYpBZdQ@mail.gmail.com> <5559AB3F020000780007AE54@mail.emea.novell.com> <CAMe9rOoWCn0xMZ5+n1MKDGdpXjqk9G0XUh1fp-HBaRE2Vn7kkg@mail.gmail.com>
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>>> On 18.05.15 at 13:22, <hjl.tools@gmail.com> wrote:
> On Mon, May 18, 2015 at 12:05 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 15.05.15 at 18:52, <hjl.tools@gmail.com> wrote:
>>> * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
>>> Mark direct call/jmp without Disp16|Disp32 as Intel64.
>>
>> I had hoped that you wouldn't add back Disp32 to the AMD case, and
>=20
> This is what I checked in.

Thanks!

>> perhaps also that CpuAMD64 and CpuIntel64 would imply Cpu64 (as
>> their names already suggest).
>=20
> They are just a bit.  Make them to implement Cpu64 means adding more
> codes to x86 assembler without any benefit.  If you can share with me
> what you have in mind, I will see what I can do.

Ah, no, I didn't mean the assembler to do more work. Instead I
thought that the generator utility could set Cpu64 alongside either
of the new ones, thus keeping the opcode table slightly better
readable.

Jan