* [PATCH 1/2][Aarch64][binutils] Add support for ARMv8.1a Adv.SIMD instructions.
@ 2015-05-20 14:52 Matthew Wahab
2015-05-20 14:55 ` [PATCH 2/2][Aarch64][gas] " Matthew Wahab
2015-05-29 14:59 ` [PATCH 1/2][Aarch64][binutils] " Nicholas Clifton
0 siblings, 2 replies; 4+ messages in thread
From: Matthew Wahab @ 2015-05-20 14:52 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 707 bytes --]
ARMv8.1a adds two instructions, SQRDMLAH and SQRDMLSH, to the Aarch64 SIMD
instruction set. This patch adds support to binutils for these instructions, with
a following patch to add support in gas.
Tested aarch64-none-linux-gnu with check-gas and check-binutils.
Ok for trunk?
Matthew
include/
2015-05-20 Matthew Wahab <matthew.wahab@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_RDMA): New.
opcodes/
2015-05-20 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-tbl.h (aarch64_feature_rdma): New.
(RDMA): New.
(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: binutils_rdma.patch --]
[-- Type: text/x-patch; name=binutils_rdma.patch, Size: 4714 bytes --]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 7130d2d..c300d8b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -39,6 +39,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
+#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 228ce35..82715ed 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1222,6 +1222,8 @@ static const aarch64_feature_set aarch64_feature_crc =
AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
static const aarch64_feature_set aarch64_feature_lse =
AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0);
+static const aarch64_feature_set aarch64_feature_rdma =
+ AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -1229,6 +1231,7 @@ static const aarch64_feature_set aarch64_feature_lse =
#define CRYPTO &aarch64_feature_crypto
#define CRC &aarch64_feature_crc
#define LSE &aarch64_feature_lse
+#define RDMA &aarch64_feature_rdma
struct aarch64_opcode aarch64_opcode_table[] =
{
@@ -1358,6 +1361,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
{"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
{"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
+ {"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
+ {"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
/* AdvSIMD EXT. */
{"ext", 0x2e000000, 0xbfe0c400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
/* AdvSIMD modified immediate. */
@@ -1544,6 +1549,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
{"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
{"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
+ /* AdvSIMD three same extension. */
+ {"sqrdmlah", 0x2e008400, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
+ {"sqrdmlsh", 0x2e008c00, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
/* AdvSIMD shift by immediate. */
{"sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
{"ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
@@ -1604,6 +1612,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"fmls", 0x5f805000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
{"fmul", 0x5f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
{"fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
+ {"sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
+ {"sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
/* AdvSIMD load/store multiple structures. */
{"st4", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
{"st1", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
@@ -1726,6 +1736,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
{"sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
{"cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
+ /* AdvSIMDs scalar three same extension. */
+ {"sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
+ {"sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
/* AdvSIMD scalar shift by immediate. */
{"sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
{"ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2][Aarch64][gas] Add support for ARMv8.1a Adv.SIMD instructions.
2015-05-20 14:52 [PATCH 1/2][Aarch64][binutils] Add support for ARMv8.1a Adv.SIMD instructions Matthew Wahab
@ 2015-05-20 14:55 ` Matthew Wahab
2015-05-29 14:59 ` Nicholas Clifton
2015-05-29 14:59 ` [PATCH 1/2][Aarch64][binutils] " Nicholas Clifton
1 sibling, 1 reply; 4+ messages in thread
From: Matthew Wahab @ 2015-05-20 14:55 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 600 bytes --]
ARMv8.1a adds two instructions, SQRDMLAH and SQRDMLSH, to the Aarch64 SIMD
instruction set. This patch adds support to gas for these instructions
under the new architecture extension "rdma".
Tested aarch64-none-linux-gnu with check-gas and check-binutils.
Ok for trunk?
Matthew
gas/
2015-05-20 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "rdma".
* doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".
gas/testsuite/
2015-05-20 Matthew Wahab <matthew.wahab@arm.com>
* rdma-directive.d: New.
* rdma.d: New.
* rdma.s: New.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: gas_rdma.patch --]
[-- Type: text/x-patch; name=gas_rdma.patch, Size: 10027 bytes --]
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ae0e2d6..780d1ef 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7366,6 +7366,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
{"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0)},
{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
+ {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
+ | AARCH64_FEATURE_RDMA, 0)},
{NULL, AARCH64_ARCH_NONE}
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 79fe168..f7fdb52 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -133,6 +133,8 @@ automatically cause those extensions to be disabled.
@tab Enable floating-point extensions.
@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable Advanced SIMD extensions. This implies @code{fp}.
+@item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
@end multitable
@node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/rdma-directive.d b/gas/testsuite/gas/aarch64/rdma-directive.d
new file mode 100644
index 0000000..bd2e818
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rdma-directive.d
@@ -0,0 +1,70 @@
+#objdump: -dr
+#as: --defsym DIRECTIVE=1
+#source: rdma.s
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 2e428420 sqrdmlah v0\.4h, v1\.4h, v2\.4h
+ 4: 6e428420 sqrdmlah v0\.8h, v1\.8h, v2\.8h
+ 8: 2e828420 sqrdmlah v0\.2s, v1\.2s, v2\.2s
+ c: 6e828420 sqrdmlah v0\.4s, v1\.4s, v2\.4s
+ 10: 2e428c20 sqrdmlsh v0\.4h, v1\.4h, v2\.4h
+ 14: 6e428c20 sqrdmlsh v0\.8h, v1\.8h, v2\.8h
+ 18: 2e828c20 sqrdmlsh v0\.2s, v1\.2s, v2\.2s
+ 1c: 6e828c20 sqrdmlsh v0\.4s, v1\.4s, v2\.4s
+ 20: 7e828420 sqrdmlah s0, s1, s2
+ 24: 7e428420 sqrdmlah h0, h1, h2
+ 28: 7e828c20 sqrdmlsh s0, s1, s2
+ 2c: 7e428c20 sqrdmlsh h0, h1, h2
+ 30: 2f42d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[0\]
+ 34: 2f52d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[1\]
+ 38: 2f62d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[2\]
+ 3c: 2f72d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[3\]
+ 40: 6f42d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[0\]
+ 44: 6f52d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[1\]
+ 48: 6f62d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[2\]
+ 4c: 6f72d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[3\]
+ 50: 2f82d020 sqrdmlah v0\.2s, v1\.2s, v2\.s\[0\]
+ 54: 2fa2d020 sqrdmlah v0\.2s, v1\.2s, v2\.s\[1\]
+ 58: 2f82d820 sqrdmlah v0\.2s, v1\.2s, v2\.s\[2\]
+ 5c: 2fa2d820 sqrdmlah v0\.2s, v1\.2s, v2\.s\[3\]
+ 60: 6f82d020 sqrdmlah v0\.4s, v1\.4s, v2\.s\[0\]
+ 64: 6fa2d020 sqrdmlah v0\.4s, v1\.4s, v2\.s\[1\]
+ 68: 6f82d820 sqrdmlah v0\.4s, v1\.4s, v2\.s\[2\]
+ 6c: 6fa2d820 sqrdmlah v0\.4s, v1\.4s, v2\.s\[3\]
+ 70: 2f42f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[0\]
+ 74: 2f52f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[1\]
+ 78: 2f62f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[2\]
+ 7c: 2f72f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[3\]
+ 80: 6f42f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[0\]
+ 84: 6f52f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[1\]
+ 88: 6f62f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[2\]
+ 8c: 6f72f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[3\]
+ 90: 2f82f020 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[0\]
+ 94: 2fa2f020 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[1\]
+ 98: 2f82f820 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[2\]
+ 9c: 2fa2f820 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[3\]
+ a0: 6f82f020 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[0\]
+ a4: 6fa2f020 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[1\]
+ a8: 6f82f820 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[2\]
+ ac: 6fa2f820 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[3\]
+ b0: 7f42d020 sqrdmlah h0, h1, v2\.h\[0\]
+ b4: 7f52d020 sqrdmlah h0, h1, v2\.h\[1\]
+ b8: 7f62d020 sqrdmlah h0, h1, v2\.h\[2\]
+ bc: 7f72d020 sqrdmlah h0, h1, v2\.h\[3\]
+ c0: 7f82d020 sqrdmlah s0, s1, v2\.s\[0\]
+ c4: 7fa2d020 sqrdmlah s0, s1, v2\.s\[1\]
+ c8: 7f82d820 sqrdmlah s0, s1, v2\.s\[2\]
+ cc: 7fa2d820 sqrdmlah s0, s1, v2\.s\[3\]
+ d0: 7f42f020 sqrdmlsh h0, h1, v2\.h\[0\]
+ d4: 7f52f020 sqrdmlsh h0, h1, v2\.h\[1\]
+ d8: 7f62f020 sqrdmlsh h0, h1, v2\.h\[2\]
+ dc: 7f72f020 sqrdmlsh h0, h1, v2\.h\[3\]
+ e0: 7f82f020 sqrdmlsh s0, s1, v2\.s\[0\]
+ e4: 7fa2f020 sqrdmlsh s0, s1, v2\.s\[1\]
+ e8: 7f82f820 sqrdmlsh s0, s1, v2\.s\[2\]
+ ec: 7fa2f820 sqrdmlsh s0, s1, v2\.s\[3\]
diff --git a/gas/testsuite/gas/aarch64/rdma.d b/gas/testsuite/gas/aarch64/rdma.d
new file mode 100644
index 0000000..2ffde68
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rdma.d
@@ -0,0 +1,69 @@
+#objdump: -dr
+#as: -march=armv8-a+rdma
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: 2e428420 sqrdmlah v0\.4h, v1\.4h, v2\.4h
+ 4: 6e428420 sqrdmlah v0\.8h, v1\.8h, v2\.8h
+ 8: 2e828420 sqrdmlah v0\.2s, v1\.2s, v2\.2s
+ c: 6e828420 sqrdmlah v0\.4s, v1\.4s, v2\.4s
+ 10: 2e428c20 sqrdmlsh v0\.4h, v1\.4h, v2\.4h
+ 14: 6e428c20 sqrdmlsh v0\.8h, v1\.8h, v2\.8h
+ 18: 2e828c20 sqrdmlsh v0\.2s, v1\.2s, v2\.2s
+ 1c: 6e828c20 sqrdmlsh v0\.4s, v1\.4s, v2\.4s
+ 20: 7e828420 sqrdmlah s0, s1, s2
+ 24: 7e428420 sqrdmlah h0, h1, h2
+ 28: 7e828c20 sqrdmlsh s0, s1, s2
+ 2c: 7e428c20 sqrdmlsh h0, h1, h2
+ 30: 2f42d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[0\]
+ 34: 2f52d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[1\]
+ 38: 2f62d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[2\]
+ 3c: 2f72d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[3\]
+ 40: 6f42d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[0\]
+ 44: 6f52d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[1\]
+ 48: 6f62d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[2\]
+ 4c: 6f72d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[3\]
+ 50: 2f82d020 sqrdmlah v0\.2s, v1\.2s, v2\.s\[0\]
+ 54: 2fa2d020 sqrdmlah v0\.2s, v1\.2s, v2\.s\[1\]
+ 58: 2f82d820 sqrdmlah v0\.2s, v1\.2s, v2\.s\[2\]
+ 5c: 2fa2d820 sqrdmlah v0\.2s, v1\.2s, v2\.s\[3\]
+ 60: 6f82d020 sqrdmlah v0\.4s, v1\.4s, v2\.s\[0\]
+ 64: 6fa2d020 sqrdmlah v0\.4s, v1\.4s, v2\.s\[1\]
+ 68: 6f82d820 sqrdmlah v0\.4s, v1\.4s, v2\.s\[2\]
+ 6c: 6fa2d820 sqrdmlah v0\.4s, v1\.4s, v2\.s\[3\]
+ 70: 2f42f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[0\]
+ 74: 2f52f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[1\]
+ 78: 2f62f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[2\]
+ 7c: 2f72f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[3\]
+ 80: 6f42f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[0\]
+ 84: 6f52f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[1\]
+ 88: 6f62f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[2\]
+ 8c: 6f72f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[3\]
+ 90: 2f82f020 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[0\]
+ 94: 2fa2f020 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[1\]
+ 98: 2f82f820 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[2\]
+ 9c: 2fa2f820 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[3\]
+ a0: 6f82f020 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[0\]
+ a4: 6fa2f020 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[1\]
+ a8: 6f82f820 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[2\]
+ ac: 6fa2f820 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[3\]
+ b0: 7f42d020 sqrdmlah h0, h1, v2\.h\[0\]
+ b4: 7f52d020 sqrdmlah h0, h1, v2\.h\[1\]
+ b8: 7f62d020 sqrdmlah h0, h1, v2\.h\[2\]
+ bc: 7f72d020 sqrdmlah h0, h1, v2\.h\[3\]
+ c0: 7f82d020 sqrdmlah s0, s1, v2\.s\[0\]
+ c4: 7fa2d020 sqrdmlah s0, s1, v2\.s\[1\]
+ c8: 7f82d820 sqrdmlah s0, s1, v2\.s\[2\]
+ cc: 7fa2d820 sqrdmlah s0, s1, v2\.s\[3\]
+ d0: 7f42f020 sqrdmlsh h0, h1, v2\.h\[0\]
+ d4: 7f52f020 sqrdmlsh h0, h1, v2\.h\[1\]
+ d8: 7f62f020 sqrdmlsh h0, h1, v2\.h\[2\]
+ dc: 7f72f020 sqrdmlsh h0, h1, v2\.h\[3\]
+ e0: 7f82f020 sqrdmlsh s0, s1, v2\.s\[0\]
+ e4: 7fa2f020 sqrdmlsh s0, s1, v2\.s\[1\]
+ e8: 7f82f820 sqrdmlsh s0, s1, v2\.s\[2\]
+ ec: 7fa2f820 sqrdmlsh s0, s1, v2\.s\[3\]
diff --git a/gas/testsuite/gas/aarch64/rdma.s b/gas/testsuite/gas/aarch64/rdma.s
new file mode 100644
index 0000000..7dbf914
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rdma.s
@@ -0,0 +1,78 @@
+/* rdma.s Test file for AArch64 v8.1 Advanced-SIMD instructions.
+
+ Copyright (C) 2012-2015 Free Software Foundation, Inc. Contributed by ARM Ltd.
+
+ This file is part of GAS.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the license, or
+ (at your option) any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING3. If not,
+ see <http://www.gnu.org/licenses/>. */
+
+
+ .text
+ .ifdef DIRECTIVE
+ .arch_extension rdma
+ .endif
+
+ .macro vect_inst I T
+ \I v0.\()\T, v1.\()\T, v2.\()\T
+ .endm
+
+ .text
+ .irp inst, sqrdmlah, sqrdmlsh
+ .irp type, 4h, 8h, 2s, 4s
+ vect_inst \inst \type
+ .endr
+ .endr
+
+ .macro scalar_inst I R
+ \I \R\()0, \R\()1, \R\()2
+ .endm
+
+ .text
+ .irp inst, sqrdmlah, sqrdmlsh
+ .irp reg, s,h
+ scalar_inst \inst \reg
+ .endr
+ .endr
+
+ .macro vect_indexed_inst I S T N
+ \I v0.\S\T, v1.\S\T, v2.\T[\N]
+ .endm
+
+ .text
+ .irp inst, sqrdmlah, sqrdmlsh
+ .irp size, 4, 8
+ .irp index 0,1,2,3
+ vect_indexed_inst \inst \size h \index
+ .endr
+ .endr
+ .irp size, 2, 4
+ .irp index 0,1,2,3
+ vect_indexed_inst \inst \size s \index
+ .endr
+ .endr
+ .endr
+
+ .macro scalar_indexed_inst I T N
+ \I \T\()0, \T\()1, v2.\T[\N]
+ .endm
+
+ .text
+ .irp inst, sqrdmlah, sqrdmlsh
+ .irp type h,s
+ .irp index 0,1,2,3
+ scalar_indexed_inst \inst \type \index
+ .endr
+ .endr
+ .endr
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2][Aarch64][gas] Add support for ARMv8.1a Adv.SIMD instructions.
2015-05-20 14:55 ` [PATCH 2/2][Aarch64][gas] " Matthew Wahab
@ 2015-05-29 14:59 ` Nicholas Clifton
0 siblings, 0 replies; 4+ messages in thread
From: Nicholas Clifton @ 2015-05-29 14:59 UTC (permalink / raw)
To: Matthew Wahab, binutils
Hi Matthew,
> gas/
> 2015-05-20 Matthew Wahab <matthew.wahab@arm.com>
>
> * config/tc-aarch64.c (aarch64_features): Add "rdma".
> * doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".
>
> gas/testsuite/
> 2015-05-20 Matthew Wahab <matthew.wahab@arm.com>
>
> * rdma-directive.d: New.
> * rdma.d: New.
> * rdma.s: New.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2][Aarch64][binutils] Add support for ARMv8.1a Adv.SIMD instructions.
2015-05-20 14:52 [PATCH 1/2][Aarch64][binutils] Add support for ARMv8.1a Adv.SIMD instructions Matthew Wahab
2015-05-20 14:55 ` [PATCH 2/2][Aarch64][gas] " Matthew Wahab
@ 2015-05-29 14:59 ` Nicholas Clifton
1 sibling, 0 replies; 4+ messages in thread
From: Nicholas Clifton @ 2015-05-29 14:59 UTC (permalink / raw)
To: Matthew Wahab, binutils
Hi Matthew,
> include/
> 2015-05-20 Matthew Wahab <matthew.wahab@arm.com>
>
> * opcode/aarch64.h (AARCH64_FEATURE_RDMA): New.
>
> opcodes/
> 2015-05-20 Matthew Wahab <matthew.wahab@arm.com>
>
> * aarch64-tbl.h (aarch64_feature_rdma): New.
> (RDMA): New.
> (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
> * aarch64-asm-2.c: Regenerate.
> * aarch64-dis-2.c: Regenerate.
> * aarch64-opc-2.c: Regenerate.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2015-05-29 14:59 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2015-05-20 14:52 [PATCH 1/2][Aarch64][binutils] Add support for ARMv8.1a Adv.SIMD instructions Matthew Wahab
2015-05-20 14:55 ` [PATCH 2/2][Aarch64][gas] " Matthew Wahab
2015-05-29 14:59 ` Nicholas Clifton
2015-05-29 14:59 ` [PATCH 1/2][Aarch64][binutils] " Nicholas Clifton
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