Re: [PATCH] x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}

["Jan Beulich" <JBeulich@suse.com>]

>>> On 26.05.15 at 13:24, <kirill.yukhin@gmail.com> wrote:
> Finally, (I promise, I repeat it last time) as far as SDM is not a source of 
> Intel syntax,

Which btw is something I don't really buy, for three reasons:
1) Why would it specify mnemonics (including operands) then in the
first place?
2) Other architectures explicitly use the instruction specifications as
guideline for what assemblers should accept, or even require
assemblers to behave in a certain way (see e.g. ARM ARM).
3) In the absence of any other formal definition, one ought to use
what is there instead of inventing something new.

> I see no reason to allow another order. IMO, such addition might
> even increase confusion about this non-trivial stuff.

Quite the opposite - it eliminates some confusion: Just compare

vcvtsd2ss xmm6\{k7\},xmm5,xmm4,\{rn-sae\}

and

vcvtsi2ss xmm6,xmm5,\{rn-sae\},eax

(found in the unpatched testsuite). In the former and all other
instructions (excepting the questionable ones) the rounding
specifier goes after all source operands.

Jan