From: WANG Xuerui <i.swmail@xen0n.name>
To: liuzhensong <liuzhensong@loongson.cn>,
WANG Xuerui <i.swmail@xen0n.name>,
binutils@sourceware.org
Cc: Chenghua Xu <xuchenghua@loongson.cn>,
Xi Ruoyao <xry111@xry111.site>, WANG Xuerui <git@xen0n.name>,
chenglulu@loongson.cn
Subject: Re: [PATCH 1/2] opcodes: LoongArch: make all non-native jumps desugar to canonical b{lt/ge}[u] forms
Date: Fri, 29 Jul 2022 18:06:21 +0800 [thread overview]
Message-ID: <569a795d-d62a-ab9a-3071-fac52144bf0e@xen0n.name> (raw)
In-Reply-To: <8a0d2034-f7a4-53db-858b-98bddbb36c16@loongson.cn>
On 2022/7/29 18:02, liuzhensong wrote:
>
> 在 2022/7/29 下午5:42, WANG Xuerui 写道:
>> On 2022/7/29 09:18, liuzhensong wrote:
>>>
>>>
>>> On 2022/7/27 下午7:07, WANG Xuerui wrote:
>>>> From: WANG Xuerui<git@xen0n.name>
>>>>
>>>> Also re-order the jump/branch opcodes while at it, so that insns are
>>>> sorted in ascending order according to opcodes, and the label form
>>>> preceding the real definition.
>>>> ---
>>>> opcodes/loongarch-opc.c | 31 ++++++++++++-------------------
>>>> 1 file changed, 12 insertions(+), 19 deletions(-)
>>>>
>>>> diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
>>>> index 08ba101a902..6f5e42d57e5 100644
>>>> --- a/opcodes/loongarch-opc.c
>>>> +++ b/opcodes/loongarch-opc.c
>>>> @@ -810,22 +810,13 @@ static struct loongarch_opcode
>>>> loongarch_float_jmp_opcodes[] =
>>>> static struct loongarch_opcode loongarch_jmp_opcodes[] =
>>>> {
>>>> /* match, mask, name, format, macro,
>>>> include, exclude, pinfo. */
>>>> - { 0x0, 0x0, "bltz", "r,la", "bltz
>>>> %1,%%b16(%2)", 0, 0, 0 },
>>>> - { 0x60000000, 0xfc00001f, "bltz", "r5:5,sb10:16<<2",
>>>> 0, 0, 0, 0 },
>>>> - { 0x0, 0x0, "bgtz", "r,la", "bgtz
>>>> %1,%%b16(%2)", 0, 0, 0 },
>>>> - { 0x60000000, 0xfc0003e0, "bgtz", "r0:5,sb10:16<<2",
>>>> 0, 0, 0, 0 },
>>>> - { 0x0, 0x0, "bgez", "r,la", "bgez
>>>> %1,%%b16(%2)", 0, 0, 0 },
>>>> - { 0x64000000, 0xfc00001f, "bgez", "r5:5,sb10:16<<2",
>>>> 0, 0, 0, 0 },
>>>> - { 0x0, 0x0, "blez", "r,la", "blez
>>>> %1,%%b16(%2)", 0, 0, 0 },
>>>> - { 0x64000000, 0xfc0003e0, "blez", "r0:5,sb10:16<<2",
>>>> 0, 0, 0, 0 },
>>>> { 0x0, 0x0, "beqz", "r,la", "beqz
>>>> %1,%%b21(%2)", 0, 0, 0 },
>>>> { 0x40000000, 0xfc000000, "beqz",
>>>> "r5:5,sb0:5|10:16<<2", 0, 0, 0, 0 },
>>>> { 0x0, 0x0, "bnez", "r,la", "bnez
>>>> %1,%%b21(%2)", 0, 0, 0 },
>>>> { 0x44000000, 0xfc000000, "bnez",
>>>> "r5:5,sb0:5|10:16<<2", 0, 0, 0, 0 },
>>>> - { 0x0, 0x0, "jr", "r", "jirl $r0,%1,0",
>>>> 0, 0, 0 },
>>>> - { 0x50000000, 0xfc000000, "b", "sb0:10|10:16<<2",
>>>> 0, 0, 0, 0 },
>>>> - { 0x0, 0x0, "b", "la", "b
>>>> %%b26(%1)", 0, 0, 0 },
>>>> { 0x4c000000, 0xfc000000, "jirl",
>>>> "r0:5,r5:5,s10:16<<2", 0, 0, 0, 0 },
>>>> + { 0x0, 0x0, "b", "la", "b
>>>> %%b26(%1)", 0, 0, 0 },
>>>> + { 0x50000000, 0xfc000000, "b", "sb0:10|10:16<<2",
>>>> 0, 0, 0, 0 },
>>>> { 0x0, 0x0, "bl", "la", "bl
>>>> %%b26(%1)", 0, 0, 0 },
>>>> { 0x54000000, 0xfc000000, "bl", "sb0:10|10:16<<2",
>>>> 0, 0, 0, 0 },
>>>> { 0x0, 0x0, "beq", "r,r,la", "beq
>>>> %1,%2,%%b16(%3)", 0, 0, 0 },
>>>> @@ -834,20 +825,22 @@ static struct loongarch_opcode
>>>> loongarch_jmp_opcodes[] =
>>>> { 0x5c000000, 0xfc000000, "bne",
>>>> "r5:5,r0:5,sb10:16<<2", 0, 0, 0, 0 },
>>>> { 0x0, 0x0, "blt", "r,r,la", "blt
>>>> %1,%2,%%b16(%3)", 0, 0, 0 },
>>>> { 0x60000000, 0xfc000000, "blt",
>>>> "r5:5,r0:5,sb10:16<<2", 0, 0, 0, 0 },
>>>> - { 0x0, 0x0, "bgt", "r,r,la", "bgt
>>>> %1,%2,%%b16(%3)", 0, 0, 0 },
>>>> - { 0x60000000, 0xfc000000, "bgt",
>>>> "r0:5,r5:5,sb10:16<<2", 0, 0, 0, 0 },
>>>> { 0x0, 0x0, "bge", "r,r,la", "bge
>>>> %1,%2,%%b16(%3)", 0, 0, 0 },
>>>> { 0x64000000, 0xfc000000, "bge",
>>>> "r5:5,r0:5,sb10:16<<2", 0, 0, 0, 0 },
>>>> - { 0x0, 0x0, "ble", "r,r,la", "ble
>>>> %1,%2,%%b16(%3)", 0, 0, 0 },
>>>> - { 0x64000000, 0xfc000000, "ble",
>>>> "r0:5,r5:5,sb10:16<<2", 0, 0, 0, 0 },
>>>> { 0x0, 0x0, "bltu", "r,r,la", "bltu
>>>> %1,%2,%%b16(%3)", 0, 0, 0 },
>>>> { 0x68000000, 0xfc000000, "bltu",
>>>> "r5:5,r0:5,sb10:16<<2", 0, 0, 0, 0 },
>>>> - { 0x0, 0x0, "bgtu", "r,r,la", "bgtu
>>>> %1,%2,%%b16(%3)", 0, 0, 0 },
>>>> - { 0x68000000, 0xfc000000, "bgtu",
>>>> "r0:5,r5:5,sb10:16<<2", 0, 0, 0, 0 },
>>>> { 0x0, 0x0, "bgeu", "r,r,la", "bgeu
>>>> %1,%2,%%b16(%3)", 0, 0, 0 },
>>>> { 0x6c000000, 0xfc000000, "bgeu",
>>>> "r5:5,r0:5,sb10:16<<2", 0, 0, 0, 0 },
>>>> - { 0x0, 0x0, "bleu", "r,r,la", "bleu
>>>> %1,%2,%%b16(%3)", 0, 0, 0 },
>>>> - { 0x6c000000, 0xfc000000, "bleu",
>>>> "r0:5,r5:5,sb10:16<<2", 0, 0, 0, 0 },
>>>> + /* Jumps implemented with macros. */
>>>> + { 0x0, 0x0, "bgt", "r,r,la", "blt
>>>> %2,%1,%%b16(%3)", 0, 0, 0 },
>>>> + { 0x0, 0x0, "ble", "r,r,la", "bge
>>>> %2,%1,%%b16(%3)", 0, 0, 0 },
>>>> + { 0x0, 0x0, "bltz", "r,la", "blt
>>>> %1,$r0,%%b16(%2)", 0, 0, 0 },
>>>> + { 0x0, 0x0, "bgtz", "r,la", "blt
>>>> $r0,%1,%%b16(%2)", 0, 0, 0 },
>>>> + { 0x0, 0x0, "bgez", "r,la", "bge
>>>> %1,$r0,%%b16(%2)", 0, 0, 0 },
>>>> + { 0x0, 0x0, "blez", "r,la", "bge
>>>> $r0,%1,%%b16(%2)", 0, 0, 0 },
>>>> + { 0x0, 0x0, "bgtu", "r,r,la", "bltu
>>>> %2,%1,%%b16(%3)", 0, 0, 0 },
>>>> + { 0x0, 0x0, "bleu", "r,r,la", "bgeu
>>>> %2,%1,%%b16(%3)", 0, 0, 0 },
>>>> + { 0x0, 0x0, "jr", "r", "jirl $r0,%1,0",
>>>> 0, 0, 0 },
>>>> { 0 } /* Terminate the list. */
>>>> };
>>> Looks good to me. And I don't think the instruction "ret" is
>>> necessary in [PATCH 2/2].
>>
>> Please don't be so subjective. You and Chenghua never gave objective
>> reasons against "ret", your rejections seem to be just based on some
>> kind of personal preference. All while ignoring the objective
>> readability improvement and ease of learning gained by adding such
>> support, and I believe there must be community members in favor of
>> the addition.
>>
>> And it's not like everyone must immediately migrate to it, people may
>> well continue to write "jr ra" or even "jirl zero, ra, 0", only those
>> of us preferring brevity would have one more palatable choice...
> If gcc is not required to be generated instruction "ret" by default, I
> think it can be added.
>
Yeah that was never my intention to force everyone onto this. I always
wanted to ease the learning curve of LoongArch assembly, and improve its
readability and brevity along the way. All my effort around the
assembler is centered around this, including the addition of "ret" of
course.
And thanks for the very much needed communication and understanding.
next prev parent reply other threads:[~2022-07-29 10:06 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-27 11:07 [PATCH 0/2] opcodes: LoongArch: Cleanups to jumps WANG Xuerui
2022-07-27 11:07 ` [PATCH 1/2] opcodes: LoongArch: make all non-native jumps desugar to canonical b{lt/ge}[u] forms WANG Xuerui
2022-07-29 1:18 ` liuzhensong
2022-07-29 9:42 ` WANG Xuerui
2022-07-29 10:02 ` liuzhensong
2022-07-29 10:06 ` WANG Xuerui [this message]
2022-08-01 3:43 ` liuzhensong
2022-07-27 11:07 ` [PATCH 2/2] opcodes: LoongArch: add "ret" instruction to reduce typing WANG Xuerui
2022-07-27 13:26 ` Xi Ruoyao
2022-07-29 10:09 ` WANG Xuerui
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