* [PATCH] gas/opcodes: Add initial arc nps400 support
@ 2016-02-25 23:39 Andrew Burgess
2016-02-29 11:00 ` Claudiu Zissulescu
0 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-02-25 23:39 UTC (permalink / raw)
To: binutils; +Cc: noamca, Claudiu.Zissulescu, Cupertino.Miranda, Andrew Burgess
The ARC NPS400 is an ARC700 with some additional instructions, created
by Mellanox (formally EZchip). This commit adds initial support for the
ARC NPS400 variant.
At this stage I have added only one new instruction, movb, this is to
allow a discussion of the correct approach for adding additional
instructions to the arc target. Additional instructions, and supporting
relocations will be added in future commits.
When binutils is configured for NPS400, by specifying 'mellanox' as the
vendor name in the target tuple, then the additional NPS400 instructions
are added into the ARC700 instruction set (within the opcodes library),
and in the assembler, the default architecture is changed to be ARC700.
There's a test for the new instruction, a test for the default
architecture, and one test needs updating slightly.
gas/ChangeLog:
* config.in: Regenerate.
* config/tc-arc.c (arc_target): Don't provide an initial value.
(arc_target_name): Likewise.
(arc_features): Likewise.
(arc_mach_type): Likewise.
(arc_select_cpu): New function.
(md_begin): Call arc_select_cpu.
(md_parse_option): Move initialisation into arc_select_cpu.
* configure: Regenerate.
* configure.ac: Detect mellanox arc target.
* testsuite/gas/arc/nps400-0.d: New file.
* testsuite/gas/arc/nps400-0.s: New file.
* testsuite/gas/arc/nps400-1.d: New file.
* testsuite/gas/arc/nps400-1.s: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: New file.
* arc-opc.c: Add top level comment.
(insert_nps_dst): New function.
(extract_nps_dst): New function.
(insert_nps_j_dst): New function.
(extract_nps_j_dst): New function.
(insert_nps_dup_src1): New function.
(extract_nps_dup_src1): New function.
(insert_nps_src2): New function.
(extract_nps_src2): New function.
(insert_nps_bitop_size): New function.
(extract_nps_bitop_size): New function.
(arc_flag_operands): Add nps400 entries.
(arc_flag_classes): Add nps400 entries.
(arc_operands): Add nps400 entries.
(arc_opcodes): Add nps400 entries.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Detect NPS400 ARC target.
binutils/ChangeLog:
* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700.
---
binutils/ChangeLog | 4 +
binutils/testsuite/binutils-all/objdump.exp | 2 +-
gas/ChangeLog | 17 +++
gas/config.in | 3 +
gas/config/tc-arc.c | 92 ++++++-----
gas/configure | 10 ++
gas/configure.ac | 8 +
gas/testsuite/gas/arc/nps400-0.d | 16 ++
gas/testsuite/gas/arc/nps400-0.s | 2 +
gas/testsuite/gas/arc/nps400-1.d | 15 ++
gas/testsuite/gas/arc/nps400-1.s | 7 +
opcodes/ChangeLog | 22 +++
opcodes/arc-nps400-tbl.h | 3 +
opcodes/arc-opc.c | 229 ++++++++++++++++++++++++++++
opcodes/config.in | 3 +
opcodes/configure | 8 +
opcodes/configure.ac | 6 +
17 files changed, 405 insertions(+), 42 deletions(-)
create mode 100644 gas/testsuite/gas/arc/nps400-0.d
create mode 100644 gas/testsuite/gas/arc/nps400-0.s
create mode 100644 gas/testsuite/gas/arc/nps400-1.d
create mode 100644 gas/testsuite/gas/arc/nps400-1.s
create mode 100644 opcodes/arc-nps400-tbl.h
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index bbaa373..4026d0d 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700.
+
2016-02-16 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/19647
diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp
index 22c4686..eb4d5f4 100644
--- a/binutils/testsuite/binutils-all/objdump.exp
+++ b/binutils/testsuite/binutils-all/objdump.exp
@@ -34,7 +34,7 @@ send_user "Version [binutil_version $OBJDUMP]"
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
-lappend cpus_expected aarch64 alpha arc ARCv2 arm cris
+lappend cpus_expected aarch64 alpha arc ARCv2 ARC700 arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 0e9222e..6655ff7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,20 @@
+2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config.in: Regenerate.
+ * config/tc-arc.c (arc_target): Don't provide an initial value.
+ (arc_target_name): Likewise.
+ (arc_features): Likewise.
+ (arc_mach_type): Likewise.
+ (arc_select_cpu): New function.
+ (md_begin): Call arc_select_cpu.
+ (md_parse_option): Move initialisation into arc_select_cpu.
+ * configure: Regenerate.
+ * configure.ac: Detect mellanox arc target.
+ * testsuite/gas/arc/nps400-0.d: New file.
+ * testsuite/gas/arc/nps400-0.s: New file.
+ * testsuite/gas/arc/nps400-1.d: New file.
+ * testsuite/gas/arc/nps400-1.s: New file.
+
2016-02-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* as.c (select_emulation_mode): Add const qualifiers.
diff --git a/gas/config.in b/gas/config.in
index 8b040fc..3462912 100644
--- a/gas/config.in
+++ b/gas/config.in
@@ -13,6 +13,9 @@
/* Define if using AIX 5.2 value for C_WEAKEXT. */
#undef AIX_WEAK_SUPPORT
+/* ARC NPS400 support. */
+#undef ARC_NPS400
+
/* assert broken? */
#undef BROKEN_ASSERT
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 82cff9a..70afb81 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -310,13 +310,14 @@ static void assemble_insn
(const struct arc_opcode *, const expressionS *, int,
const struct arc_flags *, int, struct arc_insn *);
-/* The cpu for which we are generating code. */
-static unsigned arc_target = ARC_OPCODE_BASE;
-static const char *arc_target_name = "<all>";
-static unsigned arc_features = 0x00;
+/* The cpu for which we are generating code. These are initialised either
+ by command line options, or set to a sane default in md_begin. */
+static unsigned arc_target;
+static const char *arc_target_name;
+static unsigned arc_features;
/* The default architecture. */
-static int arc_mach_type = bfd_mach_arc_arcv2;
+static int arc_mach_type;
/* Non-zero if the cpu type has been explicitly specified. */
static int mach_type_specified_p = 0;
@@ -569,6 +570,40 @@ md_number_to_chars_midend (char *buf, valueT val, int n)
}
}
+/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
+ the relevant static global variables. */
+
+static void
+arc_select_cpu (const char *arg)
+{
+ int cpu_flags = EF_ARC_CPU_GENERIC;
+ int i;
+ char *dst, *cpu = alloca (strlen (arg) + 1);
+ const char *src;
+
+ for (dst = cpu, src = arg; *src != '\0'; ++dst, ++src)
+ *dst = TOLOWER (*src);
+
+ for (i = 0; cpu_types[i].name; ++i)
+ {
+ if (!strcmp (cpu_types[i].name, cpu))
+ {
+ arc_target = cpu_types[i].flags;
+ arc_target_name = cpu_types[i].name;
+ arc_features = cpu_types[i].features;
+ arc_mach_type = cpu_types[i].mach;
+ cpu_flags = cpu_types[i].eflags;
+ break;
+ }
+ }
+
+ if (!cpu_types[i].name)
+ as_fatal (_("unknown architecture: %s\n"), arg);
+
+ if (cpu_flags != EF_ARC_CPU_GENERIC)
+ arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+}
+
/* Here ends all the ARCompact extension instruction assembling
stuff. */
@@ -2067,6 +2102,15 @@ md_begin (void)
{
unsigned int i;
+ if (!mach_type_specified_p)
+ {
+#ifdef ARC_NPS400
+ arc_select_cpu ("arc700");
+#else
+ arc_select_cpu ("all");
+#endif
+ }
+
/* The endianness can be chosen "at the factory". */
target_big_endian = byte_order == BIG_ENDIAN;
@@ -2853,8 +2897,6 @@ arc_parse_name (const char *name,
int
md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
{
- int cpu_flags = EF_ARC_CPU_GENERIC;
-
switch (c)
{
case OPTION_ARC600:
@@ -2872,37 +2914,8 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
case OPTION_MCPU:
{
- int i;
- char *s = alloca (strlen (arg) + 1);
-
- {
- char *t = s;
- char *arg1 = arg;
-
- do
- *t = TOLOWER (*arg1++);
- while (*t++);
- }
-
- for (i = 0; cpu_types[i].name; ++i)
- {
- if (!strcmp (cpu_types[i].name, s))
- {
- arc_target = cpu_types[i].flags;
- arc_target_name = cpu_types[i].name;
- arc_features = cpu_types[i].features;
- arc_mach_type = cpu_types[i].mach;
- cpu_flags = cpu_types[i].eflags;
-
- mach_type_specified_p = 1;
- break;
- }
- }
-
- if (!cpu_types[i].name)
- {
- as_fatal (_("unknown architecture: %s\n"), arg);
- }
+ arc_select_cpu (arg);
+ mach_type_specified_p = 1;
break;
}
@@ -2956,9 +2969,6 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
return 0;
}
- if (cpu_flags != EF_ARC_CPU_GENERIC)
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
-
return 1;
}
diff --git a/gas/configure b/gas/configure
index cd7182f..be39ffa 100755
--- a/gas/configure
+++ b/gas/configure
@@ -12160,6 +12160,16 @@ _ACEOF
# Other random stuff.
case ${cpu_type} in
+ arc)
+ case ${target} in
+ arc*-mellanox-*)
+
+$as_echo "#define ARC_NPS400 1" >>confdefs.h
+
+ ;;
+ esac
+ ;;
+
mips)
# Set mips_cpu to the name of the default CPU.
case ${target_cpu} in
diff --git a/gas/configure.ac b/gas/configure.ac
index 377526e..d72ecd4 100644
--- a/gas/configure.ac
+++ b/gas/configure.ac
@@ -234,6 +234,14 @@ changequote([,])dnl
# Other random stuff.
case ${cpu_type} in
+ arc)
+ case ${target} in
+ arc*-mellanox-*)
+ AC_DEFINE(ARC_NPS400, 1, [ARC NPS400 support.])
+ ;;
+ esac
+ ;;
+
mips)
# Set mips_cpu to the name of the default CPU.
case ${target_cpu} in
diff --git a/gas/testsuite/gas/arc/nps400-0.d b/gas/testsuite/gas/arc/nps400-0.d
new file mode 100644
index 0000000..09e62b3
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.d
@@ -0,0 +1,16 @@
+#as:
+#target: arc*-mellanox-*
+#readelf: -h
+
+#...
+ Class: ELF32
+ Data: 2's complement, .* endian
+ Version: 1 \(current\)
+ OS/ABI: UNIX - System V
+ ABI Version: 0
+ Type: REL \(Relocatable file\)
+ Machine: ARCompact
+ Version: 0x1
+#...
+ Flags: 0x303, ARC 700, v3 no-legacy-syscalls ABI
+#...
\ No newline at end of file
diff --git a/gas/testsuite/gas/arc/nps400-0.s b/gas/testsuite/gas/arc/nps400-0.s
new file mode 100644
index 0000000..2b6cc1d
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.s
@@ -0,0 +1,2 @@
+ .text
+ nop
diff --git a/gas/testsuite/gas/arc/nps400-1.d b/gas/testsuite/gas/arc/nps400-1.d
new file mode 100644
index 0000000..bd68eb0
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.d
@@ -0,0 +1,15 @@
+#as: -mcpu=arc700
+#target: arc*-mellanox-*
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 4821 1485 movb r0,r0,r1,0x4,0x5,0x6
+ 4: 4881 1485 movb r0,r0,r12,0x4,0x5,0x6
+ 8: 4f81 1485 movb r15,r15,r12,0x4,0x5,0x6
+ c: 4821 9485 movb.cl r0,r1,0x4,0x5,0x6
+ 10: 48c1 9485 movb.cl r0,r14,0x4,0x5,0x6
+ 14: 4d21 9485 movb.cl r13,r1,0x4,0x5,0x6
diff --git a/gas/testsuite/gas/arc/nps400-1.s b/gas/testsuite/gas/arc/nps400-1.s
new file mode 100644
index 0000000..1d340b3
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.s
@@ -0,0 +1,7 @@
+ .text
+ movb r0, r0, r1, 4, 5, 6
+ movb r0, r0, r12, 4, 5, 6
+ movb r15, r15, r12, 4, 5, 6
+ movb.cl r0, r1, 4, 5, 6
+ movb.cl r0, r14, 4, 5, 6
+ movb.cl r13, r1, 4, 5, 6
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f95fd6a..dca02cb 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,25 @@
+2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: New file.
+ * arc-opc.c: Add top level comment.
+ (insert_nps_dst): New function.
+ (extract_nps_dst): New function.
+ (insert_nps_j_dst): New function.
+ (extract_nps_j_dst): New function.
+ (insert_nps_dup_src1): New function.
+ (extract_nps_dup_src1): New function.
+ (insert_nps_src2): New function.
+ (extract_nps_src2): New function.
+ (insert_nps_bitop_size): New function.
+ (extract_nps_bitop_size): New function.
+ (arc_flag_operands): Add nps400 entries.
+ (arc_flag_classes): Add nps400 entries.
+ (arc_operands): Add nps400 entries.
+ (arc_opcodes): Add nps400 entries.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+ * configure.ac: Detect NPS400 ARC target.
+
2016-02-24 Renlin Li <renlin.li@arm.com>
* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
new file mode 100644
index 0000000..27207b1
--- /dev/null
+++ b/opcodes/arc-nps400-tbl.h
@@ -0,0 +1,3 @@
+/* movb<.f><.cl> */
+{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, { NPS_R_J_DST, NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 9a674d5..398fecb 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -26,6 +26,12 @@
#include "opintl.h"
#include "libiberty.h"
+/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
+ instructions. Support for this target is available when binutils is
+ configured and built for the 'arc*-mellanox-*-*' target. As far as
+ possible all ARC NPS400 features are built into all ARC target builds as
+ this reduces the chances that regressions might creep in. */
+
/* Insert RB register into a 32-bit opcode. */
static unsigned
insert_rb (unsigned insn,
@@ -637,6 +643,188 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
return value;
}
+/* ARC NPS400 Support: See comment near head of file. */
+static unsigned
+insert_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 24;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 24;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_j_dst (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 24;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 24;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_j_dst (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value;
+
+ /* If the CL flag is not set then this is invalid. */
+ if (((insn >> 15) & 0x1) == 0)
+ *invalid = TRUE;
+ value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_dup_src1 (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 24;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 24;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_dup_src1 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value;
+
+ /* If the CL flag is set then this is invalid. */
+ if (((insn >> 15) & 0x1) == 0x1)
+ *invalid = TRUE;
+ value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 21;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 21;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 21) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value < 1 || value > 32)
+ {
+ *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
+ return insn;
+ }
+
+ --value;
+ insn |= ((value & 0x1f) << 10);
+ return insn;
+}
+
+static int
+extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 10) & 0x1f) + 1;
+}
+
/* Include the generic extract/insert functions. Order is important
as some of the functions present in the .h may be disabled via
defines. */
@@ -795,6 +983,13 @@ const struct arc_flag_operand arc_flag_operands[] =
/* Fake Flags. */
#define F_NE (F_H17 + 1)
{ "ne", 0, 0, 0, 1 },
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define F_NPS_CL (F_NE + 1)
+ { "cl", 1, 1, 15, 1 },
+
+#define F_NPS_FLAG (F_NPS_CL + 1)
+ { "f", 1, 1, 20, 1 },
};
const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
@@ -865,6 +1060,13 @@ const struct arc_flag_class arc_flag_classes[] =
#define C_NE (C_AS + 1)
{ CND, { F_NE, F_NULL}},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define C_NPS_CL (C_NE + 1)
+ { FLG, { F_NPS_CL, F_NULL}},
+
+#define C_NPS_F (C_NPS_CL + 1)
+ { FLG, { F_NPS_FLAG, F_NULL}},
};
/* The operands table.
@@ -1183,6 +1385,29 @@ const struct arc_operand arc_operands[] =
/* UIMM6_5_S mask = 0000011111100000. */
#define UIMM6_5_S (W6 + 1)
{6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define NPS_R_DST (UIMM6_5_S + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_dst },
+
+#define NPS_R_J_DST (NPS_R_DST + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_j_dst, extract_nps_j_dst },
+
+#define NPS_R_SRC1 (NPS_R_J_DST + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_dup_src1, extract_nps_dup_src1 },
+
+#define NPS_R_SRC2 (NPS_R_SRC1 + 1)
+ { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_src2, extract_nps_src2 },
+
+ /* Next 3 operands are integer immediate for bitops. */
+#define NPS_BITOP_DST_POS (NPS_R_SRC2 + 1)
+ { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
+ { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
@@ -1198,6 +1423,10 @@ const unsigned arc_NToperand = FKT_NT;
const struct arc_opcode arc_opcodes[] =
{
#include "arc-tbl.h"
+
+#ifdef ARC_NPS400
+#include "arc-nps400-tbl.h"
+#endif
};
const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
diff --git a/opcodes/config.in b/opcodes/config.in
index 55a80fd..34b194a 100644
--- a/opcodes/config.in
+++ b/opcodes/config.in
@@ -7,6 +7,9 @@
#endif
#define __CONFIG_H__ 1
+/* ARC NPS400 support. */
+#undef ARC_NPS400
+
/* Define to 1 if translation of program messages to the user's native
language is requested. */
#undef ENABLE_NLS
diff --git a/opcodes/configure b/opcodes/configure
index 75c6573..258c963 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12505,6 +12505,14 @@ fi
# target-specific stuff:
+case ${target} in
+ arc*-mellanox-*)
+
+$as_echo "#define ARC_NPS400 1" >>confdefs.h
+
+ ;;
+esac
+
# Canonicalize the secondary target names.
if test -n "$enable_targets" ; then
for targ in `echo $enable_targets | sed 's/,/ /g'`
diff --git a/opcodes/configure.ac b/opcodes/configure.ac
index c7f4783..1dbe70b 100644
--- a/opcodes/configure.ac
+++ b/opcodes/configure.ac
@@ -210,6 +210,12 @@ AC_SUBST(SHARED_DEPENDENCIES)
# target-specific stuff:
+case ${target} in
+ arc*-mellanox-*)
+ AC_DEFINE(ARC_NPS400, 1, [ARC NPS400 support.])
+ ;;
+esac
+
# Canonicalize the secondary target names.
if test -n "$enable_targets" ; then
for targ in `echo $enable_targets | sed 's/,/ /g'`
--
2.6.4
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH] gas/opcodes: Add initial arc nps400 support
2016-02-25 23:39 [PATCH] gas/opcodes: Add initial arc nps400 support Andrew Burgess
@ 2016-02-29 11:00 ` Claudiu Zissulescu
2016-03-01 15:15 ` Andrew Burgess
0 siblings, 1 reply; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-02-29 11:00 UTC (permalink / raw)
To: Andrew Burgess, binutils; +Cc: noamca, Cupertino.Miranda
H Andrew,
I have some small remarks regarding your patch. Please find them inserted.
>
> +/* ARC NPS400 support. */
> +#undef ARC_NPS400
> +
My opinion is we do not need this define, or at least not in this form. If we want to support multiple selective cpu targets, maybe we should (un)define something like ARC_CPU_DEFAULT. Where this macro will be initialized with a desired cpu by the configure script file. This may make sense for example when the assembler needs to behave differently between two cpu configurations, but as far as I can see there is not the case for the time being.
> + if (!mach_type_specified_p)
> + {
> +#ifdef ARC_NPS400
> + arc_select_cpu ("arc700");
> +#else
> + arc_select_cpu ("all");
> +#endif
> + }
You can let the default cpu to arc700. The "all" stuff is just for testing purposes, and needed to be removed anyhow.
> + arc)
> + case ${target} in
> + arc*-mellanox-*)
> +
> +$as_echo "#define ARC_NPS400 1" >>confdefs.h
> +
> + ;;
> + esac
> + ;;
> +
See my above comments.
> + arc)
> + case ${target} in
> + arc*-mellanox-*)
> + AC_DEFINE(ARC_NPS400, 1, [ARC NPS400 support.])
> + ;;
> + esac
> + ;;
> +
Likewise.
> +++ b/opcodes/arc-nps400-tbl.h
> @@ -0,0 +1,3 @@
> +/* movb<.f><.cl> */
> +{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, {
> +NPS_R_DST, NPS_R_SRC1, NPS_R_SRC2, NPS_BITOP_DST_POS,
> +NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, { "movb",
> +0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, {
> NPS_R_J_DST,
> +NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS,
> NPS_BITOP_SIZE }, {
> +C_NPS_F, C_NPS_CL }},
Probably the best will be to make a file common for all other users of ARC architecture which are having their own custom instructions. Hence, I would propose to rename arc-nps400-tbl.h to arc-ext-tbl.h or something of a sort. Also, if you would like those instructions to be enabled by a particular assembler option, you can use a new Subclass category (e.g., add NPS400 to insn_subclass_t) instead of NONE, and match against it. It may make sense as your opcodes are overlapping with other arc instructions. In this situation, the disassembler may choose the first ones instead of yours. However, in this case, we need to add an option to the disassembler as well.
> +/* ARC NPS400 Support: See comment near head of file. */ static
> +unsigned insert_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
> + int value ATTRIBUTE_UNUSED,
> + const char **errmsg ATTRIBUTE_UNUSED) {
> + switch (value)
> + {
> + case 0:
> + case 1:
> + case 2:
> + case 3:
> + insn |= value << 24;
> + break;
> + case 12:
> + case 13:
> + case 14:
> + case 15:
> + insn |= (value - 8) << 24;
> + break;
> + default:
> + *errmsg = _("Register must be either r0-r3 or r12-r15.");
> + break;
> + }
> + return insn;
> +}
> +
> +static int
> +extract_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
> + bfd_boolean * invalid ATTRIBUTE_UNUSED) {
> + int value = (insn >> 24) & 0x07;
> + if (value > 3)
> + return (value + 8);
> + else
> + return value;
> +}
> +
> +static unsigned
> +insert_nps_j_dst (unsigned insn ATTRIBUTE_UNUSED,
> + int value ATTRIBUTE_UNUSED,
> + const char **errmsg ATTRIBUTE_UNUSED) {
> + switch (value)
> + {
> + case 0:
> + case 1:
> + case 2:
> + case 3:
> + insn |= value << 24;
> + break;
> + case 12:
> + case 13:
> + case 14:
> + case 15:
> + insn |= (value - 8) << 24;
> + break;
> + default:
> + *errmsg = _("Register must be either r0-r3 or r12-r15.");
> + break;
> + }
> + return insn;
> +}
This function looks similar with insert_nps_dst(). Is not possible to use a single function only?
> +static unsigned
> +insert_nps_dup_src1 (unsigned insn ATTRIBUTE_UNUSED,
> + int value ATTRIBUTE_UNUSED,
> + const char **errmsg ATTRIBUTE_UNUSED) {
> + switch (value)
> + {
> + case 0:
> + case 1:
> + case 2:
> + case 3:
> + insn |= value << 24;
> + break;
> + case 12:
> + case 13:
> + case 14:
> + case 15:
> + insn |= (value - 8) << 24;
> + break;
> + default:
> + *errmsg = _("Register must be either r0-r3 or r12-r15.");
> + break;
> + }
> + return insn;
> +}
Also this looks identical with insert_nps_dst() function.
>
> const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); @@ -
> 1198,6 +1423,10 @@ const unsigned arc_NToperand = FKT_NT; const struct
> arc_opcode arc_opcodes[] = { #include "arc-tbl.h"
> +
> +#ifdef ARC_NPS400
> +#include "arc-nps400-tbl.h"
> +#endif
> };
See my comments on ARC_NPS400.
Bottom line: I would drop the ARC_NPS400 construction at all, I would make the arc-ext-tbl.h file with my new instructions, keep the changes in tc-arc.c and optimize the ones in arc-opcodes.c. Eventually, I would add a new subclass for the extra instructions.
N.B. Although the current binutils arc backend is not supporting the .extInstruction and friends, we will try to add it soon.
Best,
Claudiu
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH] gas/opcodes: Add initial arc nps400 support
2016-02-29 11:00 ` Claudiu Zissulescu
@ 2016-03-01 15:15 ` Andrew Burgess
2016-03-01 20:53 ` Claudiu Zissulescu
0 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-01 15:15 UTC (permalink / raw)
To: Claudiu Zissulescu; +Cc: binutils, noamca, Cupertino.Miranda
* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2016-02-29 11:00:05 +0000]:
Hi Claudiu,
Thanks for your feedback. I have some follow on questions:
> >
> > +/* ARC NPS400 support. */
> > +#undef ARC_NPS400
> > +
> My opinion is we do not need this define, or at least not in this
> form. If we want to support multiple selective cpu targets, maybe we
> should (un)define something like ARC_CPU_DEFAULT. Where this macro
> will be initialized with a desired cpu by the configure script
> file. This may make sense for example when the assembler needs to
> behave differently between two cpu configurations, but as far as I
> can see there is not the case for the time being.
So do you see the 'ARC_CPU_DEFAULT' being defined to 'ARC700' for the
current stock arc binutils, and then set to 'NPS400' for the Mellanox
NPS400 binutils?
The name feels wrong to me, the default for both core arc, and nps400
would still be arc700, it's just in the nps400 case we have an
additional feature enabled; one that adds some additional
instructions.
If the default architecture for arc changes to arc700 as you suggest
below, then all uses of ARC_NPS400 disappear from gas, so the config
changes can also be dropped.
That leaves just a single use of ARC_NPS400 in the opcode library,
where we include the extension instructions. One possibility would be
that I could create a define call ARC_OPCODE_EXTENSION_INSN_FILE or
some such. This would be undefined for core arc, and defined to
"arc-nps400-tbl.h" for nps400, then in arc_opcodes[] we can say:
#ifdef ARC_OPCODE_EXTENSION_INSN_FILE
#include ARC_OPCODE_EXTENSION_INSN_FILE
#endif
Would that be better?
If you still prefer ARC_CPU_DEFAULT, could you expand a little more on
how you see it being used please.
>
> > + if (!mach_type_specified_p)
> > + {
> > +#ifdef ARC_NPS400
> > + arc_select_cpu ("arc700");
> > +#else
> > + arc_select_cpu ("all");
> > +#endif
> > + }
> You can let the default cpu to arc700. The "all" stuff is just for
> testing purposes, and needed to be removed anyhow.
OK, I'll do that.
>
> > + arc)
> > + case ${target} in
> > + arc*-mellanox-*)
> > +
> > +$as_echo "#define ARC_NPS400 1" >>confdefs.h
> > +
> > + ;;
> > + esac
> > + ;;
> > +
> See my above comments.
>
> > + arc)
> > + case ${target} in
> > + arc*-mellanox-*)
> > + AC_DEFINE(ARC_NPS400, 1, [ARC NPS400 support.])
> > + ;;
> > + esac
> > + ;;
> > +
> Likewise.
>
> > +++ b/opcodes/arc-nps400-tbl.h
> > @@ -0,0 +1,3 @@
> > +/* movb<.f><.cl> */
> > +{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, {
> > +NPS_R_DST, NPS_R_SRC1, NPS_R_SRC2, NPS_BITOP_DST_POS,
> > +NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, { "movb",
> > +0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, {
> > NPS_R_J_DST,
> > +NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS,
> > NPS_BITOP_SIZE }, {
> > +C_NPS_F, C_NPS_CL }},
>
> Probably the best will be to make a file common for all other users
> of ARC architecture which are having their own custom
> instructions. Hence, I would propose to rename arc-nps400-tbl.h to
> arc-ext-tbl.h or something of a sort.
I'm not sure I like that idea. Keeping different extensions separate
would be best I think.
The total number of extensions is likely to be pretty low, but the
number of entries in (this one at least) is likely to be ~100.
Keeping them separate will help provide more structure to the code,
making it more obvious which sets of extensions go together.
> Also, if you would like those
> instructions to be enabled by a particular assembler option, you can
> use a new Subclass category (e.g., add NPS400 to insn_subclass_t)
> instead of NONE, and match against it. It may make sense as your
> opcodes are overlapping with other arc instructions.
Which instructions do they overlap with? I thought that these new
instructions fitted into the gap in the arc architecture reserved for
after-market extensions (major opcode 0x09).
As an experiment I assembled the nps400 new instruction test case
using the nps400 binutils then disassemble using a clean, stock arc
binutils, all I see are ".long HEX-VALUE" lines, which is what I would
expect.
The desired behaviour at this stage is that a binutils configured for
nps400 would appear to be an arc700 binutils, just with the additional
instruction included.
> In this
> situation, the disassembler may choose the first ones instead of
> yours. However, in this case, we need to add an option to the
> disassembler as well.
If this ever became a problem then I think the correct solution would
be a new ELF header flag, in the same way we split ARCv2 in to ARCEM
and ARCHS, we'd split ARC700 into ARC700 and NPS400. I'm hoping any
such flag changes can be put off until necessary.
>
> > +/* ARC NPS400 Support: See comment near head of file. */ static
> > +unsigned insert_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
> > + int value ATTRIBUTE_UNUSED,
> > + const char **errmsg ATTRIBUTE_UNUSED) {
> > + switch (value)
> > + {
> > + case 0:
> > + case 1:
> > + case 2:
> > + case 3:
> > + insn |= value << 24;
> > + break;
> > + case 12:
> > + case 13:
> > + case 14:
> > + case 15:
> > + insn |= (value - 8) << 24;
> > + break;
> > + default:
> > + *errmsg = _("Register must be either r0-r3 or r12-r15.");
> > + break;
> > + }
> > + return insn;
> > +}
> > +
> > +static int
> > +extract_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
> > + bfd_boolean * invalid ATTRIBUTE_UNUSED) {
> > + int value = (insn >> 24) & 0x07;
> > + if (value > 3)
> > + return (value + 8);
> > + else
> > + return value;
> > +}
> > +
> > +static unsigned
> > +insert_nps_j_dst (unsigned insn ATTRIBUTE_UNUSED,
> > + int value ATTRIBUTE_UNUSED,
> > + const char **errmsg ATTRIBUTE_UNUSED) {
> > + switch (value)
> > + {
> > + case 0:
> > + case 1:
> > + case 2:
> > + case 3:
> > + insn |= value << 24;
> > + break;
> > + case 12:
> > + case 13:
> > + case 14:
> > + case 15:
> > + insn |= (value - 8) << 24;
> > + break;
> > + default:
> > + *errmsg = _("Register must be either r0-r3 or r12-r15.");
> > + break;
> > + }
> > + return insn;
> > +}
> This function looks similar with insert_nps_dst(). Is not possible
> to use a single function only?
I'll try to get get more code reuse into here where possible. It
sounds like you're happy with the general approach, which is the main
thing :)
I'll post a revised patch set soon.
Thanks,
Andrew
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH] gas/opcodes: Add initial arc nps400 support
2016-03-01 15:15 ` Andrew Burgess
@ 2016-03-01 20:53 ` Claudiu Zissulescu
2016-03-02 19:37 ` Andrew Burgess
0 siblings, 1 reply; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-03-01 20:53 UTC (permalink / raw)
To: Andrew Burgess; +Cc: binutils, noamca, Cupertino.Miranda
Hi Andrew,
> So do you see the 'ARC_CPU_DEFAULT' being defined to 'ARC700' for the
> current stock arc binutils, and then set to 'NPS400' for the Mellanox
> NPS400 binutils?
No, more like arc700 or archs. The nps400 is an arc700 with some extra instructions. What I am trying to do is to have a piece of code that is generic and mps400 is only one of the possible configurations. But this discussion may be for another time.
> That leaves just a single use of ARC_NPS400 in the opcode library,
> where we include the extension instructions. One possibility would be
> that I could create a define call ARC_OPCODE_EXTENSION_INSN_FILE or
> some such. This would be undefined for core arc, and defined to
> "arc-nps400-tbl.h" for nps400, then in arc_opcodes[] we can say:
>
> #ifdef ARC_OPCODE_EXTENSION_INSN_FILE
> #include ARC_OPCODE_EXTENSION_INSN_FILE
> #endif
>
> Would that be better?
Looks nice. You need to think how to test the nsp400 without special actions, if possible.
> > Probably the best will be to make a file common for all other users
> > of ARC architecture which are having their own custom
> > instructions. Hence, I would propose to rename arc-nps400-tbl.h to
> > arc-ext-tbl.h or something of a sort.
>
> I'm not sure I like that idea. Keeping different extensions separate
> would be best I think.
>
> The total number of extensions is likely to be pretty low, but the
> number of entries in (this one at least) is likely to be ~100.
> Keeping them separate will help provide more structure to the code,
> making it more obvious which sets of extensions go together.
I see your point, I just want to avoid to have a separate file for each ARC custom configuration in the binutils (see my generality concern). Again, it is not a show stopper.
> > In this
> > situation, the disassembler may choose the first ones instead of
> > yours. However, in this case, we need to add an option to the
> > disassembler as well.
>
> If this ever became a problem then I think the correct solution would
> be a new ELF header flag, in the same way we split ARCv2 in to ARCEM
> and ARCHS, we'd split ARC700 into ARC700 and NPS400. I'm hoping any
> such flag changes can be put off until necessary.
Maybe the best is to have a section with all the relevant information in. However, as you show it, we are not in need of such extra addition to the toolchain.
Best,
Claudiu
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH] gas/opcodes: Add initial arc nps400 support
2016-03-01 20:53 ` Claudiu Zissulescu
@ 2016-03-02 19:37 ` Andrew Burgess
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
0 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-02 19:37 UTC (permalink / raw)
To: Claudiu Zissulescu; +Cc: binutils, noamca, Cupertino.Miranda
* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2016-03-01 20:53:25 +0000]:
> Hi Andrew,
>
> > So do you see the 'ARC_CPU_DEFAULT' being defined to 'ARC700' for the
> > current stock arc binutils, and then set to 'NPS400' for the Mellanox
> > NPS400 binutils?
>
> No, more like arc700 or archs. The nps400 is an arc700 with some
> extra instructions. What I am trying to do is to have a piece of
> code that is generic and mps400 is only one of the possible
> configurations. But this discussion may be for another time.
Given that you said in a previous mail to make the default for core
arc binutils be arc700, which suits nps400 fine, I think that this
change can be put off for another day. I already have a test in place
that ensures that nps400 gets arc700 as the default, so if/when the
rest of the arc binutils wants a different default, we can make the
above change then.
>
> > That leaves just a single use of ARC_NPS400 in the opcode library,
> > where we include the extension instructions. One possibility would be
> > that I could create a define call ARC_OPCODE_EXTENSION_INSN_FILE or
> > some such. This would be undefined for core arc, and defined to
> > "arc-nps400-tbl.h" for nps400, then in arc_opcodes[] we can say:
> >
> > #ifdef ARC_OPCODE_EXTENSION_INSN_FILE
> > #include ARC_OPCODE_EXTENSION_INSN_FILE
> > #endif
> >
> > Would that be better?
>
> Looks nice. You need to think how to test the nsp400 without
> special actions, if possible.
My intention is that testing nps400 would be done by configuring and
building the nps400 target. All the arc/nps400 tests will be guarded
so they don't run on core arc binutils, so we'll see no additional
test failures (if you do this is a mistake on my part, please let me
know).
>
> > > Probably the best will be to make a file common for all other users
> > > of ARC architecture which are having their own custom
> > > instructions. Hence, I would propose to rename arc-nps400-tbl.h to
> > > arc-ext-tbl.h or something of a sort.
> >
> > I'm not sure I like that idea. Keeping different extensions separate
> > would be best I think.
> >
> > The total number of extensions is likely to be pretty low, but the
> > number of entries in (this one at least) is likely to be ~100.
> > Keeping them separate will help provide more structure to the code,
> > making it more obvious which sets of extensions go together.
>
> I see your point, I just want to avoid to have a separate file for
> each ARC custom configuration in the binutils (see my generality
> concern). Again, it is not a show stopper.
I think that if there's a significant amount of code, which there will
be in this case, and it's logically separate from other, similar code,
then placing it in a separate file is probably best. I don't think we
should worry about too many files; if there really are that many arc
variants out there trying to get into binutils we can always move the
tables to support them into a sub-directory. As you say, this should
probably wait until it becomes an issue.
>
>
> > > In this
> > > situation, the disassembler may choose the first ones instead of
> > > yours. However, in this case, we need to add an option to the
> > > disassembler as well.
> >
> > If this ever became a problem then I think the correct solution would
> > be a new ELF header flag, in the same way we split ARCv2 in to ARCEM
> > and ARCHS, we'd split ARC700 into ARC700 and NPS400. I'm hoping any
> > such flag changes can be put off until necessary.
>
> Maybe the best is to have a section with all the relevant
> information in. However, as you show it, we are not in need of such
> extra addition to the toolchain.
OK, for now I'll not worry about this. We can address it later if
needed.
Thanks for the review. I'll roll a new version of the patch, and post
it soon.
Thanks,
Andrew
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv2 2/2] gas/opcodes: Add initial arc nps400 support
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
@ 2016-03-02 19:47 ` Andrew Burgess
2016-03-03 6:47 ` Claudiu Zissulescu
2016-03-15 13:20 ` Andreas Schwab
2016-03-02 19:47 ` [PATCHv2 1/2] arc/gas: default mach is arc700, initialised in md_begin Andrew Burgess
` (9 subsequent siblings)
10 siblings, 2 replies; 50+ messages in thread
From: Andrew Burgess @ 2016-03-02 19:47 UTC (permalink / raw)
To: binutils; +Cc: noamca, Claudiu.Zissulescu, Cupertino.Miranda, Andrew Burgess
The ARC NPS400 is an ARC700 with some additional instructions, created
by Mellanox (formally EZchip). This commit adds initial support for the
ARC NPS400 variant.
At this stage I have added only one new instruction, movb, this is to
allow a discussion of the correct approach for adding additional
instructions to the arc target. Additional instructions, and supporting
relocations will be added in future commits.
When binutils is configured for NPS400, by specifying 'mellanox' as the
vendor name in the target tuple, then the additional NPS400 instructions
are added into the ARC700 instruction set (within the opcodes library),
and in the assembler, the default architecture is changed to be ARC700.
There's a test for the new instruction, a test for the default
architecture, and one test needs updating slightly.
gas/ChangeLog:
* testsuite/gas/arc/nps400-0.d: New file.
* testsuite/gas/arc/nps400-0.s: New file.
* testsuite/gas/arc/nps400-1.d: New file.
* testsuite/gas/arc/nps400-1.s: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: New file.
* arc-opc.c: Add top level comment.
(insert_nps_dst): New function.
(extract_nps_dst): New function.
(extract_nps_dst_cl_z): New function.
(extract_nps_src1_in_dst): New function.
(insert_nps_src2): New function.
(extract_nps_src2): New function.
(insert_nps_bitop_size): New function.
(extract_nps_bitop_size): New function.
(arc_flag_operands): Add nps400 entries.
(arc_flag_classes): Add nps400 entries.
(arc_operands): Add nps400 entries.
(arc_opcodes): Add nps400 entries.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Setup extension instruction file for arc nps400.
---
gas/ChangeLog | 7 ++
gas/testsuite/gas/arc/nps400-0.d | 16 ++++
gas/testsuite/gas/arc/nps400-0.s | 2 +
gas/testsuite/gas/arc/nps400-1.d | 15 ++++
gas/testsuite/gas/arc/nps400-1.s | 7 ++
opcodes/ChangeLog | 20 +++++
opcodes/arc-nps400-tbl.h | 3 +
opcodes/arc-opc.c | 177 +++++++++++++++++++++++++++++++++++++++
opcodes/config.in | 3 +
opcodes/configure | 8 ++
opcodes/configure.ac | 6 ++
11 files changed, 264 insertions(+)
create mode 100644 gas/testsuite/gas/arc/nps400-0.d
create mode 100644 gas/testsuite/gas/arc/nps400-0.s
create mode 100644 gas/testsuite/gas/arc/nps400-1.d
create mode 100644 gas/testsuite/gas/arc/nps400-1.s
create mode 100644 opcodes/arc-nps400-tbl.h
diff --git a/gas/ChangeLog b/gas/ChangeLog
index d9975a6..dddb06f 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/gas/arc/nps400-0.d: New file.
+ * testsuite/gas/arc/nps400-0.s: New file.
+ * testsuite/gas/arc/nps400-1.d: New file.
+ * testsuite/gas/arc/nps400-1.s: New file.
+
2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_target): Delay initialisation until
diff --git a/gas/testsuite/gas/arc/nps400-0.d b/gas/testsuite/gas/arc/nps400-0.d
new file mode 100644
index 0000000..09e62b3
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.d
@@ -0,0 +1,16 @@
+#as:
+#target: arc*-mellanox-*
+#readelf: -h
+
+#...
+ Class: ELF32
+ Data: 2's complement, .* endian
+ Version: 1 \(current\)
+ OS/ABI: UNIX - System V
+ ABI Version: 0
+ Type: REL \(Relocatable file\)
+ Machine: ARCompact
+ Version: 0x1
+#...
+ Flags: 0x303, ARC 700, v3 no-legacy-syscalls ABI
+#...
\ No newline at end of file
diff --git a/gas/testsuite/gas/arc/nps400-0.s b/gas/testsuite/gas/arc/nps400-0.s
new file mode 100644
index 0000000..2b6cc1d
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.s
@@ -0,0 +1,2 @@
+ .text
+ nop
diff --git a/gas/testsuite/gas/arc/nps400-1.d b/gas/testsuite/gas/arc/nps400-1.d
new file mode 100644
index 0000000..bd68eb0
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.d
@@ -0,0 +1,15 @@
+#as: -mcpu=arc700
+#target: arc*-mellanox-*
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 4821 1485 movb r0,r0,r1,0x4,0x5,0x6
+ 4: 4881 1485 movb r0,r0,r12,0x4,0x5,0x6
+ 8: 4f81 1485 movb r15,r15,r12,0x4,0x5,0x6
+ c: 4821 9485 movb.cl r0,r1,0x4,0x5,0x6
+ 10: 48c1 9485 movb.cl r0,r14,0x4,0x5,0x6
+ 14: 4d21 9485 movb.cl r13,r1,0x4,0x5,0x6
diff --git a/gas/testsuite/gas/arc/nps400-1.s b/gas/testsuite/gas/arc/nps400-1.s
new file mode 100644
index 0000000..1d340b3
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.s
@@ -0,0 +1,7 @@
+ .text
+ movb r0, r0, r1, 4, 5, 6
+ movb r0, r0, r12, 4, 5, 6
+ movb r15, r15, r12, 4, 5, 6
+ movb.cl r0, r1, 4, 5, 6
+ movb.cl r0, r14, 4, 5, 6
+ movb.cl r13, r1, 4, 5, 6
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index eb2b61c..24b2940 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,23 @@
+2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: New file.
+ * arc-opc.c: Add top level comment.
+ (insert_nps_dst): New function.
+ (extract_nps_dst): New function.
+ (extract_nps_dst_cl_z): New function.
+ (extract_nps_src1_in_dst): New function.
+ (insert_nps_src2): New function.
+ (extract_nps_src2): New function.
+ (insert_nps_bitop_size): New function.
+ (extract_nps_bitop_size): New function.
+ (arc_flag_operands): Add nps400 entries.
+ (arc_flag_classes): Add nps400 entries.
+ (arc_operands): Add nps400 entries.
+ (arc_opcodes): Add nps400 entries.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+ * configure.ac: Setup extension instruction file for arc nps400.
+
2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
* arc-opc.c (BASE): Delete.
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
new file mode 100644
index 0000000..8347e68
--- /dev/null
+++ b/opcodes/arc-nps400-tbl.h
@@ -0,0 +1,3 @@
+/* movb<.f><.cl> */
+{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, { NPS_R_DST, NPS_R_SRC1_IN_DST, NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, { NPS_R_DST_CL_Z, NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index a4fdaff..a745fc1 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -26,6 +26,12 @@
#include "opintl.h"
#include "libiberty.h"
+/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
+ instructions. Support for this target is available when binutils is
+ configured and built for the 'arc*-mellanox-*-*' target. As far as
+ possible all ARC NPS400 features are built into all ARC target builds as
+ this reduces the chances that regressions might creep in. */
+
/* Insert RB register into a 32-bit opcode. */
static unsigned
insert_rb (unsigned insn,
@@ -637,6 +643,136 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
return value;
}
+/* ARC NPS400 Support: See comment near head of file. */
+static unsigned
+insert_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 24;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 24;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static int
+extract_nps_dst_cl_z (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value;
+
+ /* If the CL flag is not set then this is invalid. */
+ if (((insn >> 15) & 0x1) == 0)
+ *invalid = TRUE;
+ value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static int
+extract_nps_src1_in_dst (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value;
+
+ /* If the CL flag is set then this is invalid. */
+ if (((insn >> 15) & 0x1) == 0x1)
+ *invalid = TRUE;
+ value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 21;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 21;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 21) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value < 1 || value > 32)
+ {
+ *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
+ return insn;
+ }
+
+ --value;
+ insn |= ((value & 0x1f) << 10);
+ return insn;
+}
+
+static int
+extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 10) & 0x1f) + 1;
+}
+
/* Include the generic extract/insert functions. Order is important
as some of the functions present in the .h may be disabled via
defines. */
@@ -792,6 +928,13 @@ const struct arc_flag_operand arc_flag_operands[] =
/* Fake Flags. */
#define F_NE (F_H17 + 1)
{ "ne", 0, 0, 0, 1 },
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define F_NPS_CL (F_NE + 1)
+ { "cl", 1, 1, 15, 1 },
+
+#define F_NPS_FLAG (F_NPS_CL + 1)
+ { "f", 1, 1, 20, 1 },
};
const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
@@ -862,6 +1005,13 @@ const struct arc_flag_class arc_flag_classes[] =
#define C_NE (C_AS + 1)
{ CND, { F_NE, F_NULL}},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define C_NPS_CL (C_NE + 1)
+ { FLG, { F_NPS_CL, F_NULL}},
+
+#define C_NPS_F (C_NPS_CL + 1)
+ { FLG, { F_NPS_FLAG, F_NULL}},
};
/* The operands table.
@@ -1180,6 +1330,29 @@ const struct arc_operand arc_operands[] =
/* UIMM6_5_S mask = 0000011111100000. */
#define UIMM6_5_S (W6 + 1)
{6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define NPS_R_DST (UIMM6_5_S + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_dst },
+
+#define NPS_R_DST_CL_Z (NPS_R_DST + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_dst_cl_z },
+
+#define NPS_R_SRC1_IN_DST (NPS_R_DST_CL_Z + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_src1_in_dst },
+
+#define NPS_R_SRC2 (NPS_R_SRC1_IN_DST + 1)
+ { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_src2, extract_nps_src2 },
+
+ /* Next 3 operands are integer immediate for bitops. */
+#define NPS_BITOP_DST_POS (NPS_R_SRC2 + 1)
+ { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
+ { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
@@ -1195,6 +1368,10 @@ const unsigned arc_NToperand = FKT_NT;
const struct arc_opcode arc_opcodes[] =
{
#include "arc-tbl.h"
+
+#ifdef ARC_OPCODE_EXTENSION_INSN_FILE
+#include ARC_OPCODE_EXTENSION_INSN_FILE
+#endif /* ARC_OPCODE_EXTENSION_INSN_FILE */
};
const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
diff --git a/opcodes/config.in b/opcodes/config.in
index 55a80fd..174bfb4 100644
--- a/opcodes/config.in
+++ b/opcodes/config.in
@@ -7,6 +7,9 @@
#endif
#define __CONFIG_H__ 1
+/* ARC extension instructions. */
+#undef ARC_OPCODE_EXTENSION_INSN_FILE
+
/* Define to 1 if translation of program messages to the user's native
language is requested. */
#undef ENABLE_NLS
diff --git a/opcodes/configure b/opcodes/configure
index 75c6573..78d4a59 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12505,6 +12505,14 @@ fi
# target-specific stuff:
+case ${target} in
+ arc*-mellanox-*)
+
+$as_echo "#define ARC_OPCODE_EXTENSION_INSN_FILE \"arc-nps400-tbl.h\"" >>confdefs.h
+
+ ;;
+esac
+
# Canonicalize the secondary target names.
if test -n "$enable_targets" ; then
for targ in `echo $enable_targets | sed 's/,/ /g'`
diff --git a/opcodes/configure.ac b/opcodes/configure.ac
index c7f4783..05b55ca 100644
--- a/opcodes/configure.ac
+++ b/opcodes/configure.ac
@@ -210,6 +210,12 @@ AC_SUBST(SHARED_DEPENDENCIES)
# target-specific stuff:
+case ${target} in
+ arc*-mellanox-*)
+ AC_DEFINE(ARC_OPCODE_EXTENSION_INSN_FILE, "arc-nps400-tbl.h", [ARC extension instructions.])
+ ;;
+esac
+
# Canonicalize the secondary target names.
if test -n "$enable_targets" ; then
for targ in `echo $enable_targets | sed 's/,/ /g'`
--
2.6.4
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv2 1/2] arc/gas: default mach is arc700, initialised in md_begin
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
2016-03-02 19:47 ` [PATCHv2 2/2] gas/opcodes: " Andrew Burgess
@ 2016-03-02 19:47 ` Andrew Burgess
2016-03-03 6:44 ` Claudiu Zissulescu
2016-03-05 21:24 ` Andrew Burgess
2016-03-11 20:13 ` PING: Re: [PATCHv2 0/2] Add initial arc nps400 support Andrew Burgess
` (8 subsequent siblings)
10 siblings, 2 replies; 50+ messages in thread
From: Andrew Burgess @ 2016-03-02 19:47 UTC (permalink / raw)
To: binutils; +Cc: noamca, Claudiu.Zissulescu, Cupertino.Miranda, Andrew Burgess
This commit restructures the selection of the default cpu/mach so that
the choice is made from md_begin (if the user has not provided a command
line choice). This will reduce the amount of change needed in a later
patch.
At the request of Synopsys, the default architecture changes to ARC700
from this commit, previously the default was a non-existent
super-architecture that contained all instructions from all arc
variants. There's some clean up associated with removing the default
merged architecture, and a small test fix now that the default is
ARC700.
binutils/ChangeLog:
* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
to the architecture list.
gas/ChangeLog:
* config/tc-arc.c (arc_target): Delay initialisation until
arc_select_cpu.
(arc_target_name): Likewise.
(arc_features): Likewise.
(arc_mach_type): Likewise.
(cpu_types): Remove "all" entry.
(arc_select_cpu): New function, most of the content is from...
(md_parse_option): ... here. Call new arc_select_cpu.
(md_begin): Call arc_select_cpu if needed, default is now arc700.
include/ChangeLog:
* opcode/arc.h (ARC_OPCODE_BASE): Delete.
opcodes/ChangeLog:
* arc-opc.c (BASE): Delete.
---
binutils/ChangeLog | 5 ++
binutils/testsuite/binutils-all/objdump.exp | 2 +-
gas/ChangeLog | 12 ++++
gas/config/tc-arc.c | 85 +++++++++++++++--------------
include/ChangeLog | 4 ++
include/opcode/arc.h | 5 --
opcodes/ChangeLog | 4 ++
opcodes/arc-opc.c | 3 -
8 files changed, 69 insertions(+), 51 deletions(-)
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 56c8adc..b4750ef 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
+ to the architecture list.
+
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
PR ld/19645
diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp
index 22c4686..3573037 100644
--- a/binutils/testsuite/binutils-all/objdump.exp
+++ b/binutils/testsuite/binutils-all/objdump.exp
@@ -34,7 +34,7 @@ send_user "Version [binutil_version $OBJDUMP]"
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
-lappend cpus_expected aarch64 alpha arc ARCv2 arm cris
+lappend cpus_expected aarch64 alpha arc ARC700 ARCv2 arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3b79ccb..d9975a6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-arc.c (arc_target): Delay initialisation until
+ arc_select_cpu.
+ (arc_target_name): Likewise.
+ (arc_features): Likewise.
+ (arc_mach_type): Likewise.
+ (cpu_types): Remove "all" entry.
+ (arc_select_cpu): New function, most of the content is from...
+ (md_parse_option): ... here. Call new arc_select_cpu.
+ (md_begin): Call arc_select_cpu if needed, default is now arc700.
+
2016-03-02 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/x86_64-intel.d: Adjusted for COFF.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index e509fec..b83d928 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -311,12 +311,12 @@ static void assemble_insn
const struct arc_flags *, int, struct arc_insn *);
/* The cpu for which we are generating code. */
-static unsigned arc_target = ARC_OPCODE_BASE;
-static const char *arc_target_name = "<all>";
-static unsigned arc_features = 0x00;
+static unsigned arc_target;
+static const char *arc_target_name;
+static unsigned arc_features;
/* The default architecture. */
-static int arc_mach_type = bfd_mach_arc_arcv2;
+static int arc_mach_type;
/* Non-zero if the cpu type has been explicitly specified. */
static int mach_type_specified_p = 0;
@@ -346,8 +346,6 @@ static const struct cpu_type
EF_ARC_CPU_ARCV2EM, ARC_CD},
{ "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
EF_ARC_CPU_ARCV2HS, ARC_CD},
- { "all", ARC_OPCODE_BASE, bfd_mach_arc_arcv2,
- 0x00, 0x00 },
{ 0, 0, 0, 0, 0 }
};
@@ -569,6 +567,40 @@ md_number_to_chars_midend (char *buf, valueT val, int n)
}
}
+/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
+ the relevant static global variables. */
+
+static void
+arc_select_cpu (const char *arg)
+{
+ int cpu_flags = EF_ARC_CPU_GENERIC;
+ int i;
+ char *dst, *cpu = alloca (strlen (arg) + 1);
+ const char *src;
+
+ for (dst = cpu, src = arg; *src != '\0'; ++dst, ++src)
+ *dst = TOLOWER (*src);
+
+ for (i = 0; cpu_types[i].name; ++i)
+ {
+ if (!strcmp (cpu_types[i].name, cpu))
+ {
+ arc_target = cpu_types[i].flags;
+ arc_target_name = cpu_types[i].name;
+ arc_features = cpu_types[i].features;
+ arc_mach_type = cpu_types[i].mach;
+ cpu_flags = cpu_types[i].eflags;
+ break;
+ }
+ }
+
+ if (!cpu_types[i].name)
+ as_fatal (_("unknown architecture: %s\n"), arg);
+
+ if (cpu_flags != EF_ARC_CPU_GENERIC)
+ arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+}
+
/* Here ends all the ARCompact extension instruction assembling
stuff. */
@@ -2088,6 +2120,9 @@ md_begin (void)
{
unsigned int i;
+ if (!mach_type_specified_p)
+ arc_select_cpu ("arc700");
+
/* The endianness can be chosen "at the factory". */
target_big_endian = byte_order == BIG_ENDIAN;
@@ -2874,8 +2909,6 @@ arc_parse_name (const char *name,
int
md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
{
- int cpu_flags = EF_ARC_CPU_GENERIC;
-
switch (c)
{
case OPTION_ARC600:
@@ -2893,37 +2926,8 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
case OPTION_MCPU:
{
- int i;
- char *s = alloca (strlen (arg) + 1);
-
- {
- char *t = s;
- char *arg1 = arg;
-
- do
- *t = TOLOWER (*arg1++);
- while (*t++);
- }
-
- for (i = 0; cpu_types[i].name; ++i)
- {
- if (!strcmp (cpu_types[i].name, s))
- {
- arc_target = cpu_types[i].flags;
- arc_target_name = cpu_types[i].name;
- arc_features = cpu_types[i].features;
- arc_mach_type = cpu_types[i].mach;
- cpu_flags = cpu_types[i].eflags;
-
- mach_type_specified_p = 1;
- break;
- }
- }
-
- if (!cpu_types[i].name)
- {
- as_fatal (_("unknown architecture: %s\n"), arg);
- }
+ arc_select_cpu (arg);
+ mach_type_specified_p = 1;
break;
}
@@ -2977,9 +2981,6 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
return 0;
}
- if (cpu_flags != EF_ARC_CPU_GENERIC)
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
-
return 1;
}
diff --git a/include/ChangeLog b/include/ChangeLog
index 97bba8b..dcefe91 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * opcode/arc.h (ARC_OPCODE_BASE): Delete.
+
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
PR ld/19645
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 6f5bc98..d33b878 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -171,11 +171,6 @@ extern const unsigned arc_num_opcodes;
#define ARC_XMAC 0x1000
#define ARC_CRC 0x1000
-/* Base architecture -- all cpus. */
-#define ARC_OPCODE_BASE \
- (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
-
/* A macro to check for short instructions. */
#define ARC_SHORT(mask) \
(((mask) & 0xFFFF0000) ? 0 : 1)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f2a9c26..eb2b61c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (BASE): Delete.
+
2016-03-02 Alan Modra <amodra@gmail.com>
* or1k-desc.h: Regenerate.
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 9a674d5..a4fdaff 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -642,9 +642,6 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
defines. */
#include "arc-fxi.h"
-/* Abbreviations for instruction subsets. */
-#define BASE ARC_OPCODE_BASE
-
/* The flag operands table.
The format of the table is
--
2.6.4
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv2 0/2] Add initial arc nps400 support
2016-03-02 19:37 ` Andrew Burgess
@ 2016-03-02 19:47 ` Andrew Burgess
2016-03-02 19:47 ` [PATCHv2 2/2] gas/opcodes: " Andrew Burgess
` (10 more replies)
0 siblings, 11 replies; 50+ messages in thread
From: Andrew Burgess @ 2016-03-02 19:47 UTC (permalink / raw)
To: binutils; +Cc: noamca, Claudiu.Zissulescu, Cupertino.Miranda, Andrew Burgess
This is the revised patch series for adding initial arc nps400 support.
The original thread can be found here:
https://sourceware.org/ml/binutils/2016-02/msg00406.html
The first patch is not really related to nps400, but is a small
restructure within the assembler, and makes arc700 the default arc
architecture. This change was recomended by Claudiu in this mail:
https://sourceware.org/ml/binutils/2016-02/msg00435.html
The second patch is then an update of the original nps400 patch, with
revisions based on feedback.
OK to apply?
--
Andrew Burgess (2):
arc/gas: default mach is arc700, initialised in md_begin
gas/opcodes: Add initial arc nps400 support
binutils/ChangeLog | 5 +
binutils/testsuite/binutils-all/objdump.exp | 2 +-
gas/ChangeLog | 19 +++
gas/config/tc-arc.c | 85 ++++++-------
gas/testsuite/gas/arc/nps400-0.d | 16 +++
gas/testsuite/gas/arc/nps400-0.s | 2 +
gas/testsuite/gas/arc/nps400-1.d | 15 +++
gas/testsuite/gas/arc/nps400-1.s | 7 ++
include/ChangeLog | 4 +
include/opcode/arc.h | 5 -
opcodes/ChangeLog | 24 ++++
opcodes/arc-nps400-tbl.h | 3 +
opcodes/arc-opc.c | 180 +++++++++++++++++++++++++++-
opcodes/config.in | 3 +
opcodes/configure | 8 ++
opcodes/configure.ac | 6 +
16 files changed, 333 insertions(+), 51 deletions(-)
create mode 100644 gas/testsuite/gas/arc/nps400-0.d
create mode 100644 gas/testsuite/gas/arc/nps400-0.s
create mode 100644 gas/testsuite/gas/arc/nps400-1.d
create mode 100644 gas/testsuite/gas/arc/nps400-1.s
create mode 100644 opcodes/arc-nps400-tbl.h
--
2.6.4
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCHv2 1/2] arc/gas: default mach is arc700, initialised in md_begin
2016-03-02 19:47 ` [PATCHv2 1/2] arc/gas: default mach is arc700, initialised in md_begin Andrew Burgess
@ 2016-03-03 6:44 ` Claudiu Zissulescu
2016-03-05 21:24 ` Andrew Burgess
1 sibling, 0 replies; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-03-03 6:44 UTC (permalink / raw)
To: Andrew Burgess, binutils; +Cc: noamca, Cupertino.Miranda
Hi Andrew,
This patch looks ok to me.
//Claudiu
________________________________________
From: Andrew Burgess [andrew.burgess@embecosm.com]
Sent: Wednesday, March 02, 2016 8:47 PM
To: binutils@sourceware.org
Cc: noamca@mellanox.com; Claudiu.Zissulescu@synopsys.com; Cupertino.Miranda@synopsys.com; Andrew Burgess
Subject: [PATCHv2 1/2] arc/gas: default mach is arc700, initialised in md_begin
This commit restructures the selection of the default cpu/mach so that
the choice is made from md_begin (if the user has not provided a command
line choice). This will reduce the amount of change needed in a later
patch.
At the request of Synopsys, the default architecture changes to ARC700
from this commit, previously the default was a non-existent
super-architecture that contained all instructions from all arc
variants. There's some clean up associated with removing the default
merged architecture, and a small test fix now that the default is
ARC700.
binutils/ChangeLog:
* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
to the architecture list.
gas/ChangeLog:
* config/tc-arc.c (arc_target): Delay initialisation until
arc_select_cpu.
(arc_target_name): Likewise.
(arc_features): Likewise.
(arc_mach_type): Likewise.
(cpu_types): Remove "all" entry.
(arc_select_cpu): New function, most of the content is from...
(md_parse_option): ... here. Call new arc_select_cpu.
(md_begin): Call arc_select_cpu if needed, default is now arc700.
include/ChangeLog:
* opcode/arc.h (ARC_OPCODE_BASE): Delete.
opcodes/ChangeLog:
* arc-opc.c (BASE): Delete.
---
binutils/ChangeLog | 5 ++
binutils/testsuite/binutils-all/objdump.exp | 2 +-
gas/ChangeLog | 12 ++++
gas/config/tc-arc.c | 85 +++++++++++++++--------------
include/ChangeLog | 4 ++
include/opcode/arc.h | 5 --
opcodes/ChangeLog | 4 ++
opcodes/arc-opc.c | 3 -
8 files changed, 69 insertions(+), 51 deletions(-)
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 56c8adc..b4750ef 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
+ to the architecture list.
+
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
PR ld/19645
diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp
index 22c4686..3573037 100644
--- a/binutils/testsuite/binutils-all/objdump.exp
+++ b/binutils/testsuite/binutils-all/objdump.exp
@@ -34,7 +34,7 @@ send_user "Version [binutil_version $OBJDUMP]"
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
-lappend cpus_expected aarch64 alpha arc ARCv2 arm cris
+lappend cpus_expected aarch64 alpha arc ARC700 ARCv2 arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3b79ccb..d9975a6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-arc.c (arc_target): Delay initialisation until
+ arc_select_cpu.
+ (arc_target_name): Likewise.
+ (arc_features): Likewise.
+ (arc_mach_type): Likewise.
+ (cpu_types): Remove "all" entry.
+ (arc_select_cpu): New function, most of the content is from...
+ (md_parse_option): ... here. Call new arc_select_cpu.
+ (md_begin): Call arc_select_cpu if needed, default is now arc700.
+
2016-03-02 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/x86_64-intel.d: Adjusted for COFF.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index e509fec..b83d928 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -311,12 +311,12 @@ static void assemble_insn
const struct arc_flags *, int, struct arc_insn *);
/* The cpu for which we are generating code. */
-static unsigned arc_target = ARC_OPCODE_BASE;
-static const char *arc_target_name = "<all>";
-static unsigned arc_features = 0x00;
+static unsigned arc_target;
+static const char *arc_target_name;
+static unsigned arc_features;
/* The default architecture. */
-static int arc_mach_type = bfd_mach_arc_arcv2;
+static int arc_mach_type;
/* Non-zero if the cpu type has been explicitly specified. */
static int mach_type_specified_p = 0;
@@ -346,8 +346,6 @@ static const struct cpu_type
EF_ARC_CPU_ARCV2EM, ARC_CD},
{ "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
EF_ARC_CPU_ARCV2HS, ARC_CD},
- { "all", ARC_OPCODE_BASE, bfd_mach_arc_arcv2,
- 0x00, 0x00 },
{ 0, 0, 0, 0, 0 }
};
@@ -569,6 +567,40 @@ md_number_to_chars_midend (char *buf, valueT val, int n)
}
}
+/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
+ the relevant static global variables. */
+
+static void
+arc_select_cpu (const char *arg)
+{
+ int cpu_flags = EF_ARC_CPU_GENERIC;
+ int i;
+ char *dst, *cpu = alloca (strlen (arg) + 1);
+ const char *src;
+
+ for (dst = cpu, src = arg; *src != '\0'; ++dst, ++src)
+ *dst = TOLOWER (*src);
+
+ for (i = 0; cpu_types[i].name; ++i)
+ {
+ if (!strcmp (cpu_types[i].name, cpu))
+ {
+ arc_target = cpu_types[i].flags;
+ arc_target_name = cpu_types[i].name;
+ arc_features = cpu_types[i].features;
+ arc_mach_type = cpu_types[i].mach;
+ cpu_flags = cpu_types[i].eflags;
+ break;
+ }
+ }
+
+ if (!cpu_types[i].name)
+ as_fatal (_("unknown architecture: %s\n"), arg);
+
+ if (cpu_flags != EF_ARC_CPU_GENERIC)
+ arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+}
+
/* Here ends all the ARCompact extension instruction assembling
stuff. */
@@ -2088,6 +2120,9 @@ md_begin (void)
{
unsigned int i;
+ if (!mach_type_specified_p)
+ arc_select_cpu ("arc700");
+
/* The endianness can be chosen "at the factory". */
target_big_endian = byte_order == BIG_ENDIAN;
@@ -2874,8 +2909,6 @@ arc_parse_name (const char *name,
int
md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
{
- int cpu_flags = EF_ARC_CPU_GENERIC;
-
switch (c)
{
case OPTION_ARC600:
@@ -2893,37 +2926,8 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
case OPTION_MCPU:
{
- int i;
- char *s = alloca (strlen (arg) + 1);
-
- {
- char *t = s;
- char *arg1 = arg;
-
- do
- *t = TOLOWER (*arg1++);
- while (*t++);
- }
-
- for (i = 0; cpu_types[i].name; ++i)
- {
- if (!strcmp (cpu_types[i].name, s))
- {
- arc_target = cpu_types[i].flags;
- arc_target_name = cpu_types[i].name;
- arc_features = cpu_types[i].features;
- arc_mach_type = cpu_types[i].mach;
- cpu_flags = cpu_types[i].eflags;
-
- mach_type_specified_p = 1;
- break;
- }
- }
-
- if (!cpu_types[i].name)
- {
- as_fatal (_("unknown architecture: %s\n"), arg);
- }
+ arc_select_cpu (arg);
+ mach_type_specified_p = 1;
break;
}
@@ -2977,9 +2981,6 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
return 0;
}
- if (cpu_flags != EF_ARC_CPU_GENERIC)
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
-
return 1;
}
diff --git a/include/ChangeLog b/include/ChangeLog
index 97bba8b..dcefe91 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * opcode/arc.h (ARC_OPCODE_BASE): Delete.
+
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
PR ld/19645
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 6f5bc98..d33b878 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -171,11 +171,6 @@ extern const unsigned arc_num_opcodes;
#define ARC_XMAC 0x1000
#define ARC_CRC 0x1000
-/* Base architecture -- all cpus. */
-#define ARC_OPCODE_BASE \
- (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
-
/* A macro to check for short instructions. */
#define ARC_SHORT(mask) \
(((mask) & 0xFFFF0000) ? 0 : 1)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f2a9c26..eb2b61c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (BASE): Delete.
+
2016-03-02 Alan Modra <amodra@gmail.com>
* or1k-desc.h: Regenerate.
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 9a674d5..a4fdaff 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -642,9 +642,6 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
defines. */
#include "arc-fxi.h"
-/* Abbreviations for instruction subsets. */
-#define BASE ARC_OPCODE_BASE
-
/* The flag operands table.
The format of the table is
--
2.6.4
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCHv2 2/2] gas/opcodes: Add initial arc nps400 support
2016-03-02 19:47 ` [PATCHv2 2/2] gas/opcodes: " Andrew Burgess
@ 2016-03-03 6:47 ` Claudiu Zissulescu
2016-03-15 13:20 ` Andreas Schwab
1 sibling, 0 replies; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-03-03 6:47 UTC (permalink / raw)
To: Andrew Burgess, binutils; +Cc: noamca, Cupertino.Miranda
It looks ok to me as well,
Claudiu
________________________________________
From: Andrew Burgess [andrew.burgess@embecosm.com]
Sent: Wednesday, March 02, 2016 8:47 PM
To: binutils@sourceware.org
Cc: noamca@mellanox.com; Claudiu.Zissulescu@synopsys.com; Cupertino.Miranda@synopsys.com; Andrew Burgess
Subject: [PATCHv2 2/2] gas/opcodes: Add initial arc nps400 support
The ARC NPS400 is an ARC700 with some additional instructions, created
by Mellanox (formally EZchip). This commit adds initial support for the
ARC NPS400 variant.
At this stage I have added only one new instruction, movb, this is to
allow a discussion of the correct approach for adding additional
instructions to the arc target. Additional instructions, and supporting
relocations will be added in future commits.
When binutils is configured for NPS400, by specifying 'mellanox' as the
vendor name in the target tuple, then the additional NPS400 instructions
are added into the ARC700 instruction set (within the opcodes library),
and in the assembler, the default architecture is changed to be ARC700.
There's a test for the new instruction, a test for the default
architecture, and one test needs updating slightly.
gas/ChangeLog:
* testsuite/gas/arc/nps400-0.d: New file.
* testsuite/gas/arc/nps400-0.s: New file.
* testsuite/gas/arc/nps400-1.d: New file.
* testsuite/gas/arc/nps400-1.s: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: New file.
* arc-opc.c: Add top level comment.
(insert_nps_dst): New function.
(extract_nps_dst): New function.
(extract_nps_dst_cl_z): New function.
(extract_nps_src1_in_dst): New function.
(insert_nps_src2): New function.
(extract_nps_src2): New function.
(insert_nps_bitop_size): New function.
(extract_nps_bitop_size): New function.
(arc_flag_operands): Add nps400 entries.
(arc_flag_classes): Add nps400 entries.
(arc_operands): Add nps400 entries.
(arc_opcodes): Add nps400 entries.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Setup extension instruction file for arc nps400.
---
gas/ChangeLog | 7 ++
gas/testsuite/gas/arc/nps400-0.d | 16 ++++
gas/testsuite/gas/arc/nps400-0.s | 2 +
gas/testsuite/gas/arc/nps400-1.d | 15 ++++
gas/testsuite/gas/arc/nps400-1.s | 7 ++
opcodes/ChangeLog | 20 +++++
opcodes/arc-nps400-tbl.h | 3 +
opcodes/arc-opc.c | 177 +++++++++++++++++++++++++++++++++++++++
opcodes/config.in | 3 +
opcodes/configure | 8 ++
opcodes/configure.ac | 6 ++
11 files changed, 264 insertions(+)
create mode 100644 gas/testsuite/gas/arc/nps400-0.d
create mode 100644 gas/testsuite/gas/arc/nps400-0.s
create mode 100644 gas/testsuite/gas/arc/nps400-1.d
create mode 100644 gas/testsuite/gas/arc/nps400-1.s
create mode 100644 opcodes/arc-nps400-tbl.h
diff --git a/gas/ChangeLog b/gas/ChangeLog
index d9975a6..dddb06f 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/gas/arc/nps400-0.d: New file.
+ * testsuite/gas/arc/nps400-0.s: New file.
+ * testsuite/gas/arc/nps400-1.d: New file.
+ * testsuite/gas/arc/nps400-1.s: New file.
+
2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-arc.c (arc_target): Delay initialisation until
diff --git a/gas/testsuite/gas/arc/nps400-0.d b/gas/testsuite/gas/arc/nps400-0.d
new file mode 100644
index 0000000..09e62b3
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.d
@@ -0,0 +1,16 @@
+#as:
+#target: arc*-mellanox-*
+#readelf: -h
+
+#...
+ Class: ELF32
+ Data: 2's complement, .* endian
+ Version: 1 \(current\)
+ OS/ABI: UNIX - System V
+ ABI Version: 0
+ Type: REL \(Relocatable file\)
+ Machine: ARCompact
+ Version: 0x1
+#...
+ Flags: 0x303, ARC 700, v3 no-legacy-syscalls ABI
+#...
\ No newline at end of file
diff --git a/gas/testsuite/gas/arc/nps400-0.s b/gas/testsuite/gas/arc/nps400-0.s
new file mode 100644
index 0000000..2b6cc1d
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.s
@@ -0,0 +1,2 @@
+ .text
+ nop
diff --git a/gas/testsuite/gas/arc/nps400-1.d b/gas/testsuite/gas/arc/nps400-1.d
new file mode 100644
index 0000000..bd68eb0
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.d
@@ -0,0 +1,15 @@
+#as: -mcpu=arc700
+#target: arc*-mellanox-*
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 4821 1485 movb r0,r0,r1,0x4,0x5,0x6
+ 4: 4881 1485 movb r0,r0,r12,0x4,0x5,0x6
+ 8: 4f81 1485 movb r15,r15,r12,0x4,0x5,0x6
+ c: 4821 9485 movb.cl r0,r1,0x4,0x5,0x6
+ 10: 48c1 9485 movb.cl r0,r14,0x4,0x5,0x6
+ 14: 4d21 9485 movb.cl r13,r1,0x4,0x5,0x6
diff --git a/gas/testsuite/gas/arc/nps400-1.s b/gas/testsuite/gas/arc/nps400-1.s
new file mode 100644
index 0000000..1d340b3
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.s
@@ -0,0 +1,7 @@
+ .text
+ movb r0, r0, r1, 4, 5, 6
+ movb r0, r0, r12, 4, 5, 6
+ movb r15, r15, r12, 4, 5, 6
+ movb.cl r0, r1, 4, 5, 6
+ movb.cl r0, r14, 4, 5, 6
+ movb.cl r13, r1, 4, 5, 6
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index eb2b61c..24b2940 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,23 @@
+2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: New file.
+ * arc-opc.c: Add top level comment.
+ (insert_nps_dst): New function.
+ (extract_nps_dst): New function.
+ (extract_nps_dst_cl_z): New function.
+ (extract_nps_src1_in_dst): New function.
+ (insert_nps_src2): New function.
+ (extract_nps_src2): New function.
+ (insert_nps_bitop_size): New function.
+ (extract_nps_bitop_size): New function.
+ (arc_flag_operands): Add nps400 entries.
+ (arc_flag_classes): Add nps400 entries.
+ (arc_operands): Add nps400 entries.
+ (arc_opcodes): Add nps400 entries.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+ * configure.ac: Setup extension instruction file for arc nps400.
+
2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
* arc-opc.c (BASE): Delete.
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
new file mode 100644
index 0000000..8347e68
--- /dev/null
+++ b/opcodes/arc-nps400-tbl.h
@@ -0,0 +1,3 @@
+/* movb<.f><.cl> */
+{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, { NPS_R_DST, NPS_R_SRC1_IN_DST, NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, { NPS_R_DST_CL_Z, NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index a4fdaff..a745fc1 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -26,6 +26,12 @@
#include "opintl.h"
#include "libiberty.h"
+/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
+ instructions. Support for this target is available when binutils is
+ configured and built for the 'arc*-mellanox-*-*' target. As far as
+ possible all ARC NPS400 features are built into all ARC target builds as
+ this reduces the chances that regressions might creep in. */
+
/* Insert RB register into a 32-bit opcode. */
static unsigned
insert_rb (unsigned insn,
@@ -637,6 +643,136 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
return value;
}
+/* ARC NPS400 Support: See comment near head of file. */
+static unsigned
+insert_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 24;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 24;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static int
+extract_nps_dst_cl_z (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value;
+
+ /* If the CL flag is not set then this is invalid. */
+ if (((insn >> 15) & 0x1) == 0)
+ *invalid = TRUE;
+ value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static int
+extract_nps_src1_in_dst (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value;
+
+ /* If the CL flag is set then this is invalid. */
+ if (((insn >> 15) & 0x1) == 0x1)
+ *invalid = TRUE;
+ value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 21;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 21;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 21) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value < 1 || value > 32)
+ {
+ *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
+ return insn;
+ }
+
+ --value;
+ insn |= ((value & 0x1f) << 10);
+ return insn;
+}
+
+static int
+extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 10) & 0x1f) + 1;
+}
+
/* Include the generic extract/insert functions. Order is important
as some of the functions present in the .h may be disabled via
defines. */
@@ -792,6 +928,13 @@ const struct arc_flag_operand arc_flag_operands[] =
/* Fake Flags. */
#define F_NE (F_H17 + 1)
{ "ne", 0, 0, 0, 1 },
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define F_NPS_CL (F_NE + 1)
+ { "cl", 1, 1, 15, 1 },
+
+#define F_NPS_FLAG (F_NPS_CL + 1)
+ { "f", 1, 1, 20, 1 },
};
const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
@@ -862,6 +1005,13 @@ const struct arc_flag_class arc_flag_classes[] =
#define C_NE (C_AS + 1)
{ CND, { F_NE, F_NULL}},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define C_NPS_CL (C_NE + 1)
+ { FLG, { F_NPS_CL, F_NULL}},
+
+#define C_NPS_F (C_NPS_CL + 1)
+ { FLG, { F_NPS_FLAG, F_NULL}},
};
/* The operands table.
@@ -1180,6 +1330,29 @@ const struct arc_operand arc_operands[] =
/* UIMM6_5_S mask = 0000011111100000. */
#define UIMM6_5_S (W6 + 1)
{6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define NPS_R_DST (UIMM6_5_S + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_dst },
+
+#define NPS_R_DST_CL_Z (NPS_R_DST + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_dst_cl_z },
+
+#define NPS_R_SRC1_IN_DST (NPS_R_DST_CL_Z + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_src1_in_dst },
+
+#define NPS_R_SRC2 (NPS_R_SRC1_IN_DST + 1)
+ { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_src2, extract_nps_src2 },
+
+ /* Next 3 operands are integer immediate for bitops. */
+#define NPS_BITOP_DST_POS (NPS_R_SRC2 + 1)
+ { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
+ { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
@@ -1195,6 +1368,10 @@ const unsigned arc_NToperand = FKT_NT;
const struct arc_opcode arc_opcodes[] =
{
#include "arc-tbl.h"
+
+#ifdef ARC_OPCODE_EXTENSION_INSN_FILE
+#include ARC_OPCODE_EXTENSION_INSN_FILE
+#endif /* ARC_OPCODE_EXTENSION_INSN_FILE */
};
const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
diff --git a/opcodes/config.in b/opcodes/config.in
index 55a80fd..174bfb4 100644
--- a/opcodes/config.in
+++ b/opcodes/config.in
@@ -7,6 +7,9 @@
#endif
#define __CONFIG_H__ 1
+/* ARC extension instructions. */
+#undef ARC_OPCODE_EXTENSION_INSN_FILE
+
/* Define to 1 if translation of program messages to the user's native
language is requested. */
#undef ENABLE_NLS
diff --git a/opcodes/configure b/opcodes/configure
index 75c6573..78d4a59 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12505,6 +12505,14 @@ fi
# target-specific stuff:
+case ${target} in
+ arc*-mellanox-*)
+
+$as_echo "#define ARC_OPCODE_EXTENSION_INSN_FILE \"arc-nps400-tbl.h\"" >>confdefs.h
+
+ ;;
+esac
+
# Canonicalize the secondary target names.
if test -n "$enable_targets" ; then
for targ in `echo $enable_targets | sed 's/,/ /g'`
diff --git a/opcodes/configure.ac b/opcodes/configure.ac
index c7f4783..05b55ca 100644
--- a/opcodes/configure.ac
+++ b/opcodes/configure.ac
@@ -210,6 +210,12 @@ AC_SUBST(SHARED_DEPENDENCIES)
# target-specific stuff:
+case ${target} in
+ arc*-mellanox-*)
+ AC_DEFINE(ARC_OPCODE_EXTENSION_INSN_FILE, "arc-nps400-tbl.h", [ARC extension instructions.])
+ ;;
+esac
+
# Canonicalize the secondary target names.
if test -n "$enable_targets" ; then
for targ in `echo $enable_targets | sed 's/,/ /g'`
--
2.6.4
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv2 1/2] arc/gas: default mach is arc700, initialised in md_begin
2016-03-02 19:47 ` [PATCHv2 1/2] arc/gas: default mach is arc700, initialised in md_begin Andrew Burgess
2016-03-03 6:44 ` Claudiu Zissulescu
@ 2016-03-05 21:24 ` Andrew Burgess
1 sibling, 0 replies; 50+ messages in thread
From: Andrew Burgess @ 2016-03-05 21:24 UTC (permalink / raw)
To: binutils; +Cc: noamca, Claudiu.Zissulescu, Cupertino.Miranda
After a little further testing on this branch it turns out I
introduced a bug in the content I moved from md_parse_option to
arc_select_cpu.
After a little thought, I realised that the whole allocating of a
temporary string was unneeded, and we can instead just use strcasecmp
(which is already being used in tc-arc.c).
Here's a new version of the patch, basically the same except that
arc_select_cpu is now a little simpler.
Thanks,
Andrew
---
This commit restructures the selection of the default cpu/mach so that
the choice is made from md_begin (if the user has not provided a command
line choice). This will reduce the amount of change needed in a later
patch.
At the request of Synopsys, the default architecture changes to ARC700
from this commit, previously the default was a non-existent
super-architecture that contained all instructions from all arc
variants. There's some clean up associated with removing the default
merged architecture, and a small test fix now that the default is
ARC700.
binutils/ChangeLog:
* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
to the architecture list.
gas/ChangeLog:
* config/tc-arc.c (arc_target): Delay initialisation until
arc_select_cpu.
(arc_target_name): Likewise.
(arc_features): Likewise.
(arc_mach_type): Likewise.
(cpu_types): Remove "all" entry.
(arc_select_cpu): New function, most of the content is from...
(md_parse_option): ... here. Call new arc_select_cpu.
(md_begin): Call arc_select_cpu if needed, default is now arc700.
include/ChangeLog:
* opcode/arc.h (ARC_OPCODE_BASE): Delete.
opcodes/ChangeLog:
* arc-opc.c (BASE): Delete.
---
binutils/ChangeLog | 5 ++
binutils/testsuite/binutils-all/objdump.exp | 2 +-
gas/ChangeLog | 12 +++++
gas/config/tc-arc.c | 80 ++++++++++++++---------------
include/ChangeLog | 4 ++
include/opcode/arc.h | 5 --
opcodes/ChangeLog | 4 ++
opcodes/arc-opc.c | 3 --
8 files changed, 64 insertions(+), 51 deletions(-)
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 56c8adc..b4750ef 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
+ to the architecture list.
+
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
PR ld/19645
diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp
index 22c4686..3573037 100644
--- a/binutils/testsuite/binutils-all/objdump.exp
+++ b/binutils/testsuite/binutils-all/objdump.exp
@@ -34,7 +34,7 @@ send_user "Version [binutil_version $OBJDUMP]"
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
-lappend cpus_expected aarch64 alpha arc ARCv2 arm cris
+lappend cpus_expected aarch64 alpha arc ARC700 ARCv2 arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4a075bb..141f8c8 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-arc.c (arc_target): Delay initialisation until
+ arc_select_cpu.
+ (arc_target_name): Likewise.
+ (arc_features): Likewise.
+ (arc_mach_type): Likewise.
+ (cpu_types): Remove "all" entry.
+ (arc_select_cpu): New function, most of the content is from...
+ (md_parse_option): ... here. Call new arc_select_cpu.
+ (md_begin): Call arc_select_cpu if needed, default is now arc700.
+
2016-02-29 Cupertino Miranda <cmiranda@synopsys.com>
Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index e509fec..b11dd64 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -311,12 +311,12 @@ static void assemble_insn
const struct arc_flags *, int, struct arc_insn *);
/* The cpu for which we are generating code. */
-static unsigned arc_target = ARC_OPCODE_BASE;
-static const char *arc_target_name = "<all>";
-static unsigned arc_features = 0x00;
+static unsigned arc_target;
+static const char *arc_target_name;
+static unsigned arc_features;
/* The default architecture. */
-static int arc_mach_type = bfd_mach_arc_arcv2;
+static int arc_mach_type;
/* Non-zero if the cpu type has been explicitly specified. */
static int mach_type_specified_p = 0;
@@ -346,8 +346,6 @@ static const struct cpu_type
EF_ARC_CPU_ARCV2EM, ARC_CD},
{ "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
EF_ARC_CPU_ARCV2HS, ARC_CD},
- { "all", ARC_OPCODE_BASE, bfd_mach_arc_arcv2,
- 0x00, 0x00 },
{ 0, 0, 0, 0, 0 }
};
@@ -569,6 +567,35 @@ md_number_to_chars_midend (char *buf, valueT val, int n)
}
}
+/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
+ the relevant static global variables. */
+
+static void
+arc_select_cpu (const char *arg)
+{
+ int cpu_flags = EF_ARC_CPU_GENERIC;
+ int i;
+
+ for (i = 0; cpu_types[i].name; ++i)
+ {
+ if (!strcasecmp (cpu_types[i].name, arg))
+ {
+ arc_target = cpu_types[i].flags;
+ arc_target_name = cpu_types[i].name;
+ arc_features = cpu_types[i].features;
+ arc_mach_type = cpu_types[i].mach;
+ cpu_flags = cpu_types[i].eflags;
+ break;
+ }
+ }
+
+ if (!cpu_types[i].name)
+ as_fatal (_("unknown architecture: %s\n"), arg);
+
+ if (cpu_flags != EF_ARC_CPU_GENERIC)
+ arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+}
+
/* Here ends all the ARCompact extension instruction assembling
stuff. */
@@ -2088,6 +2115,9 @@ md_begin (void)
{
unsigned int i;
+ if (!mach_type_specified_p)
+ arc_select_cpu ("arc700");
+
/* The endianness can be chosen "at the factory". */
target_big_endian = byte_order == BIG_ENDIAN;
@@ -2874,8 +2904,6 @@ arc_parse_name (const char *name,
int
md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
{
- int cpu_flags = EF_ARC_CPU_GENERIC;
-
switch (c)
{
case OPTION_ARC600:
@@ -2893,37 +2921,8 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
case OPTION_MCPU:
{
- int i;
- char *s = alloca (strlen (arg) + 1);
-
- {
- char *t = s;
- char *arg1 = arg;
-
- do
- *t = TOLOWER (*arg1++);
- while (*t++);
- }
-
- for (i = 0; cpu_types[i].name; ++i)
- {
- if (!strcmp (cpu_types[i].name, s))
- {
- arc_target = cpu_types[i].flags;
- arc_target_name = cpu_types[i].name;
- arc_features = cpu_types[i].features;
- arc_mach_type = cpu_types[i].mach;
- cpu_flags = cpu_types[i].eflags;
-
- mach_type_specified_p = 1;
- break;
- }
- }
-
- if (!cpu_types[i].name)
- {
- as_fatal (_("unknown architecture: %s\n"), arg);
- }
+ arc_select_cpu (arg);
+ mach_type_specified_p = 1;
break;
}
@@ -2977,9 +2976,6 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
return 0;
}
- if (cpu_flags != EF_ARC_CPU_GENERIC)
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
-
return 1;
}
diff --git a/include/ChangeLog b/include/ChangeLog
index 97bba8b..dcefe91 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * opcode/arc.h (ARC_OPCODE_BASE): Delete.
+
2016-02-26 H.J. Lu <hongjiu.lu@intel.com>
PR ld/19645
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 6f5bc98..d33b878 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -171,11 +171,6 @@ extern const unsigned arc_num_opcodes;
#define ARC_XMAC 0x1000
#define ARC_CRC 0x1000
-/* Base architecture -- all cpus. */
-#define ARC_OPCODE_BASE \
- (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
-
/* A macro to check for short instructions. */
#define ARC_SHORT(mask) \
(((mask) & 0xFFFF0000) ? 0 : 1)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0a78719..fe466f3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2016-03-01 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (BASE): Delete.
+
2016-03-01 Nick Clifton <nickc@redhat.com>
PR target/19747
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 9a674d5..a4fdaff 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -642,9 +642,6 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
defines. */
#include "arc-fxi.h"
-/* Abbreviations for instruction subsets. */
-#define BASE ARC_OPCODE_BASE
-
/* The flag operands table.
The format of the table is
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* PING: Re: [PATCHv2 0/2] Add initial arc nps400 support
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
2016-03-02 19:47 ` [PATCHv2 2/2] gas/opcodes: " Andrew Burgess
2016-03-02 19:47 ` [PATCHv2 1/2] arc/gas: default mach is arc700, initialised in md_begin Andrew Burgess
@ 2016-03-11 20:13 ` Andrew Burgess
2016-03-15 11:14 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 3/7] arc: Remove duplicated constant in include/elf/arc.h Andrew Burgess
` (7 subsequent siblings)
10 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-11 20:13 UTC (permalink / raw)
To: binutils; +Cc: noamca, Claudiu.Zissulescu, Cupertino.Miranda
* Andrew Burgess <andrew.burgess@embecosm.com> [2016-03-02 19:47:34 +0000]:
> This is the revised patch series for adding initial arc nps400
> support.
PING! I've had some great feedback from Claudiu, but I'm still hoping
for a global maintainer to cast an eye over this too please.
Thanks,
Andrew
>
> The original thread can be found here:
>
> https://sourceware.org/ml/binutils/2016-02/msg00406.html
>
> The first patch is not really related to nps400, but is a small
> restructure within the assembler, and makes arc700 the default arc
> architecture. This change was recomended by Claudiu in this mail:
>
> https://sourceware.org/ml/binutils/2016-02/msg00435.html
>
> The second patch is then an update of the original nps400 patch, with
> revisions based on feedback.
>
> OK to apply?
>
> --
>
> Andrew Burgess (2):
> arc/gas: default mach is arc700, initialised in md_begin
> gas/opcodes: Add initial arc nps400 support
>
> binutils/ChangeLog | 5 +
> binutils/testsuite/binutils-all/objdump.exp | 2 +-
> gas/ChangeLog | 19 +++
> gas/config/tc-arc.c | 85 ++++++-------
> gas/testsuite/gas/arc/nps400-0.d | 16 +++
> gas/testsuite/gas/arc/nps400-0.s | 2 +
> gas/testsuite/gas/arc/nps400-1.d | 15 +++
> gas/testsuite/gas/arc/nps400-1.s | 7 ++
> include/ChangeLog | 4 +
> include/opcode/arc.h | 5 -
> opcodes/ChangeLog | 24 ++++
> opcodes/arc-nps400-tbl.h | 3 +
> opcodes/arc-opc.c | 180 +++++++++++++++++++++++++++-
> opcodes/config.in | 3 +
> opcodes/configure | 8 ++
> opcodes/configure.ac | 6 +
> 16 files changed, 333 insertions(+), 51 deletions(-)
> create mode 100644 gas/testsuite/gas/arc/nps400-0.d
> create mode 100644 gas/testsuite/gas/arc/nps400-0.s
> create mode 100644 gas/testsuite/gas/arc/nps400-1.d
> create mode 100644 gas/testsuite/gas/arc/nps400-1.s
> create mode 100644 opcodes/arc-nps400-tbl.h
>
> --
> 2.6.4
>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: PING: Re: [PATCHv2 0/2] Add initial arc nps400 support
2016-03-11 20:13 ` PING: Re: [PATCHv2 0/2] Add initial arc nps400 support Andrew Burgess
@ 2016-03-15 11:14 ` Nick Clifton
2016-03-15 11:38 ` Andrew Burgess
0 siblings, 1 reply; 50+ messages in thread
From: Nick Clifton @ 2016-03-15 11:14 UTC (permalink / raw)
To: Andrew Burgess, binutils; +Cc: noamca, Claudiu.Zissulescu, Cupertino.Miranda
Hi Andrew,
> PING! I've had some great feedback from Claudiu, but I'm still hoping
> for a global maintainer to cast an eye over this too please.
Oops - sorry - dropped the ball on this one.
The patches (1 and 2) both look fine to me, apart from one very small issue:
The new assembler test control files (gas/testsuite/gas/arc/nps400-0.d and
gas/testsuite/gas/arc/nps400-1.d) both restrict the test to:
#target: arc*-mellanox-*
What is "mellanox" and why is it included in the target string ? The name
is not present in the gas/configure.tgt or bfd/config.bfd files, so I am
assuming that it is a manufacturer name and not an OS name. If so then its
presence in these tests will stop them from being run with toolchains
configured with, for example, --target=arc-elf. (This matters to me, since
that is one of the configurations I use in my daily regression testing).
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: PING: Re: [PATCHv2 0/2] Add initial arc nps400 support
2016-03-15 11:14 ` Nick Clifton
@ 2016-03-15 11:38 ` Andrew Burgess
2016-03-15 12:48 ` Nick Clifton
0 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 11:38 UTC (permalink / raw)
To: Nick Clifton; +Cc: binutils, noamca, Claudiu.Zissulescu, Cupertino.Miranda
* Nick Clifton <nickc@redhat.com> [2016-03-15 11:14:44 +0000]:
> Hi Andrew,
>
> > PING! I've had some great feedback from Claudiu, but I'm still hoping
> > for a global maintainer to cast an eye over this too please.
>
> Oops - sorry - dropped the ball on this one.
No problem. Thanks for the review.
> The patches (1 and 2) both look fine to me, apart from one very small issue:
> The new assembler test control files (gas/testsuite/gas/arc/nps400-0.d and
> gas/testsuite/gas/arc/nps400-1.d) both restrict the test to:
>
> #target: arc*-mellanox-*
>
> What is "mellanox" and why is it included in the target string ? The name
> is not present in the gas/configure.tgt or bfd/config.bfd files, so I am
> assuming that it is a manufacturer name and not an OS name. If so then its
> presence in these tests will stop them from being run with toolchains
> configured with, for example, --target=arc-elf. (This matters to me, since
> that is one of the configurations I use in my daily regression
> testing).
Patch #2 adds this name to the opcodes/configure script. I
deliberately tried to minimise the number of configure scripts I
changed.
The mellanox nps400 core is an ARC700 with a set of vendor extension
instructions added into the gap that is left in the ARC700
architecture specifically for such instructions.
So, at the moment, when we configure with arc*-mellanox-* in the
opcodes directory we build the standard arc opcodes library, but
include an additional set of instructions that sit in the gap.
Everything else (right now) bfd/gas/etc is unchanged.
In the future this might not be the case, for bfd/ld I do have some
small patches to submit, but they can wait for another day. I'm
hopeful that gas might not require any mellanox specific changes
though.
With this new knowledge, are the patches still OK?
Thanks,
Andrew
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: PING: Re: [PATCHv2 0/2] Add initial arc nps400 support
2016-03-15 11:38 ` Andrew Burgess
@ 2016-03-15 12:48 ` Nick Clifton
2016-03-15 13:41 ` Andrew Burgess
0 siblings, 1 reply; 50+ messages in thread
From: Nick Clifton @ 2016-03-15 12:48 UTC (permalink / raw)
To: Andrew Burgess; +Cc: binutils, noamca, Claudiu.Zissulescu, Cupertino.Miranda
Hi Andrew,
>> #target: arc*-mellanox-*
>>
>> What is "mellanox"
> Patch #2 adds this name to the opcodes/configure script. I
> deliberately tried to minimise the number of configure scripts I
> changed.
Would it be possible to use an underscore rather than a hyphen for the
mellenox extension ? Ie:
arc_mellanox-*
No other CPU name includes a hyphen character, and this character is
traditionally used to separate the three fields of a target configuration.
(See the top level config.sub file for more information on this).
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv2 2/2] gas/opcodes: Add initial arc nps400 support
2016-03-02 19:47 ` [PATCHv2 2/2] gas/opcodes: " Andrew Burgess
2016-03-03 6:47 ` Claudiu Zissulescu
@ 2016-03-15 13:20 ` Andreas Schwab
2016-03-15 13:50 ` Andrew Burgess
1 sibling, 1 reply; 50+ messages in thread
From: Andreas Schwab @ 2016-03-15 13:20 UTC (permalink / raw)
To: Andrew Burgess; +Cc: binutils, noamca, Claudiu.Zissulescu, Cupertino.Miranda
Andrew Burgess <andrew.burgess@embecosm.com> writes:
> When binutils is configured for NPS400, by specifying 'mellanox' as the
> vendor name in the target tuple, then the additional NPS400 instructions
The vendor name should never be used for target selection.
Andreas.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: PING: Re: [PATCHv2 0/2] Add initial arc nps400 support
2016-03-15 12:48 ` Nick Clifton
@ 2016-03-15 13:41 ` Andrew Burgess
2016-03-15 15:46 ` Nick Clifton
0 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 13:41 UTC (permalink / raw)
To: Nick Clifton; +Cc: binutils, noamca, Claudiu.Zissulescu, Cupertino.Miranda
* Nick Clifton <nickc@redhat.com> [2016-03-15 12:48:48 +0000]:
> Hi Andrew,
>
> >> #target: arc*-mellanox-*
> >>
> >> What is "mellanox"
>
> > Patch #2 adds this name to the opcodes/configure script. I
> > deliberately tried to minimise the number of configure scripts I
> > changed.
>
> Would it be possible to use an underscore rather than a hyphen for the
> mellenox extension ? Ie:
>
> arc_mellanox-*
>
> No other CPU name includes a hyphen character, and this character is
> traditionally used to separate the three fields of a target configuration.
> (See the top level config.sub file for more information on this).
Maybe I'm miss-understanding the target triplet system. My intention was
that mellanox was a vendor name, which I thought got its own space
within the triplet. This page, for example, led me to think this:
https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.69/html_node/Specifying-Target-Triplets.html
though as this page also says, cpu-vendor-os, can also become
cpu-vendor-kernel-system.
For arc it's possible to configure for both little-endian and
big-endian toolchains, with the default being little-endian, while the
mellanox system is most commonly big-endian but can also be configured
little-endian, so for configuration, I normally use:
--target=arceb-mellanox-linux-uclibc
though the -linux-uclibc part is really about GCC and makes no
difference to binutils, I suspect -elf would be fine too (I _think_
I've tried that).
[ It's worth noting though that parts of binutils are broken for
big-endian arc. I posted and merged a patch recently that fixed the
assembler, as that's where I'm currently working for mellanox, and I
plan to fix the linker soon. ]
So, mellanox is definitely not the cpu name, the cpu name is nps400,
but as it's an arc700 with extension instructions to support their SoC
I would rather not create a whole new cpu type. If I did then I'd end
up having to patch a lot of configure scripts, plus a lot of test
files.
If I'm not understanding the purpose of the vendor field in the target
triplet, please can you help me understand. After reading all I can
find, I still think arc-mellanox-* is the right fit.
Thanks,
Andrew
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv2 2/2] gas/opcodes: Add initial arc nps400 support
2016-03-15 13:20 ` Andreas Schwab
@ 2016-03-15 13:50 ` Andrew Burgess
2016-03-15 14:05 ` Andreas Schwab
0 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 13:50 UTC (permalink / raw)
To: Andreas Schwab; +Cc: binutils, noamca, Claudiu.Zissulescu, Cupertino.Miranda
* Andreas Schwab <schwab@suse.de> [2016-03-15 14:20:13 +0100]:
> Andrew Burgess <andrew.burgess@embecosm.com> writes:
>
> > When binutils is configured for NPS400, by specifying 'mellanox' as the
> > vendor name in the target tuple, then the additional NPS400 instructions
>
> The vendor name should never be used for target selection.
Hi Andreas,
Thanks for taking the time to provide feedback on this patch.
Do you think you could expand on the above sentence please. I think
this is probably the same issue that Nick is referring to in a
different mail, but it is not clear.
What precisely do you mean by "target selection", the target, as I
understood it, was the string that included the vendor name. Do you
mean that the vendor name should never be used to modify the behaviour
of the program being configured?
A follow on to the above then, and please forgive me if this seems
obvious, what is the vendor name for? Why have it in the target
triplet if it can't modify program behaviour?
And finally, what would your recommended route forward be? Is it to
create a new cpu type, and just to share the configuration routine
with arc? And update all arc specific tests to also apply to the new
cpu type?
Again, thanks taking the time to provide this feedback.
Thanks,
Andrew
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv2 2/2] gas/opcodes: Add initial arc nps400 support
2016-03-15 13:50 ` Andrew Burgess
@ 2016-03-15 14:05 ` Andreas Schwab
2016-03-15 15:53 ` Nick Clifton
0 siblings, 1 reply; 50+ messages in thread
From: Andreas Schwab @ 2016-03-15 14:05 UTC (permalink / raw)
To: Andrew Burgess; +Cc: binutils, noamca, Claudiu.Zissulescu, Cupertino.Miranda
Andrew Burgess <andrew.burgess@embecosm.com> writes:
> And finally, what would your recommended route forward be? Is it to
> create a new cpu type, and just to share the configuration routine
> with arc? And update all arc specific tests to also apply to the new
> cpu type?
The custom insns should always be supported, controlled by an -m option.
Andreas.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: PING: Re: [PATCHv2 0/2] Add initial arc nps400 support
2016-03-15 13:41 ` Andrew Burgess
@ 2016-03-15 15:46 ` Nick Clifton
0 siblings, 0 replies; 50+ messages in thread
From: Nick Clifton @ 2016-03-15 15:46 UTC (permalink / raw)
To: Andrew Burgess; +Cc: binutils, noamca, Claudiu.Zissulescu, Cupertino.Miranda
Hi Andrew,
> If I'm not understanding the purpose of the vendor field in the target
> triplet, please can you help me understand. After reading all I can
> find, I still think arc-mellanox-* is the right fit.
You are understanding it correctly. It is just that it is unusual, but not
unheard-of, for the vendor field to play a role in selecting how a target is
configured.
So please go ahead and commit the patch.
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv2 2/2] gas/opcodes: Add initial arc nps400 support
2016-03-15 14:05 ` Andreas Schwab
@ 2016-03-15 15:53 ` Nick Clifton
0 siblings, 0 replies; 50+ messages in thread
From: Nick Clifton @ 2016-03-15 15:53 UTC (permalink / raw)
To: Andrew Burgess
Cc: Andreas Schwab, binutils, noamca, Claudiu.Zissulescu, Cupertino.Miranda
Hi Andrew,
On 15/03/16 14:04, Andreas Schwab wrote:
> The custom insns should always be supported, controlled by an -m option.
Exactly - this is the point that I was trying to get at. (But failing spectacularly
due to my fuddled brain). Supporting extra instructions should be an option
(to the assembler and disassembler), and possibly protected by a flag bit somewhere
(eg the ELF header) in order to avoid mixing nps400 object files with non nps400
object files.
I know that I have just posted an approval of your patch, but I would much rather
that you did not follow up on that, and instead looked at the possibility of handling
the extension as indicated above.
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv3 6/7] arc/opcodes: Use flag operand class to handle multiple flag matches
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
` (7 preceding siblings ...)
2016-03-15 23:02 ` [PATCHv3 0/7] Add initial arc nps400 support Andrew Burgess
@ 2016-03-15 23:02 ` Andrew Burgess
2016-03-16 11:51 ` Claudiu Zissulescu
2016-03-18 10:00 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag Andrew Burgess
2016-03-15 23:02 ` [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant Andrew Burgess
10 siblings, 2 replies; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 23:02 UTC (permalink / raw)
To: binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab, Andrew Burgess
When parsing the operand instruction flags we don't currently detect the
case where multiple flags are provided from the same class set, these
will be accepted and the bit values merged together, resulting in the
wrong instruction being assembled. For example:
adc.n.eq r0,r0,r2
Will assemble without error, yet, upon disassembly, the instruction will
actually be:
adc.c r0,r0,r2
In a later commit the concept of required flags will be introduced.
Required flags are just like normal instruction flags, except that they
must be present for the instruction to match. Adding this will allow
for simpler instructions in the instruction table, and allow for more
sharing of operand extraction and insertion functions.
To solve both of the above issues (multiple flags being invalid, and
required flags), this commit reworks the flag class mechanism.
Currently the flag class is never used. Each instruction can reference
multiple flag classes, each flag class has a class type and a set of
flags. However, at present, the class type is never used. The current
values identify the type of instruction that the flag will be used in,
but this is not required information.
Instead, this commit discards the old flag classes, and introduces 3 new
classes. The first F_CLASS_NONE, is just a NULL marker value, and is
only used in the NULL marker flag class. The other two flag classes are
F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.
The class F_FLAG_OPTIONAL has the property that at most one of the flags
in the flag set for that class must be present in the instruction. The
"at most" one means that no flags being present is fine.
The class F_FLAG_REQUIRED is not currently used, but will be soon. With
this class, exactly one of the flags from this class must be present in
the instruction. If the flag class contains a single flag, then of
course that flag must be present. However, if the flag class contained
two or more, then one, and only one of them must be present.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
declarations to start of block. Reset code on all flags before
attempting to match them. Handle multiple hits on the same flag.
Handle flag class.
* testsuite/gas/arc/asm-errors.d: New file.
* testsuite/gas/arc/asm-errors.err: New file.
* testsuite/gas/arc/asm-errors.s: New file.
include/ChangeLog:
* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
new classes instead.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_classes): Convert all flag classes to use
the new class enum values.
---
gas/ChangeLog | 10 +++++++
gas/config/tc-arc.c | 22 +++++++++++-----
gas/testsuite/gas/arc/asm-errors.d | 2 ++
gas/testsuite/gas/arc/asm-errors.err | 4 +++
gas/testsuite/gas/arc/asm-errors.s | 4 +++
include/ChangeLog | 5 ++++
include/opcode/arc.h | 18 ++++++-------
opcodes/ChangeLog | 5 ++++
opcodes/arc-opc.c | 51 ++++++++++++++++++------------------
9 files changed, 81 insertions(+), 40 deletions(-)
create mode 100644 gas/testsuite/gas/arc/asm-errors.d
create mode 100644 gas/testsuite/gas/arc/asm-errors.err
create mode 100644 gas/testsuite/gas/arc/asm-errors.s
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8df40e9..71f7ec0 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,15 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * config/tc-arc.c (find_opcode_match): Move lnflg, and i
+ declarations to start of block. Reset code on all flags before
+ attempting to match them. Handle multiple hits on the same flag.
+ Handle flag class.
+ * testsuite/gas/arc/asm-errors.d: New file.
+ * testsuite/gas/arc/asm-errors.err: New file.
+ * testsuite/gas/arc/asm-errors.s: New file.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* config/tc-arc.c (cpu_types): Add nps400 entry.
(check_zol): Handle nps400.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 2bf7f13..736143e 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -1370,7 +1370,7 @@ find_opcode_match (const struct arc_opcode *first_opcode,
{
const unsigned char *opidx;
const unsigned char *flgidx;
- int tokidx = 0;
+ int tokidx = 0, lnflg, i;
const expressionS *t = &emptyE;
pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
@@ -1596,20 +1596,23 @@ find_opcode_match (const struct arc_opcode *first_opcode,
}
pr_debug ("opr ");
- /* Check the flags. Iterate over the valid flag classes. */
- int lnflg = nflgs;
+ /* Setup ready for flag parsing. */
+ lnflg = nflgs;
+ for (i = 0; i < nflgs; i++)
+ first_pflag [i].code = 0;
- for (flgidx = opcode->flags; *flgidx && lnflg; ++flgidx)
+ /* Check the flags. Iterate over the valid flag classes. */
+ for (flgidx = opcode->flags; *flgidx; ++flgidx)
{
/* Get a valid flag class. */
const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
const unsigned *flgopridx;
+ int cl_matches = 0;
for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
{
const struct arc_flag_operand *flg_operand;
struct arc_flags *pflag = first_pflag;
- int i;
flg_operand = &arc_flag_operands[*flgopridx];
for (i = 0; i < nflgs; i++, pflag++)
@@ -1617,13 +1620,20 @@ find_opcode_match (const struct arc_opcode *first_opcode,
/* Match against the parsed flags. */
if (!strcmp (flg_operand->name, pflag->name))
{
- /*TODO: Check if it is duplicated. */
+ if (pflag->code != 0)
+ goto match_failed;
+ cl_matches++;
pflag->code = *flgopridx;
lnflg--;
break; /* goto next flag class and parsed flag. */
}
}
}
+
+ if (cl_flags->class == F_CLASS_REQUIRED && cl_matches == 0)
+ goto match_failed;
+ if (cl_flags->class == F_CLASS_OPTIONAL && cl_matches > 1)
+ goto match_failed;
}
/* Did I check all the parsed flags? */
if (lnflg)
diff --git a/gas/testsuite/gas/arc/asm-errors.d b/gas/testsuite/gas/arc/asm-errors.d
new file mode 100644
index 0000000..9255a27
--- /dev/null
+++ b/gas/testsuite/gas/arc/asm-errors.d
@@ -0,0 +1,2 @@
+#as: -mcpu=arc700
+#error-output: asm-errors.err
diff --git a/gas/testsuite/gas/arc/asm-errors.err b/gas/testsuite/gas/arc/asm-errors.err
new file mode 100644
index 0000000..35390fc
--- /dev/null
+++ b/gas/testsuite/gas/arc/asm-errors.err
@@ -0,0 +1,4 @@
+[^:]*: Assembler messages:
+[^:]*:2: Error: inappropriate arguments for opcode 'adc'
+[^:]*:3: Error: inappropriate arguments for opcode 'adc'
+[^:]*:4: Error: inappropriate arguments for opcode 'adc'
diff --git a/gas/testsuite/gas/arc/asm-errors.s b/gas/testsuite/gas/arc/asm-errors.s
new file mode 100644
index 0000000..6e0fd6a
--- /dev/null
+++ b/gas/testsuite/gas/arc/asm-errors.s
@@ -0,0 +1,4 @@
+ .text
+ adc.al.ra r0,r0,r2
+ adc.eq.eq r0,r0,r2
+ adc.n.eq r0,r0,r2
diff --git a/include/ChangeLog b/include/ChangeLog
index d531748..7742efa 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
+ new classes instead.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* elf/arc.h (E_ARC_MACH_NPS400): Define.
* opcode/arc.h (ARC_OPCODE_NPS400): Define.
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 85ea735..3310c10 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -72,15 +72,15 @@ typedef enum
/* Flags class. */
typedef enum
{
- FNONE,
- CND, /* Conditional flags. */
- WBM, /* Write-back modes. */
- FLG, /* F Flag. */
- SBP, /* Static branch prediction. */
- DLY, /* Delay slot. */
- DIF, /* Bypass caches. */
- SGX, /* Sign extend modes. */
- SZM /* Data size modes. */
+ F_CLASS_NONE,
+
+ /* At most one flag from the set of flags can appear in the
+ instruction. */
+ F_CLASS_OPTIONAL,
+
+ /* Exactly one from from the set of flags must appear in the
+ instruction. */
+ F_CLASS_REQUIRED,
} flag_class_t;
/* The opcode table is an array of struct arc_opcode. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f9c5f77..f590a43 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * arc-opc.c (arc_flag_classes): Convert all flag classes to use
+ the new class enum values.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* arc-dis.c (print_insn_arc): Handle nps400.
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index a4fdaff..f126fa8 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -803,65 +803,66 @@ const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
const struct arc_flag_class arc_flag_classes[] =
{
#define C_EMPTY 0
- { FNONE, { F_NULL } },
+ { F_CLASS_NONE, { F_NULL } },
#define C_CC (C_EMPTY + 1)
- { CND, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO,
- F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET,
- F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET,
- F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
- F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
+ F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
+ F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
+ F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
+ F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
#define C_AA_ADDR3 (C_CC + 1)
#define C_AA27 (C_CC + 1)
- { WBM, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
#define C_AA21 (C_AA_ADDR3 + 1)
- { WBM, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
#define C_AA8 (C_AA_ADDR9 + 1)
- { WBM, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
#define C_F (C_AA_ADDR22 + 1)
- { FLG, { F_FLAG, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
#define C_FHARD (C_F + 1)
- { FLG, { F_FFAKE, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
#define C_T (C_FHARD + 1)
- { SBP, { F_NT, F_T, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
#define C_D (C_T + 1)
- { DLY, { F_ND, F_D, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
#define C_DHARD (C_D + 1)
- { DLY, { F_DFAKE, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
#define C_DI20 (C_DHARD + 1)
- { DIF, { F_DI11, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
#define C_DI16 (C_DI20 + 1)
- { DIF, { F_DI15, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
#define C_DI26 (C_DI16 + 1)
- { DIF, { F_DI5, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
#define C_X25 (C_DI26 + 1)
- { SGX, { F_SIGN6, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
#define C_X15 (C_X25 + 1)
- { SGX, { F_SIGN16, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
#define C_XHARD (C_X15 + 1)
#define C_X (C_X15 + 1)
- { SGX, { F_SIGNX, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
#define C_ZZ13 (C_X + 1)
- { SZM, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
#define C_ZZ23 (C_ZZ13 + 1)
- { SZM, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
#define C_ZZ29 (C_ZZ23 + 1)
- { SZM, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
#define C_AS (C_ZZ29 + 1)
- { SZM, { F_ASFAKE, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
#define C_NE (C_AS + 1)
- { CND, { F_NE, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
};
/* The operands table.
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv3 7/7] arc/nps400: Add first nps400 instructions
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
` (3 preceding siblings ...)
2016-03-15 23:02 ` [PATCHv3 3/7] arc: Remove duplicated constant in include/elf/arc.h Andrew Burgess
@ 2016-03-15 23:02 ` Andrew Burgess
2016-03-18 10:01 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 2/7] arc/gas: default mach is arc700, initialised in md_begin Andrew Burgess
` (5 subsequent siblings)
10 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 23:02 UTC (permalink / raw)
To: binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab, Andrew Burgess
Adds the first few nps400 instructions.
gas/ChangeLog:
* testsuite/gas/arc/nps400-0.d: New file.
* testsuite/gas/arc/nps400-0.s: New file.
* testsuite/gas/arc/nps400-1.d: New file.
* testsuite/gas/arc/nps400-1.s: New file.
include/ChangeLog:
* opcodes/arc.h (insn_class_t): Add BITOP type.
opcodes/ChangeLog:
* arc-nps400-tbl.h: New file.
* arc-opc.c: Add top level comment.
(insert_nps_3bit_dst): New function.
(extract_nps_3bit_dst): New function.
(insert_nps_3bit_src2): New function.
(extract_nps_3bit_src2): New function.
(insert_nps_bitop_size): New function.
(extract_nps_bitop_size): New function.
(arc_flag_operands): Add nps400 entries.
(arc_flag_classes): Add nps400 entries.
(arc_operands): Add nps400 entries.
(arc_opcodes): Add nps400 include.
---
gas/ChangeLog | 7 ++
gas/testsuite/gas/arc/nps400-0.d | 15 ++++
gas/testsuite/gas/arc/nps400-0.s | 2 +
gas/testsuite/gas/arc/nps400-1.d | 18 +++++
gas/testsuite/gas/arc/nps400-1.s | 12 ++++
include/ChangeLog | 4 ++
include/opcode/arc.h | 1 +
opcodes/ChangeLog | 15 ++++
opcodes/arc-nps400-tbl.h | 11 +++
opcodes/arc-opc.c | 147 +++++++++++++++++++++++++++++++++++++++
10 files changed, 232 insertions(+)
create mode 100644 gas/testsuite/gas/arc/nps400-0.d
create mode 100644 gas/testsuite/gas/arc/nps400-0.s
create mode 100644 gas/testsuite/gas/arc/nps400-1.d
create mode 100644 gas/testsuite/gas/arc/nps400-1.s
create mode 100644 opcodes/arc-nps400-tbl.h
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 71f7ec0..aaf724c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * testsuite/gas/arc/nps400-0.d: New file.
+ * testsuite/gas/arc/nps400-0.s: New file.
+ * testsuite/gas/arc/nps400-1.d: New file.
+ * testsuite/gas/arc/nps400-1.s: New file.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
declarations to start of block. Reset code on all flags before
attempting to match them. Handle multiple hits on the same flag.
diff --git a/gas/testsuite/gas/arc/nps400-0.d b/gas/testsuite/gas/arc/nps400-0.d
new file mode 100644
index 0000000..a34a4d5
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.d
@@ -0,0 +1,15 @@
+#as: -mcpu=nps400
+#readelf: -h
+
+#...
+ Class: ELF32
+ Data: 2's complement, .* endian
+ Version: 1 \(current\)
+ OS/ABI: UNIX - System V
+ ABI Version: 0
+ Type: REL \(Relocatable file\)
+ Machine: ARCompact
+ Version: 0x1
+#...
+ Flags: 0x307, NPS400, v3 no-legacy-syscalls ABI
+#...
\ No newline at end of file
diff --git a/gas/testsuite/gas/arc/nps400-0.s b/gas/testsuite/gas/arc/nps400-0.s
new file mode 100644
index 0000000..2b6cc1d
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.s
@@ -0,0 +1,2 @@
+ .text
+ nop
diff --git a/gas/testsuite/gas/arc/nps400-1.d b/gas/testsuite/gas/arc/nps400-1.d
new file mode 100644
index 0000000..294356a
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.d
@@ -0,0 +1,18 @@
+#as: -mcpu=nps400
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 4821 1485 movb r0,r0,r1,0x4,0x5,0x6
+ 4: 4881 1485 movb r0,r0,r12,0x4,0x5,0x6
+ 8: 4f81 1485 movb r15,r15,r12,0x4,0x5,0x6
+ c: 4821 9485 movb.cl r0,r1,0x4,0x5,0x6
+ 10: 48c1 9485 movb.cl r0,r14,0x4,0x5,0x6
+ 14: 4d21 9485 movb.cl r13,r1,0x4,0x5,0x6
+ 18: 4808 04d2 movh r0,r0,0x4d2
+ 1c: 4868 ffff movh r3,r3,0xffff
+ 20: 4818 04d2 movh.cl r0,0x4d2
+ 24: 4878 ffff movh.cl r3,0xffff
diff --git a/gas/testsuite/gas/arc/nps400-1.s b/gas/testsuite/gas/arc/nps400-1.s
new file mode 100644
index 0000000..34d43d0
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.s
@@ -0,0 +1,12 @@
+ .text
+ movb r0, r0, r1, 4, 5, 6
+ movb r0, r0, r12, 4, 5, 6
+ movb r15, r15, r12, 4, 5, 6
+ movb.cl r0, r1, 4, 5, 6
+ movb.cl r0, r14, 4, 5, 6
+ movb.cl r13, r1, 4, 5, 6
+
+ movh r0, r0, 1234
+ movh r3, r3, 0xffff
+ movh.cl r0, 1234
+ movh.cl r3, 0xffff
diff --git a/include/ChangeLog b/include/ChangeLog
index 7742efa..4163e74 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,9 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * opcodes/arc.h (insn_class_t): Add BITOP type.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
new classes instead.
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 3310c10..ee2ebfa 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -46,6 +46,7 @@ typedef enum
KERNEL,
LOGICAL,
MEMORY,
+ BITOP,
} insn_class_t;
/* Instruction Subclass. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f590a43..dda65ef 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,20 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * arc-nps400-tbl.h: New file.
+ * arc-opc.c: Add top level comment.
+ (insert_nps_3bit_dst): New function.
+ (extract_nps_3bit_dst): New function.
+ (insert_nps_3bit_src2): New function.
+ (extract_nps_3bit_src2): New function.
+ (insert_nps_bitop_size): New function.
+ (extract_nps_bitop_size): New function.
+ (arc_flag_operands): Add nps400 entries.
+ (arc_flag_classes): Add nps400 entries.
+ (arc_operands): Add nps400 entries.
+ (arc_opcodes): Add nps400 include.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* arc-opc.c (arc_flag_classes): Convert all flag classes to use
the new class enum values.
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
new file mode 100644
index 0000000..4b715f9
--- /dev/null
+++ b/opcodes/arc-nps400-tbl.h
@@ -0,0 +1,11 @@
+/* movl<.cl> */
+{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
+{ "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
+
+/* movl<.cl> */
+{ "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
+{ "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
+
+/* movb<.f><.cl> */
+{ "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index f126fa8..82aaf1e 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -26,6 +26,12 @@
#include "opintl.h"
#include "libiberty.h"
+/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
+ instructions. Support for this target is available when binutils is
+ configured and built for the 'arc*-mellanox-*-*' target. As far as
+ possible all ARC NPS400 features are built into all ARC target builds as
+ this reduces the chances that regressions might creep in. */
+
/* Insert RB register into a 32-bit opcode. */
static unsigned
insert_rb (unsigned insn,
@@ -637,6 +643,104 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
return value;
}
+/* ARC NPS400 Support: See comment near head of file. */
+static unsigned
+insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 24;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 24;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 21;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 21;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 21) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value < 1 || value > 32)
+ {
+ *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
+ return insn;
+ }
+
+ --value;
+ insn |= ((value & 0x1f) << 10);
+ return insn;
+}
+
+static int
+extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 10) & 0x1f) + 1;
+}
+
/* Include the generic extract/insert functions. Order is important
as some of the functions present in the .h may be disabled via
defines. */
@@ -792,6 +896,13 @@ const struct arc_flag_operand arc_flag_operands[] =
/* Fake Flags. */
#define F_NE (F_H17 + 1)
{ "ne", 0, 0, 0, 1 },
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define F_NPS_CL (F_NE + 1)
+ { "cl", 0, 0, 0, 1 },
+
+#define F_NPS_FLAG (F_NPS_CL + 1)
+ { "f", 1, 1, 20, 1 },
};
const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
@@ -863,6 +974,13 @@ const struct arc_flag_class arc_flag_classes[] =
#define C_NE (C_AS + 1)
{ F_CLASS_OPTIONAL, { F_NE, F_NULL}},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define C_NPS_CL (C_NE + 1)
+ { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
+
+#define C_NPS_F (C_NPS_CL + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
};
/* The operands table.
@@ -1181,6 +1299,34 @@ const struct arc_operand arc_operands[] =
/* UIMM6_5_S mask = 0000011111100000. */
#define UIMM6_5_S (W6 + 1)
{6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define NPS_R_DST_3B (UIMM6_5_S + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
+
+#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
+
+#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
+ { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
+
+#define NPS_R_DST (NPS_R_SRC2_3B + 1)
+ { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, NULL, NULL },
+
+#define NPS_R_SRC1 (NPS_R_DST + 1)
+ { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, NULL, NULL },
+
+#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
+ { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
+ { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size },
+
+#define NPS_UIMM16 (NPS_BITOP_SIZE + 1)
+ { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
@@ -1196,6 +1342,7 @@ const unsigned arc_NToperand = FKT_NT;
const struct arc_opcode arc_opcodes[] =
{
#include "arc-tbl.h"
+#include "arc-nps400-tbl.h"
};
const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant.
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
` (9 preceding siblings ...)
2016-03-15 23:02 ` [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag Andrew Burgess
@ 2016-03-15 23:02 ` Andrew Burgess
2016-03-16 11:06 ` Claudiu Zissulescu
10 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 23:02 UTC (permalink / raw)
To: binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab, Andrew Burgess
The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h
file, and is used in a few places in binutils, however, this constant
should never make it into the elf header flags; we always set a valid
cpu type in the assembler, which should then be copied over during
linking.
In order to simplify the code this commit remove EF_ARC_CPU_GENERIC.
bfd/ChangeLog:
* elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
EF_ARC_CPU_GENERIC.
(arc_elf_final_write_processing): Don't bother setting cpu field
in e_flags, this will have been set elsewhere.
binutils/ChangeLog:
* readelf.c (get_machine_flags): Remove use of EF_ARC_CPU_GENERIC.
gas/ChangeLog:
* config/tc-arc.c (arc_select_cpu): Remove use of
EF_ARC_CPU_GENERIC.
include/ChangeLog:
* elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
---
bfd/ChangeLog | 7 +++++++
bfd/elf32-arc.c | 10 ----------
binutils/ChangeLog | 4 ++++
binutils/readelf.c | 3 ---
gas/ChangeLog | 5 +++++
gas/config/tc-arc.c | 7 +++----
include/ChangeLog | 4 ++++
include/elf/arc.h | 6 ++----
8 files changed, 25 insertions(+), 21 deletions(-)
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index d2532f0..20c1904 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,5 +1,12 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
+ EF_ARC_CPU_GENERIC.
+ (arc_elf_final_write_processing): Don't bother setting cpu field
+ in e_flags, this will have been set elsewhere.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* elf32-arc.c (arc_elf_final_write_processing): Switch to using
EF_ARC_MACH_MSK.
diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index 7c856d0..ec81852 100644
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -415,7 +415,6 @@ arc_elf_print_private_bfd_data (bfd *abfd, void * ptr)
switch (flags & EF_ARC_MACH_MSK)
{
- case EF_ARC_CPU_GENERIC : fprintf (file, " -mcpu=generic"); break;
case EF_ARC_CPU_ARCV2HS : fprintf (file, " -mcpu=ARCv2HS"); break;
case EF_ARC_CPU_ARCV2EM : fprintf (file, " -mcpu=ARCv2EM"); break;
case E_ARC_MACH_ARC600 : fprintf (file, " -mcpu=ARC600"); break;
@@ -647,34 +646,25 @@ static void
arc_elf_final_write_processing (bfd * abfd,
bfd_boolean linker ATTRIBUTE_UNUSED)
{
- unsigned long val;
unsigned long emf;
switch (bfd_get_mach (abfd))
{
case bfd_mach_arc_arc600:
- val = E_ARC_MACH_ARC600;
emf = EM_ARC_COMPACT;
break;
case bfd_mach_arc_arc601:
- val = E_ARC_MACH_ARC601;
emf = EM_ARC_COMPACT;
break;
case bfd_mach_arc_arc700:
- val = E_ARC_MACH_ARC700;
emf = EM_ARC_COMPACT;
break;
case bfd_mach_arc_arcv2:
- val = EF_ARC_CPU_GENERIC;
emf = EM_ARC_COMPACT2;
- /* TODO: Check validity of this. It can also be ARCV2EM here.
- Previous version sets the e_machine here. */
break;
default:
abort ();
}
- if ((elf_elfheader (abfd)->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_GENERIC)
- elf_elfheader (abfd)->e_flags |= val;
elf_elfheader (abfd)->e_machine = emf;
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 9328815..1ac9384 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,5 +1,9 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * readelf.c (get_machine_flags): Remove use of EF_ARC_CPU_GENERIC.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
to the architecture list.
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 7deac04..b764234 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -2776,9 +2776,6 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
case EF_ARC_CPU_ARCV2HS:
strcat (buf, ", ARC HS");
break;
- case EF_ARC_CPU_GENERIC:
- strcat (buf, ", ARC generic");
- break;
case E_ARC_MACH_ARC600:
strcat (buf, ", ARC600");
break;
diff --git a/gas/ChangeLog b/gas/ChangeLog
index fc026ea..16d7f34 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * config/tc-arc.c (arc_select_cpu): Remove use of
+ EF_ARC_CPU_GENERIC.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* config/tc-arc.c (arc_target): Delay initialisation until
arc_select_cpu.
(arc_target_name): Likewise.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 5633905..65eb0e9 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -573,7 +573,7 @@ md_number_to_chars_midend (char *buf, valueT val, int n)
static void
arc_select_cpu (const char *arg)
{
- int cpu_flags = EF_ARC_CPU_GENERIC;
+ int cpu_flags = 0;
int i;
for (i = 0; cpu_types[i].name; ++i)
@@ -591,9 +591,8 @@ arc_select_cpu (const char *arg)
if (!cpu_types[i].name)
as_fatal (_("unknown architecture: %s\n"), arg);
-
- if (cpu_flags != EF_ARC_CPU_GENERIC)
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+ gas_assert (cpu_flags != 0);
+ arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
}
/* Here ends all the ARCompact extension instruction assembling
diff --git a/include/ChangeLog b/include/ChangeLog
index b083a8d..102d1c0 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,9 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* elf/arc.h (EF_ARC_MACH): Delete.
(EF_ARC_MACH_MSK): Remove out of date comment.
diff --git a/include/elf/arc.h b/include/elf/arc.h
index 0b75465..47381f3 100644
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -43,13 +43,11 @@ END_RELOC_NUMBERS (R_ARC_max)
#define EF_ARC_OSABI_MSK 0x00000f00
#define EF_ARC_ALL_MSK (EF_ARC_MACH_MSK | EF_ARC_OSABI_MSK)
-/* Various CPU types. */
+/* Various CPU types. These numbers are exposed in the ELF header flags
+ (e_flags field), and so must never change. */
#define E_ARC_MACH_ARC600 0x00000002
#define E_ARC_MACH_ARC601 0x00000004
#define E_ARC_MACH_ARC700 0x00000003
-
-/* Processor specific flags for the ELF header e_flags field. */
-#define EF_ARC_CPU_GENERIC 0x00000000
#define EF_ARC_CPU_ARCV2EM 0x00000005
#define EF_ARC_CPU_ARCV2HS 0x00000006
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv3 0/7] Add initial arc nps400 support
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
` (6 preceding siblings ...)
2016-03-15 23:02 ` [PATCHv3 1/7] gas/arc: Fix test for big-endian arc Andrew Burgess
@ 2016-03-15 23:02 ` Andrew Burgess
2016-03-17 16:15 ` Pedro Alves
2016-03-15 23:02 ` [PATCHv3 6/7] arc/opcodes: Use flag operand class to handle multiple flag matches Andrew Burgess
` (2 subsequent siblings)
10 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 23:02 UTC (permalink / raw)
To: binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab, Andrew Burgess
Here's a rewrite that removes the need to use the vendor string in
order change the behaviour of binutils[1].
I didn't set out to expand my 2 patch series into a 7 patch series in
order to prove that avoiding the vendor string resulted in a bunch of
extra code :) though I can understand if it looks that way.
Patch 1 is a bug fix for a new big-endian arc regression that has
crept in.
Patch 2 was patch 1 in the previous series.
Patch 3 and 4 are clean up of the constants used to setup the elf
header flags. I hadn't looked at these too closely before, but now I
needed to add a new one I though this code could be simplified.
Patch 5 adds the new nps400 cpu type, this is the code that replaces
the use of the vendor string in the old patch 2 from my previous
iteration of this series. I have now split this out into its own
patch as there's more of it.
Patch 6 is a new patch that modifies the way that the CLASS attribute
of arc flag operands are used. This makes the final patch smaller
than it was previously.
Patch 7 is the new instruction part of what used to be patch 2 in the
previous iteration of this series. I've now included a few more
instructions, so there's a few more operands. However, thanks to
patch 6 there's actually less insert/extract code than before.
Is this OK?
Thanks,
Andrew
[1] I still don't understand why that's a bad thing though....
---
Andrew Burgess (7):
gas/arc: Fix test for big-endian arc
arc/gas: default mach is arc700, initialised in md_begin
arc: Remove duplicated constant in include/elf/arc.h
arc: Remove EF_ARC_CPU_GENERIC constant.
arc: Add nps400 machine type, and assembler flag.
arc/opcodes: Use flag operand class to handle multiple flag matches
arc/nps400: Add first nps400 instructions
bfd/ChangeLog | 21 +++
bfd/archures.c | 1 +
bfd/bfd-in2.h | 1 +
bfd/cpu-arc.c | 5 +-
bfd/elf32-arc.c | 16 +--
binutils/ChangeLog | 13 ++
binutils/readelf.c | 9 +-
binutils/testsuite/binutils-all/objdump.exp | 2 +-
gas/ChangeLog | 44 ++++++
gas/config/tc-arc.c | 104 +++++++-------
gas/testsuite/gas/arc/asm-errors.d | 2 +
gas/testsuite/gas/arc/asm-errors.err | 4 +
gas/testsuite/gas/arc/asm-errors.s | 4 +
gas/testsuite/gas/arc/inline-data-1.d | 1 +
gas/testsuite/gas/arc/inline-data-2.d | 9 ++
gas/testsuite/gas/arc/nps400-0.d | 15 +++
gas/testsuite/gas/arc/nps400-0.s | 2 +
gas/testsuite/gas/arc/nps400-1.d | 18 +++
gas/testsuite/gas/arc/nps400-1.s | 12 ++
include/ChangeLog | 27 ++++
include/elf/arc.h | 12 +-
include/opcode/arc.h | 25 ++--
opcodes/ChangeLog | 28 ++++
opcodes/arc-dis.c | 4 +
opcodes/arc-nps400-tbl.h | 11 ++
opcodes/arc-opc.c | 201 ++++++++++++++++++++++++----
26 files changed, 476 insertions(+), 115 deletions(-)
create mode 100644 gas/testsuite/gas/arc/asm-errors.d
create mode 100644 gas/testsuite/gas/arc/asm-errors.err
create mode 100644 gas/testsuite/gas/arc/asm-errors.s
create mode 100644 gas/testsuite/gas/arc/inline-data-2.d
create mode 100644 gas/testsuite/gas/arc/nps400-0.d
create mode 100644 gas/testsuite/gas/arc/nps400-0.s
create mode 100644 gas/testsuite/gas/arc/nps400-1.d
create mode 100644 gas/testsuite/gas/arc/nps400-1.s
create mode 100644 opcodes/arc-nps400-tbl.h
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag.
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
` (8 preceding siblings ...)
2016-03-15 23:02 ` [PATCHv3 6/7] arc/opcodes: Use flag operand class to handle multiple flag matches Andrew Burgess
@ 2016-03-15 23:02 ` Andrew Burgess
2016-03-16 11:09 ` Claudiu Zissulescu
2016-03-16 21:27 ` Andrew Burgess
2016-03-15 23:02 ` [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant Andrew Burgess
10 siblings, 2 replies; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 23:02 UTC (permalink / raw)
To: binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab, Andrew Burgess
This commit introduces the nps400 machine type as a variant of arc.
There's a new flag in the assembler to select this machine type. All
other changes are just adding handling of the new machine type into the
relevant places.
The nps400 is an arc700 variant with some vendor specific instructions
added into the instruction set. This commit does not add any of the new
instructions, this is just laying the groundwork for future commits.
However, in preparation for these new instructions a new opcode define for
nps400 has been added to include/opcode/arc.h, this new opcode define is
used in the assembler and disassembler along with the existing define
for arc700 such that when assembling and disassembling for nps400 the
user will have access to all arc700 instructions and all the nps400
vendor extension instructions.
bfd/ChangeLog:
* archures.c (bfd_mach_arc_nps400): Define.
* bfd-in2.h: Regenerate.
* cpu-arc.c (arch_info_struct): New entry for nps400, renumber
some existing entries to make space.
* elf32-arc.c (arc_elf_object_p): Add nps400 case.
(arc_elf_final_write_processing): Likewise.
binutils/ChangeLog:
* readelf.c (get_machine_flags): Handle nps400.
gas/ChangeLog:
* config/tc-arc.c (cpu_types): Add nps400 entry.
(check_zol): Handle nps400.
include/ChangeLog:
* elf/arc.h (E_ARC_MACH_NPS400): Define.
* opcode/arc.h (ARC_OPCODE_NPS400): Define.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Handle nps400.
---
bfd/ChangeLog | 9 +++++++++
bfd/archures.c | 1 +
bfd/bfd-in2.h | 1 +
bfd/cpu-arc.c | 5 +++--
bfd/elf32-arc.c | 6 ++++++
binutils/ChangeLog | 4 ++++
binutils/readelf.c | 6 ++++++
gas/ChangeLog | 5 +++++
gas/config/tc-arc.c | 3 +++
include/ChangeLog | 5 +++++
include/elf/arc.h | 1 +
include/opcode/arc.h | 1 +
opcodes/ChangeLog | 4 ++++
opcodes/arc-dis.c | 4 ++++
14 files changed, 53 insertions(+), 2 deletions(-)
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 20c1904..0c82aea 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,5 +1,14 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * archures.c (bfd_mach_arc_nps400): Define.
+ * bfd-in2.h: Regenerate.
+ * cpu-arc.c (arch_info_struct): New entry for nps400, renumber
+ some existing entries to make space.
+ * elf32-arc.c (arc_elf_object_p): Add nps400 case.
+ (arc_elf_final_write_processing): Likewise.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
EF_ARC_CPU_GENERIC.
(arc_elf_final_write_processing): Don't bother setting cpu field
diff --git a/bfd/archures.c b/bfd/archures.c
index 12e3342..7ff1e82 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -359,6 +359,7 @@ DESCRIPTION
.#define bfd_mach_arc_arc601 4
.#define bfd_mach_arc_arc700 3
.#define bfd_mach_arc_arcv2 5
+.#define bfd_mach_arc_nps400 6
. bfd_arch_m32c, {* Renesas M16C/M32C. *}
.#define bfd_mach_m16c 0x75
.#define bfd_mach_m32c 0x78
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 13f2d6e..f02e2aa 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2174,6 +2174,7 @@ enum bfd_architecture
#define bfd_mach_arc_arc601 4
#define bfd_mach_arc_arc700 3
#define bfd_mach_arc_arcv2 5
+#define bfd_mach_arc_nps400 6
bfd_arch_m32c, /* Renesas M16C/M32C. */
#define bfd_mach_m16c 0x75
#define bfd_mach_m32c 0x78
diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c
index 07a052b..472af8d 100644
--- a/bfd/cpu-arc.c
+++ b/bfd/cpu-arc.c
@@ -47,8 +47,9 @@ static const bfd_arch_info_type arch_info_struct[] =
ARC (bfd_mach_arc_arc601, "ARC601", FALSE, &arch_info_struct[3]),
ARC (bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[4]),
ARC (bfd_mach_arc_arc700, "A7", FALSE, &arch_info_struct[5]),
- ARC (bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[6]),
- ARC (bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[7]),
+ ARC (bfd_mach_arc_nps400, "NPS400", FALSE, &arch_info_struct[6]),
+ ARC (bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[7]),
+ ARC (bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[8]),
ARC (bfd_mach_arc_arcv2, "HS", FALSE, NULL),
};
diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index ec81852..488b86f 100644
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -610,6 +610,9 @@ arc_elf_object_p (bfd * abfd)
case E_ARC_MACH_ARC700:
mach = bfd_mach_arc_arc700;
break;
+ case E_ARC_MACH_NPS400:
+ mach = bfd_mach_arc_nps400;
+ break;
case EF_ARC_CPU_ARCV2HS:
case EF_ARC_CPU_ARCV2EM:
mach = bfd_mach_arc_arcv2;
@@ -659,6 +662,9 @@ arc_elf_final_write_processing (bfd * abfd,
case bfd_mach_arc_arc700:
emf = EM_ARC_COMPACT;
break;
+ case bfd_mach_arc_nps400:
+ emf = EM_ARC_COMPACT;
+ break;
case bfd_mach_arc_arcv2:
emf = EM_ARC_COMPACT2;
break;
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 1ac9384..de99ad2 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,5 +1,9 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * readelf.c (get_machine_flags): Handle nps400.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* readelf.c (get_machine_flags): Remove use of EF_ARC_CPU_GENERIC.
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
diff --git a/binutils/readelf.c b/binutils/readelf.c
index b764234..920eca5 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -2785,6 +2785,9 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
case E_ARC_MACH_ARC700:
strcat (buf, ", ARC700");
break;
+ case E_ARC_MACH_NPS400:
+ strcat (buf, ", NPS400");
+ break;
default:
strcat (buf, ", unrecognized cpu flag for ARCv2");
break;
@@ -2819,6 +2822,9 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
case E_ARC_MACH_ARC700:
strcat (buf, ", ARC 700");
break;
+ case E_ARC_MACH_NPS400:
+ strcat (buf, ", NPS400");
+ break;
default:
strcat (buf, ", Generic ARCompact");
break;
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 16d7f34..8df40e9 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * config/tc-arc.c (cpu_types): Add nps400 entry.
+ (check_zol): Handle nps400.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* config/tc-arc.c (arc_select_cpu): Remove use of
EF_ARC_CPU_GENERIC.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 65eb0e9..2bf7f13 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -342,6 +342,8 @@ static const struct cpu_type
E_ARC_MACH_ARC600, 0x00},
{ "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
E_ARC_MACH_ARC700, 0x00},
+ { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400,
+ E_ARC_MACH_NPS400, 0x00},
{ "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
EF_ARC_CPU_ARCV2EM, ARC_CD},
{ "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
@@ -3655,6 +3657,7 @@ check_zol (symbolS *s)
end of the ZOL label @%s"), S_GET_NAME (s));
/* Fall through. */
+ case bfd_mach_arc_nps400:
case bfd_mach_arc_arc700:
if (arc_last_insns[0].has_delay_slot)
as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
diff --git a/include/ChangeLog b/include/ChangeLog
index 102d1c0..d531748 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * elf/arc.h (E_ARC_MACH_NPS400): Define.
+ * opcode/arc.h (ARC_OPCODE_NPS400): Define.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
diff --git a/include/elf/arc.h b/include/elf/arc.h
index 47381f3..2aed25d 100644
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -48,6 +48,7 @@ END_RELOC_NUMBERS (R_ARC_max)
#define E_ARC_MACH_ARC600 0x00000002
#define E_ARC_MACH_ARC601 0x00000004
#define E_ARC_MACH_ARC700 0x00000003
+#define E_ARC_MACH_NPS400 0x00000007
#define EF_ARC_CPU_ARCV2EM 0x00000005
#define EF_ARC_CPU_ARCV2HS 0x00000006
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index d33b878..85ea735 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -132,6 +132,7 @@ extern const unsigned arc_num_opcodes;
#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
+#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
/* CPU extensions. */
#define ARC_EA 0x0001
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e367f65..f9c5f77 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * arc-dis.c (print_insn_arc): Handle nps400.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* arc-opc.c (BASE): Delete.
2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 7320c9f..aeb3ba6 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -132,6 +132,10 @@ print_insn_arc (bfd_vma memaddr,
switch (info->mach)
{
+ case bfd_mach_arc_nps400:
+ isa_mask = ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400;
+ break;
+
case bfd_mach_arc_arc700:
isa_mask = ARC_OPCODE_ARC700;
break;
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv3 3/7] arc: Remove duplicated constant in include/elf/arc.h
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
` (2 preceding siblings ...)
2016-03-11 20:13 ` PING: Re: [PATCHv2 0/2] Add initial arc nps400 support Andrew Burgess
@ 2016-03-15 23:02 ` Andrew Burgess
2016-03-16 11:00 ` Claudiu Zissulescu
2016-03-18 9:58 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 7/7] arc/nps400: Add first nps400 instructions Andrew Burgess
` (6 subsequent siblings)
10 siblings, 2 replies; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 23:02 UTC (permalink / raw)
To: binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab, Andrew Burgess
In the include/elf/arc.h there are two constants that mask out the
machine architecture field. One is used lots (EF_ARC_MACH_MSK), the
other is used only once (EF_ARC_MACH). Remove EF_ARC_MACH.
bfd/ChangeLog:
* elf32-arc.c (arc_elf_final_write_processing): Switch to using
EF_ARC_MACH_MSK.
include/ChangeLog:
* elf/arc.h (EF_ARC_MACH): Delete.
(EF_ARC_MACH_MSK): Remove out of date comment.
---
bfd/ChangeLog | 5 +++++
bfd/elf32-arc.c | 2 +-
include/ChangeLog | 5 +++++
include/elf/arc.h | 5 -----
4 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 740fd44..d2532f0 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * elf32-arc.c (arc_elf_final_write_processing): Switch to using
+ EF_ARC_MACH_MSK.
+
2016-03-15 H.J. Lu <hongjiu.lu@intel.com>
PR ld/19827
diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index 4090b7a..7c856d0 100644
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -673,7 +673,7 @@ arc_elf_final_write_processing (bfd * abfd,
default:
abort ();
}
- if ((elf_elfheader (abfd)->e_flags & EF_ARC_MACH) == EF_ARC_CPU_GENERIC)
+ if ((elf_elfheader (abfd)->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_GENERIC)
elf_elfheader (abfd)->e_flags |= val;
elf_elfheader (abfd)->e_machine = emf;
diff --git a/include/ChangeLog b/include/ChangeLog
index 2930b80..b083a8d 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * elf/arc.h (EF_ARC_MACH): Delete.
+ (EF_ARC_MACH_MSK): Remove out of date comment.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* opcode/arc.h (ARC_OPCODE_BASE): Delete.
2016-03-15 H.J. Lu <hongjiu.lu@intel.com>
diff --git a/include/elf/arc.h b/include/elf/arc.h
index e535f24..0b75465 100644
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -39,15 +39,10 @@ END_RELOC_NUMBERS (R_ARC_max)
/* Processor specific flags for the ELF header e_flags field. */
-/* Four bit ARC machine type field. */
#define EF_ARC_MACH_MSK 0x000000ff
#define EF_ARC_OSABI_MSK 0x00000f00
#define EF_ARC_ALL_MSK (EF_ARC_MACH_MSK | EF_ARC_OSABI_MSK)
-/* Four bit ARC machine type field. */
-
-#define EF_ARC_MACH 0x0000000f
-
/* Various CPU types. */
#define E_ARC_MACH_ARC600 0x00000002
#define E_ARC_MACH_ARC601 0x00000004
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv3 1/7] gas/arc: Fix test for big-endian arc
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
` (5 preceding siblings ...)
2016-03-15 23:02 ` [PATCHv3 2/7] arc/gas: default mach is arc700, initialised in md_begin Andrew Burgess
@ 2016-03-15 23:02 ` Andrew Burgess
2016-03-16 10:56 ` Claudiu Zissulescu
2016-03-18 9:55 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 0/7] Add initial arc nps400 support Andrew Burgess
` (3 subsequent siblings)
10 siblings, 2 replies; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 23:02 UTC (permalink / raw)
To: binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab, Andrew Burgess
The inline-data test checks the specific bytes laid down by the
assembler, and so relies on the endianness of the target. I could
change the expected results to be endian agnostic, however, I worried
that a bug in the assembler that gets the endianness wrong would then
slip through. Instead I add a new test for big-endian arc, and restrict
the existing test to little-endian arc.
gas/ChangeLog:
* testsuite/gas/arc/inline-data-1.d: Add target restriction.
* testsuite/gas/arc/inline-data-2.d: New file.
---
gas/ChangeLog | 5 +++++
gas/testsuite/gas/arc/inline-data-1.d | 1 +
gas/testsuite/gas/arc/inline-data-2.d | 9 +++++++++
3 files changed, 15 insertions(+)
create mode 100644 gas/testsuite/gas/arc/inline-data-2.d
diff --git a/gas/ChangeLog b/gas/ChangeLog
index d67d752..ec65c57 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/gas/arc/inline-data-1.d: Add target restriction.
+ * testsuite/gas/arc/inline-data-2.d: New file.
+
2016-03-15 Ulrich Drepper <drepper@gmail.com>
* doc/c-i386.texi (Register Naming): Update to details of the
diff --git a/gas/testsuite/gas/arc/inline-data-1.d b/gas/testsuite/gas/arc/inline-data-1.d
index ce5c272..9b5e442 100644
--- a/gas/testsuite/gas/arc/inline-data-1.d
+++ b/gas/testsuite/gas/arc/inline-data-1.d
@@ -1,4 +1,5 @@
#as: -mcpu=arc700
+#target: arc-*
#objdump: -sj .text
.*: +file format .*arc.*
diff --git a/gas/testsuite/gas/arc/inline-data-2.d b/gas/testsuite/gas/arc/inline-data-2.d
new file mode 100644
index 0000000..60435d4
--- /dev/null
+++ b/gas/testsuite/gas/arc/inline-data-2.d
@@ -0,0 +1,9 @@
+#as: -mcpu=arc700
+#target: arceb-*
+#objdump: -sj .text
+#source: inline-data-1.s
+
+.*: +file format .*arc.*
+
+Contents of section .text:
+ [0-9a-f]+ aabbccdd eeff .*
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCHv3 2/7] arc/gas: default mach is arc700, initialised in md_begin
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
` (4 preceding siblings ...)
2016-03-15 23:02 ` [PATCHv3 7/7] arc/nps400: Add first nps400 instructions Andrew Burgess
@ 2016-03-15 23:02 ` Andrew Burgess
2016-03-18 9:58 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 1/7] gas/arc: Fix test for big-endian arc Andrew Burgess
` (4 subsequent siblings)
10 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-15 23:02 UTC (permalink / raw)
To: binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab, Andrew Burgess
This commit restructures the selection of the default cpu/mach so that
the choice is made from md_begin (if the user has not provided a command
line choice). This will reduce the amount of change needed in a later
patch.
At the request of Synopsys, the default architecture changes to ARC700
from this commit, previously the default was a non-existent
super-architecture that contained all instructions from all arc
variants. There's some clean up associated with removing the default
merged architecture, and a small test fix now that the default is
ARC700.
binutils/ChangeLog:
* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
to the architecture list.
gas/ChangeLog:
* config/tc-arc.c (arc_target): Delay initialisation until
arc_select_cpu.
(arc_target_name): Likewise.
(arc_features): Likewise.
(arc_mach_type): Likewise.
(cpu_types): Remove "all" entry.
(arc_select_cpu): New function, most of the content is from...
(md_parse_option): ... here. Call new arc_select_cpu.
(md_begin): Call arc_select_cpu if needed, default is now arc700.
include/ChangeLog:
* opcode/arc.h (ARC_OPCODE_BASE): Delete.
opcodes/ChangeLog:
* arc-opc.c (BASE): Delete.
---
binutils/ChangeLog | 5 ++
binutils/testsuite/binutils-all/objdump.exp | 2 +-
gas/ChangeLog | 12 +++++
gas/config/tc-arc.c | 80 ++++++++++++++---------------
include/ChangeLog | 4 ++
include/opcode/arc.h | 5 --
opcodes/ChangeLog | 4 ++
opcodes/arc-opc.c | 3 --
8 files changed, 64 insertions(+), 51 deletions(-)
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 918299a..9328815 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
+ to the architecture list.
+
2016-03-07 Nick Clifton <nickc@redhat.com>
PR binutils/19775
diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp
index 22c4686..3573037 100644
--- a/binutils/testsuite/binutils-all/objdump.exp
+++ b/binutils/testsuite/binutils-all/objdump.exp
@@ -34,7 +34,7 @@ send_user "Version [binutil_version $OBJDUMP]"
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
-lappend cpus_expected aarch64 alpha arc ARCv2 arm cris
+lappend cpus_expected aarch64 alpha arc ARC700 ARCv2 arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k
diff --git a/gas/ChangeLog b/gas/ChangeLog
index ec65c57..fc026ea 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,17 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * config/tc-arc.c (arc_target): Delay initialisation until
+ arc_select_cpu.
+ (arc_target_name): Likewise.
+ (arc_features): Likewise.
+ (arc_mach_type): Likewise.
+ (cpu_types): Remove "all" entry.
+ (arc_select_cpu): New function, most of the content is from...
+ (md_parse_option): ... here. Call new arc_select_cpu.
+ (md_begin): Call arc_select_cpu if needed, default is now arc700.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* testsuite/gas/arc/inline-data-1.d: Add target restriction.
* testsuite/gas/arc/inline-data-2.d: New file.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 0e92c55..5633905 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -311,12 +311,12 @@ static void assemble_insn
const struct arc_flags *, int, struct arc_insn *);
/* The cpu for which we are generating code. */
-static unsigned arc_target = ARC_OPCODE_BASE;
-static const char *arc_target_name = "<all>";
-static unsigned arc_features = 0x00;
+static unsigned arc_target;
+static const char *arc_target_name;
+static unsigned arc_features;
/* The default architecture. */
-static int arc_mach_type = bfd_mach_arc_arcv2;
+static int arc_mach_type;
/* Non-zero if the cpu type has been explicitly specified. */
static int mach_type_specified_p = 0;
@@ -346,8 +346,6 @@ static const struct cpu_type
EF_ARC_CPU_ARCV2EM, ARC_CD},
{ "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
EF_ARC_CPU_ARCV2HS, ARC_CD},
- { "all", ARC_OPCODE_BASE, bfd_mach_arc_arcv2,
- 0x00, 0x00 },
{ 0, 0, 0, 0, 0 }
};
@@ -569,6 +567,35 @@ md_number_to_chars_midend (char *buf, valueT val, int n)
}
}
+/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
+ the relevant static global variables. */
+
+static void
+arc_select_cpu (const char *arg)
+{
+ int cpu_flags = EF_ARC_CPU_GENERIC;
+ int i;
+
+ for (i = 0; cpu_types[i].name; ++i)
+ {
+ if (!strcasecmp (cpu_types[i].name, arg))
+ {
+ arc_target = cpu_types[i].flags;
+ arc_target_name = cpu_types[i].name;
+ arc_features = cpu_types[i].features;
+ arc_mach_type = cpu_types[i].mach;
+ cpu_flags = cpu_types[i].eflags;
+ break;
+ }
+ }
+
+ if (!cpu_types[i].name)
+ as_fatal (_("unknown architecture: %s\n"), arg);
+
+ if (cpu_flags != EF_ARC_CPU_GENERIC)
+ arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+}
+
/* Here ends all the ARCompact extension instruction assembling
stuff. */
@@ -2088,6 +2115,9 @@ md_begin (void)
{
unsigned int i;
+ if (!mach_type_specified_p)
+ arc_select_cpu ("arc700");
+
/* The endianness can be chosen "at the factory". */
target_big_endian = byte_order == BIG_ENDIAN;
@@ -2874,8 +2904,6 @@ arc_parse_name (const char *name,
int
md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
{
- int cpu_flags = EF_ARC_CPU_GENERIC;
-
switch (c)
{
case OPTION_ARC600:
@@ -2893,37 +2921,8 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
case OPTION_MCPU:
{
- int i;
- char *s = alloca (strlen (arg) + 1);
-
- {
- char *t = s;
- char *arg1 = arg;
-
- do
- *t = TOLOWER (*arg1++);
- while (*t++);
- }
-
- for (i = 0; cpu_types[i].name; ++i)
- {
- if (!strcmp (cpu_types[i].name, s))
- {
- arc_target = cpu_types[i].flags;
- arc_target_name = cpu_types[i].name;
- arc_features = cpu_types[i].features;
- arc_mach_type = cpu_types[i].mach;
- cpu_flags = cpu_types[i].eflags;
-
- mach_type_specified_p = 1;
- break;
- }
- }
-
- if (!cpu_types[i].name)
- {
- as_fatal (_("unknown architecture: %s\n"), arg);
- }
+ arc_select_cpu (arg);
+ mach_type_specified_p = 1;
break;
}
@@ -2977,9 +2976,6 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
return 0;
}
- if (cpu_flags != EF_ARC_CPU_GENERIC)
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
-
return 1;
}
diff --git a/include/ChangeLog b/include/ChangeLog
index 3523a27..2930b80 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * opcode/arc.h (ARC_OPCODE_BASE): Delete.
+
2016-03-15 H.J. Lu <hongjiu.lu@intel.com>
PR ld/19807
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 6f5bc98..d33b878 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -171,11 +171,6 @@ extern const unsigned arc_num_opcodes;
#define ARC_XMAC 0x1000
#define ARC_CRC 0x1000
-/* Base architecture -- all cpus. */
-#define ARC_OPCODE_BASE \
- (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
-
/* A macro to check for short instructions. */
#define ARC_SHORT(mask) \
(((mask) & 0xFFFF0000) ? 0 : 1)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 09fd66f..e367f65 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (BASE): Delete.
+
2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* mcore-opc.h: Add const qualifiers.
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 9a674d5..a4fdaff 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -642,9 +642,6 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
defines. */
#include "arc-fxi.h"
-/* Abbreviations for instruction subsets. */
-#define BASE ARC_OPCODE_BASE
-
/* The flag operands table.
The format of the table is
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCHv3 1/7] gas/arc: Fix test for big-endian arc
2016-03-15 23:02 ` [PATCHv3 1/7] gas/arc: Fix test for big-endian arc Andrew Burgess
@ 2016-03-16 10:56 ` Claudiu Zissulescu
2016-03-18 9:55 ` Nick Clifton
1 sibling, 0 replies; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-03-16 10:56 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab
This test was failing for a while in our nightly, good you fix it.
//Claudiu
> -----Original Message-----
> From: Andrew Burgess [mailto:andrew.burgess@embecosm.com]
> Sent: Wednesday, March 16, 2016 12:02 AM
> To: binutils@sourceware.org
> Cc: Claudiu.Zissulescu@synopsys.com; Cupertino.Miranda@synopsys.com;
> noamca@mellanox.com; Nick Clifton; Andreas Schwab; Andrew Burgess
> Subject: [PATCHv3 1/7] gas/arc: Fix test for big-endian arc
>
> The inline-data test checks the specific bytes laid down by the
> assembler, and so relies on the endianness of the target. I could
> change the expected results to be endian agnostic, however, I worried
> that a bug in the assembler that gets the endianness wrong would then
> slip through. Instead I add a new test for big-endian arc, and restrict
> the existing test to little-endian arc.
>
> gas/ChangeLog:
>
> * testsuite/gas/arc/inline-data-1.d: Add target restriction.
> * testsuite/gas/arc/inline-data-2.d: New file.
> ---
> gas/ChangeLog | 5 +++++
> gas/testsuite/gas/arc/inline-data-1.d | 1 +
> gas/testsuite/gas/arc/inline-data-2.d | 9 +++++++++
> 3 files changed, 15 insertions(+)
> create mode 100644 gas/testsuite/gas/arc/inline-data-2.d
>
> diff --git a/gas/ChangeLog b/gas/ChangeLog
> index d67d752..ec65c57 100644
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,3 +1,8 @@
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> + * testsuite/gas/arc/inline-data-1.d: Add target restriction.
> + * testsuite/gas/arc/inline-data-2.d: New file.
> +
> 2016-03-15 Ulrich Drepper <drepper@gmail.com>
>
> * doc/c-i386.texi (Register Naming): Update to details of the
> diff --git a/gas/testsuite/gas/arc/inline-data-1.d
> b/gas/testsuite/gas/arc/inline-data-1.d
> index ce5c272..9b5e442 100644
> --- a/gas/testsuite/gas/arc/inline-data-1.d
> +++ b/gas/testsuite/gas/arc/inline-data-1.d
> @@ -1,4 +1,5 @@
> #as: -mcpu=arc700
> +#target: arc-*
> #objdump: -sj .text
>
> .*: +file format .*arc.*
> diff --git a/gas/testsuite/gas/arc/inline-data-2.d
> b/gas/testsuite/gas/arc/inline-data-2.d
> new file mode 100644
> index 0000000..60435d4
> --- /dev/null
> +++ b/gas/testsuite/gas/arc/inline-data-2.d
> @@ -0,0 +1,9 @@
> +#as: -mcpu=arc700
> +#target: arceb-*
> +#objdump: -sj .text
> +#source: inline-data-1.s
> +
> +.*: +file format .*arc.*
> +
> +Contents of section .text:
> + [0-9a-f]+ aabbccdd eeff .*
> --
> 2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCHv3 3/7] arc: Remove duplicated constant in include/elf/arc.h
2016-03-15 23:02 ` [PATCHv3 3/7] arc: Remove duplicated constant in include/elf/arc.h Andrew Burgess
@ 2016-03-16 11:00 ` Claudiu Zissulescu
2016-03-18 9:58 ` Nick Clifton
1 sibling, 0 replies; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-03-16 11:00 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab
From my side, it looks alright.
//Claudiu
> -----Original Message-----
> From: Andrew Burgess [mailto:andrew.burgess@embecosm.com]
> Sent: Wednesday, March 16, 2016 12:02 AM
> To: binutils@sourceware.org
> Cc: Claudiu.Zissulescu@synopsys.com; Cupertino.Miranda@synopsys.com;
> noamca@mellanox.com; Nick Clifton; Andreas Schwab; Andrew Burgess
> Subject: [PATCHv3 3/7] arc: Remove duplicated constant in include/elf/arc.h
>
> In the include/elf/arc.h there are two constants that mask out the
> machine architecture field. One is used lots (EF_ARC_MACH_MSK), the
> other is used only once (EF_ARC_MACH). Remove EF_ARC_MACH.
>
> bfd/ChangeLog:
>
> * elf32-arc.c (arc_elf_final_write_processing): Switch to using
> EF_ARC_MACH_MSK.
>
> include/ChangeLog:
>
> * elf/arc.h (EF_ARC_MACH): Delete.
> (EF_ARC_MACH_MSK): Remove out of date comment.
> ---
> bfd/ChangeLog | 5 +++++
> bfd/elf32-arc.c | 2 +-
> include/ChangeLog | 5 +++++
> include/elf/arc.h | 5 -----
> 4 files changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/bfd/ChangeLog b/bfd/ChangeLog
> index 740fd44..d2532f0 100644
> --- a/bfd/ChangeLog
> +++ b/bfd/ChangeLog
> @@ -1,3 +1,8 @@
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> + * elf32-arc.c (arc_elf_final_write_processing): Switch to using
> + EF_ARC_MACH_MSK.
> +
> 2016-03-15 H.J. Lu <hongjiu.lu@intel.com>
>
> PR ld/19827
> diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
> index 4090b7a..7c856d0 100644
> --- a/bfd/elf32-arc.c
> +++ b/bfd/elf32-arc.c
> @@ -673,7 +673,7 @@ arc_elf_final_write_processing (bfd * abfd,
> default:
> abort ();
> }
> - if ((elf_elfheader (abfd)->e_flags & EF_ARC_MACH) ==
> EF_ARC_CPU_GENERIC)
> + if ((elf_elfheader (abfd)->e_flags & EF_ARC_MACH_MSK) ==
> EF_ARC_CPU_GENERIC)
> elf_elfheader (abfd)->e_flags |= val;
>
> elf_elfheader (abfd)->e_machine = emf;
> diff --git a/include/ChangeLog b/include/ChangeLog
> index 2930b80..b083a8d 100644
> --- a/include/ChangeLog
> +++ b/include/ChangeLog
> @@ -1,5 +1,10 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * elf/arc.h (EF_ARC_MACH): Delete.
> + (EF_ARC_MACH_MSK): Remove out of date comment.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * opcode/arc.h (ARC_OPCODE_BASE): Delete.
>
> 2016-03-15 H.J. Lu <hongjiu.lu@intel.com>
> diff --git a/include/elf/arc.h b/include/elf/arc.h
> index e535f24..0b75465 100644
> --- a/include/elf/arc.h
> +++ b/include/elf/arc.h
> @@ -39,15 +39,10 @@ END_RELOC_NUMBERS (R_ARC_max)
>
> /* Processor specific flags for the ELF header e_flags field. */
>
> -/* Four bit ARC machine type field. */
> #define EF_ARC_MACH_MSK 0x000000ff
> #define EF_ARC_OSABI_MSK 0x00000f00
> #define EF_ARC_ALL_MSK (EF_ARC_MACH_MSK |
> EF_ARC_OSABI_MSK)
>
> -/* Four bit ARC machine type field. */
> -
> -#define EF_ARC_MACH 0x0000000f
> -
> /* Various CPU types. */
> #define E_ARC_MACH_ARC600 0x00000002
> #define E_ARC_MACH_ARC601 0x00000004
> --
> 2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant.
2016-03-15 23:02 ` [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant Andrew Burgess
@ 2016-03-16 11:06 ` Claudiu Zissulescu
2016-03-16 11:16 ` Andrew Burgess
0 siblings, 1 reply; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-03-16 11:06 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab
I am not very sure about this patch. The official Synopsys ARC compiler doesn't set the e_flags. The code you just removed was made to handle those situations. Did you made some testing against those kind of situations.
Thanks,
Claudiu
> -----Original Message-----
> From: Andrew Burgess [mailto:andrew.burgess@embecosm.com]
> Sent: Wednesday, March 16, 2016 12:02 AM
> To: binutils@sourceware.org
> Cc: Claudiu.Zissulescu@synopsys.com; Cupertino.Miranda@synopsys.com;
> noamca@mellanox.com; Nick Clifton; Andreas Schwab; Andrew Burgess
> Subject: [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant.
>
> The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h
> file, and is used in a few places in binutils, however, this constant
> should never make it into the elf header flags; we always set a valid
> cpu type in the assembler, which should then be copied over during
> linking.
>
> In order to simplify the code this commit remove EF_ARC_CPU_GENERIC.
>
> bfd/ChangeLog:
>
> * elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
> EF_ARC_CPU_GENERIC.
> (arc_elf_final_write_processing): Don't bother setting cpu field
> in e_flags, this will have been set elsewhere.
>
> binutils/ChangeLog:
>
> * readelf.c (get_machine_flags): Remove use of
> EF_ARC_CPU_GENERIC.
>
> gas/ChangeLog:
>
> * config/tc-arc.c (arc_select_cpu): Remove use of
> EF_ARC_CPU_GENERIC.
>
> include/ChangeLog:
>
> * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related
> comment.
> ---
> bfd/ChangeLog | 7 +++++++
> bfd/elf32-arc.c | 10 ----------
> binutils/ChangeLog | 4 ++++
> binutils/readelf.c | 3 ---
> gas/ChangeLog | 5 +++++
> gas/config/tc-arc.c | 7 +++----
> include/ChangeLog | 4 ++++
> include/elf/arc.h | 6 ++----
> 8 files changed, 25 insertions(+), 21 deletions(-)
>
> diff --git a/bfd/ChangeLog b/bfd/ChangeLog
> index d2532f0..20c1904 100644
> --- a/bfd/ChangeLog
> +++ b/bfd/ChangeLog
> @@ -1,5 +1,12 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
> + EF_ARC_CPU_GENERIC.
> + (arc_elf_final_write_processing): Don't bother setting cpu field
> + in e_flags, this will have been set elsewhere.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * elf32-arc.c (arc_elf_final_write_processing): Switch to using
> EF_ARC_MACH_MSK.
>
> diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
> index 7c856d0..ec81852 100644
> --- a/bfd/elf32-arc.c
> +++ b/bfd/elf32-arc.c
> @@ -415,7 +415,6 @@ arc_elf_print_private_bfd_data (bfd *abfd, void *
> ptr)
>
> switch (flags & EF_ARC_MACH_MSK)
> {
> - case EF_ARC_CPU_GENERIC : fprintf (file, " -mcpu=generic"); break;
> case EF_ARC_CPU_ARCV2HS : fprintf (file, " -mcpu=ARCv2HS"); break;
> case EF_ARC_CPU_ARCV2EM : fprintf (file, " -mcpu=ARCv2EM"); break;
> case E_ARC_MACH_ARC600 : fprintf (file, " -mcpu=ARC600"); break;
> @@ -647,34 +646,25 @@ static void
> arc_elf_final_write_processing (bfd * abfd,
> bfd_boolean linker ATTRIBUTE_UNUSED)
> {
> - unsigned long val;
> unsigned long emf;
>
> switch (bfd_get_mach (abfd))
> {
> case bfd_mach_arc_arc600:
> - val = E_ARC_MACH_ARC600;
> emf = EM_ARC_COMPACT;
> break;
> case bfd_mach_arc_arc601:
> - val = E_ARC_MACH_ARC601;
> emf = EM_ARC_COMPACT;
> break;
> case bfd_mach_arc_arc700:
> - val = E_ARC_MACH_ARC700;
> emf = EM_ARC_COMPACT;
> break;
> case bfd_mach_arc_arcv2:
> - val = EF_ARC_CPU_GENERIC;
> emf = EM_ARC_COMPACT2;
> - /* TODO: Check validity of this. It can also be ARCV2EM here.
> - Previous version sets the e_machine here. */
> break;
> default:
> abort ();
> }
> - if ((elf_elfheader (abfd)->e_flags & EF_ARC_MACH_MSK) ==
> EF_ARC_CPU_GENERIC)
> - elf_elfheader (abfd)->e_flags |= val;
>
> elf_elfheader (abfd)->e_machine = emf;
>
> diff --git a/binutils/ChangeLog b/binutils/ChangeLog
> index 9328815..1ac9384 100644
> --- a/binutils/ChangeLog
> +++ b/binutils/ChangeLog
> @@ -1,5 +1,9 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * readelf.c (get_machine_flags): Remove use of
> EF_ARC_CPU_GENERIC.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
> to the architecture list.
>
> diff --git a/binutils/readelf.c b/binutils/readelf.c
> index 7deac04..b764234 100644
> --- a/binutils/readelf.c
> +++ b/binutils/readelf.c
> @@ -2776,9 +2776,6 @@ get_machine_flags (unsigned e_flags, unsigned
> e_machine)
> case EF_ARC_CPU_ARCV2HS:
> strcat (buf, ", ARC HS");
> break;
> - case EF_ARC_CPU_GENERIC:
> - strcat (buf, ", ARC generic");
> - break;
> case E_ARC_MACH_ARC600:
> strcat (buf, ", ARC600");
> break;
> diff --git a/gas/ChangeLog b/gas/ChangeLog
> index fc026ea..16d7f34 100644
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,5 +1,10 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * config/tc-arc.c (arc_select_cpu): Remove use of
> + EF_ARC_CPU_GENERIC.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * config/tc-arc.c (arc_target): Delay initialisation until
> arc_select_cpu.
> (arc_target_name): Likewise.
> diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
> index 5633905..65eb0e9 100644
> --- a/gas/config/tc-arc.c
> +++ b/gas/config/tc-arc.c
> @@ -573,7 +573,7 @@ md_number_to_chars_midend (char *buf, valueT
> val, int n)
> static void
> arc_select_cpu (const char *arg)
> {
> - int cpu_flags = EF_ARC_CPU_GENERIC;
> + int cpu_flags = 0;
> int i;
>
> for (i = 0; cpu_types[i].name; ++i)
> @@ -591,9 +591,8 @@ arc_select_cpu (const char *arg)
>
> if (!cpu_types[i].name)
> as_fatal (_("unknown architecture: %s\n"), arg);
> -
> - if (cpu_flags != EF_ARC_CPU_GENERIC)
> - arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
> + gas_assert (cpu_flags != 0);
> + arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
> }
>
> /* Here ends all the ARCompact extension instruction assembling
> diff --git a/include/ChangeLog b/include/ChangeLog
> index b083a8d..102d1c0 100644
> --- a/include/ChangeLog
> +++ b/include/ChangeLog
> @@ -1,5 +1,9 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related
> comment.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * elf/arc.h (EF_ARC_MACH): Delete.
> (EF_ARC_MACH_MSK): Remove out of date comment.
>
> diff --git a/include/elf/arc.h b/include/elf/arc.h
> index 0b75465..47381f3 100644
> --- a/include/elf/arc.h
> +++ b/include/elf/arc.h
> @@ -43,13 +43,11 @@ END_RELOC_NUMBERS (R_ARC_max)
> #define EF_ARC_OSABI_MSK 0x00000f00
> #define EF_ARC_ALL_MSK (EF_ARC_MACH_MSK |
> EF_ARC_OSABI_MSK)
>
> -/* Various CPU types. */
> +/* Various CPU types. These numbers are exposed in the ELF header flags
> + (e_flags field), and so must never change. */
> #define E_ARC_MACH_ARC600 0x00000002
> #define E_ARC_MACH_ARC601 0x00000004
> #define E_ARC_MACH_ARC700 0x00000003
> -
> -/* Processor specific flags for the ELF header e_flags field. */
> -#define EF_ARC_CPU_GENERIC 0x00000000
> #define EF_ARC_CPU_ARCV2EM 0x00000005
> #define EF_ARC_CPU_ARCV2HS 0x00000006
>
> --
> 2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag.
2016-03-15 23:02 ` [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag Andrew Burgess
@ 2016-03-16 11:09 ` Claudiu Zissulescu
2016-03-16 11:23 ` Andrew Burgess
2016-03-16 21:27 ` Andrew Burgess
1 sibling, 1 reply; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-03-16 11:09 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab
It seems ok, though some testing is required.
//Claudiu
> -----Original Message-----
> From: Andrew Burgess [mailto:andrew.burgess@embecosm.com]
> Sent: Wednesday, March 16, 2016 12:02 AM
> To: binutils@sourceware.org
> Cc: Claudiu.Zissulescu@synopsys.com; Cupertino.Miranda@synopsys.com;
> noamca@mellanox.com; Nick Clifton; Andreas Schwab; Andrew Burgess
> Subject: [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag.
>
> This commit introduces the nps400 machine type as a variant of arc.
> There's a new flag in the assembler to select this machine type. All
> other changes are just adding handling of the new machine type into the
> relevant places.
>
> The nps400 is an arc700 variant with some vendor specific instructions
> added into the instruction set. This commit does not add any of the new
> instructions, this is just laying the groundwork for future commits.
> However, in preparation for these new instructions a new opcode define for
> nps400 has been added to include/opcode/arc.h, this new opcode define is
> used in the assembler and disassembler along with the existing define
> for arc700 such that when assembling and disassembling for nps400 the
> user will have access to all arc700 instructions and all the nps400
> vendor extension instructions.
>
> bfd/ChangeLog:
>
> * archures.c (bfd_mach_arc_nps400): Define.
> * bfd-in2.h: Regenerate.
> * cpu-arc.c (arch_info_struct): New entry for nps400, renumber
> some existing entries to make space.
> * elf32-arc.c (arc_elf_object_p): Add nps400 case.
> (arc_elf_final_write_processing): Likewise.
>
> binutils/ChangeLog:
>
> * readelf.c (get_machine_flags): Handle nps400.
>
> gas/ChangeLog:
>
> * config/tc-arc.c (cpu_types): Add nps400 entry.
> (check_zol): Handle nps400.
>
> include/ChangeLog:
>
> * elf/arc.h (E_ARC_MACH_NPS400): Define.
> * opcode/arc.h (ARC_OPCODE_NPS400): Define.
>
> opcodes/ChangeLog:
>
> * arc-dis.c (print_insn_arc): Handle nps400.
> ---
> bfd/ChangeLog | 9 +++++++++
> bfd/archures.c | 1 +
> bfd/bfd-in2.h | 1 +
> bfd/cpu-arc.c | 5 +++--
> bfd/elf32-arc.c | 6 ++++++
> binutils/ChangeLog | 4 ++++
> binutils/readelf.c | 6 ++++++
> gas/ChangeLog | 5 +++++
> gas/config/tc-arc.c | 3 +++
> include/ChangeLog | 5 +++++
> include/elf/arc.h | 1 +
> include/opcode/arc.h | 1 +
> opcodes/ChangeLog | 4 ++++
> opcodes/arc-dis.c | 4 ++++
> 14 files changed, 53 insertions(+), 2 deletions(-)
>
> diff --git a/bfd/ChangeLog b/bfd/ChangeLog
> index 20c1904..0c82aea 100644
> --- a/bfd/ChangeLog
> +++ b/bfd/ChangeLog
> @@ -1,5 +1,14 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * archures.c (bfd_mach_arc_nps400): Define.
> + * bfd-in2.h: Regenerate.
> + * cpu-arc.c (arch_info_struct): New entry for nps400, renumber
> + some existing entries to make space.
> + * elf32-arc.c (arc_elf_object_p): Add nps400 case.
> + (arc_elf_final_write_processing): Likewise.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
> EF_ARC_CPU_GENERIC.
> (arc_elf_final_write_processing): Don't bother setting cpu field
> diff --git a/bfd/archures.c b/bfd/archures.c
> index 12e3342..7ff1e82 100644
> --- a/bfd/archures.c
> +++ b/bfd/archures.c
> @@ -359,6 +359,7 @@ DESCRIPTION
> .#define bfd_mach_arc_arc601 4
> .#define bfd_mach_arc_arc700 3
> .#define bfd_mach_arc_arcv2 5
> +.#define bfd_mach_arc_nps400 6
> . bfd_arch_m32c, {* Renesas M16C/M32C. *}
> .#define bfd_mach_m16c 0x75
> .#define bfd_mach_m32c 0x78
> diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
> index 13f2d6e..f02e2aa 100644
> --- a/bfd/bfd-in2.h
> +++ b/bfd/bfd-in2.h
> @@ -2174,6 +2174,7 @@ enum bfd_architecture
> #define bfd_mach_arc_arc601 4
> #define bfd_mach_arc_arc700 3
> #define bfd_mach_arc_arcv2 5
> +#define bfd_mach_arc_nps400 6
> bfd_arch_m32c, /* Renesas M16C/M32C. */
> #define bfd_mach_m16c 0x75
> #define bfd_mach_m32c 0x78
> diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c
> index 07a052b..472af8d 100644
> --- a/bfd/cpu-arc.c
> +++ b/bfd/cpu-arc.c
> @@ -47,8 +47,9 @@ static const bfd_arch_info_type arch_info_struct[] =
> ARC (bfd_mach_arc_arc601, "ARC601", FALSE, &arch_info_struct[3]),
> ARC (bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[4]),
> ARC (bfd_mach_arc_arc700, "A7", FALSE, &arch_info_struct[5]),
> - ARC (bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[6]),
> - ARC (bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[7]),
> + ARC (bfd_mach_arc_nps400, "NPS400", FALSE, &arch_info_struct[6]),
> + ARC (bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[7]),
> + ARC (bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[8]),
> ARC (bfd_mach_arc_arcv2, "HS", FALSE, NULL),
> };
>
> diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
> index ec81852..488b86f 100644
> --- a/bfd/elf32-arc.c
> +++ b/bfd/elf32-arc.c
> @@ -610,6 +610,9 @@ arc_elf_object_p (bfd * abfd)
> case E_ARC_MACH_ARC700:
> mach = bfd_mach_arc_arc700;
> break;
> + case E_ARC_MACH_NPS400:
> + mach = bfd_mach_arc_nps400;
> + break;
> case EF_ARC_CPU_ARCV2HS:
> case EF_ARC_CPU_ARCV2EM:
> mach = bfd_mach_arc_arcv2;
> @@ -659,6 +662,9 @@ arc_elf_final_write_processing (bfd * abfd,
> case bfd_mach_arc_arc700:
> emf = EM_ARC_COMPACT;
> break;
> + case bfd_mach_arc_nps400:
> + emf = EM_ARC_COMPACT;
> + break;
> case bfd_mach_arc_arcv2:
> emf = EM_ARC_COMPACT2;
> break;
> diff --git a/binutils/ChangeLog b/binutils/ChangeLog
> index 1ac9384..de99ad2 100644
> --- a/binutils/ChangeLog
> +++ b/binutils/ChangeLog
> @@ -1,5 +1,9 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * readelf.c (get_machine_flags): Handle nps400.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * readelf.c (get_machine_flags): Remove use of
> EF_ARC_CPU_GENERIC.
>
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> diff --git a/binutils/readelf.c b/binutils/readelf.c
> index b764234..920eca5 100644
> --- a/binutils/readelf.c
> +++ b/binutils/readelf.c
> @@ -2785,6 +2785,9 @@ get_machine_flags (unsigned e_flags, unsigned
> e_machine)
> case E_ARC_MACH_ARC700:
> strcat (buf, ", ARC700");
> break;
> + case E_ARC_MACH_NPS400:
> + strcat (buf, ", NPS400");
> + break;
> default:
> strcat (buf, ", unrecognized cpu flag for ARCv2");
> break;
> @@ -2819,6 +2822,9 @@ get_machine_flags (unsigned e_flags, unsigned
> e_machine)
> case E_ARC_MACH_ARC700:
> strcat (buf, ", ARC 700");
> break;
> + case E_ARC_MACH_NPS400:
> + strcat (buf, ", NPS400");
> + break;
> default:
> strcat (buf, ", Generic ARCompact");
> break;
> diff --git a/gas/ChangeLog b/gas/ChangeLog
> index 16d7f34..8df40e9 100644
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,5 +1,10 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * config/tc-arc.c (cpu_types): Add nps400 entry.
> + (check_zol): Handle nps400.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * config/tc-arc.c (arc_select_cpu): Remove use of
> EF_ARC_CPU_GENERIC.
>
> diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
> index 65eb0e9..2bf7f13 100644
> --- a/gas/config/tc-arc.c
> +++ b/gas/config/tc-arc.c
> @@ -342,6 +342,8 @@ static const struct cpu_type
> E_ARC_MACH_ARC600, 0x00},
> { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
> E_ARC_MACH_ARC700, 0x00},
> + { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400,
> bfd_mach_arc_nps400,
> + E_ARC_MACH_NPS400, 0x00},
> { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
> EF_ARC_CPU_ARCV2EM, ARC_CD},
> { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
> @@ -3655,6 +3657,7 @@ check_zol (symbolS *s)
> end of the ZOL label @%s"), S_GET_NAME (s));
>
> /* Fall through. */
> + case bfd_mach_arc_nps400:
> case bfd_mach_arc_arc700:
> if (arc_last_insns[0].has_delay_slot)
> as_bad (_("An illegal use of delay slot detected at the end of the ZOL
> label @%s"),
> diff --git a/include/ChangeLog b/include/ChangeLog
> index 102d1c0..d531748 100644
> --- a/include/ChangeLog
> +++ b/include/ChangeLog
> @@ -1,5 +1,10 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * elf/arc.h (E_ARC_MACH_NPS400): Define.
> + * opcode/arc.h (ARC_OPCODE_NPS400): Define.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related
> comment.
>
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> diff --git a/include/elf/arc.h b/include/elf/arc.h
> index 47381f3..2aed25d 100644
> --- a/include/elf/arc.h
> +++ b/include/elf/arc.h
> @@ -48,6 +48,7 @@ END_RELOC_NUMBERS (R_ARC_max)
> #define E_ARC_MACH_ARC600 0x00000002
> #define E_ARC_MACH_ARC601 0x00000004
> #define E_ARC_MACH_ARC700 0x00000003
> +#define E_ARC_MACH_NPS400 0x00000007
> #define EF_ARC_CPU_ARCV2EM 0x00000005
> #define EF_ARC_CPU_ARCV2HS 0x00000006
>
> diff --git a/include/opcode/arc.h b/include/opcode/arc.h
> index d33b878..85ea735 100644
> --- a/include/opcode/arc.h
> +++ b/include/opcode/arc.h
> @@ -132,6 +132,7 @@ extern const unsigned arc_num_opcodes;
> #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
> #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
> #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
> +#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
>
> /* CPU extensions. */
> #define ARC_EA 0x0001
> diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
> index e367f65..f9c5f77 100644
> --- a/opcodes/ChangeLog
> +++ b/opcodes/ChangeLog
> @@ -1,5 +1,9 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * arc-dis.c (print_insn_arc): Handle nps400.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * arc-opc.c (BASE): Delete.
>
> 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
> diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
> index 7320c9f..aeb3ba6 100644
> --- a/opcodes/arc-dis.c
> +++ b/opcodes/arc-dis.c
> @@ -132,6 +132,10 @@ print_insn_arc (bfd_vma memaddr,
>
> switch (info->mach)
> {
> + case bfd_mach_arc_nps400:
> + isa_mask = ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400;
> + break;
> +
> case bfd_mach_arc_arc700:
> isa_mask = ARC_OPCODE_ARC700;
> break;
> --
> 2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant.
2016-03-16 11:06 ` Claudiu Zissulescu
@ 2016-03-16 11:16 ` Andrew Burgess
2016-03-16 11:23 ` Claudiu Zissulescu
0 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-16 11:16 UTC (permalink / raw)
To: Claudiu Zissulescu
Cc: binutils, Cupertino.Miranda, noamca, Nick Clifton, Andreas Schwab
* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2016-03-16 11:06:16 +0000]:
> I am not very sure about this patch. The official Synopsys ARC
> compiler doesn't set the e_flags. The code you just removed was made
> to handle those situations. Did you made some testing against those
> kind of situations.
No I only considered the GNU tools. I will try to create a test and
see what happens, I may revise, or drop this patch from the series
then.
Out of interest, how do you tell if an ELF is ARC700 / ARCEM / etc
when it is compiled with the official tools if not by using the
e_flags? Is there some other field that should be used?
Thanks,
Andrew
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag.
2016-03-16 11:09 ` Claudiu Zissulescu
@ 2016-03-16 11:23 ` Andrew Burgess
2016-03-16 11:27 ` Claudiu Zissulescu
0 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-16 11:23 UTC (permalink / raw)
To: Claudiu Zissulescu
Cc: binutils, Cupertino.Miranda, noamca, Nick Clifton, Andreas Schwab
* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2016-03-16 11:08:50 +0000]:
> It seems ok, though some testing is required.
What testing would you like to see done? I ran the binutils tests
with no regressions, and I inspected some generated ELF files by eye,
and that all looked fine. I'm happy to run any reasonable testing if
you can specify what you'd like done :)
Thanks,
Andrew
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant.
2016-03-16 11:16 ` Andrew Burgess
@ 2016-03-16 11:23 ` Claudiu Zissulescu
2016-03-16 21:24 ` Andrew Burgess
0 siblings, 1 reply; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-03-16 11:23 UTC (permalink / raw)
To: Andrew Burgess
Cc: binutils, Cupertino.Miranda, noamca, Nick Clifton, Andreas Schwab
> No I only considered the GNU tools. I will try to create a test and
> see what happens, I may revise, or drop this patch from the series
> then.
Yeah, I need to come up with a "compatibility" test here.
>
> Out of interest, how do you tell if an ELF is ARC700 / ARCEM / etc
> when it is compiled with the official tools if not by using the
> e_flags? Is there some other field that should be used?
>
The ARC700/ARC600 has a different machine than ARCHS/ARCEM.
Best,
Claudiu
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag.
2016-03-16 11:23 ` Andrew Burgess
@ 2016-03-16 11:27 ` Claudiu Zissulescu
0 siblings, 0 replies; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-03-16 11:27 UTC (permalink / raw)
To: Andrew Burgess
Cc: binutils, Cupertino.Miranda, noamca, Nick Clifton, Andreas Schwab
Then it should be ok. I am not in the office this week and next week to put your patches through our nightly, so please apologize me if I cannot fully test your contribution.
Best,
Claudiu
> -----Original Message-----
> From: Andrew Burgess [mailto:andrew.burgess@embecosm.com]
> Sent: Wednesday, March 16, 2016 12:23 PM
> To: Claudiu Zissulescu
> Cc: binutils@sourceware.org; Cupertino.Miranda@synopsys.com;
> noamca@mellanox.com; Nick Clifton; Andreas Schwab
> Subject: Re: [PATCHv3 5/7] arc: Add nps400 machine type, and assembler
> flag.
>
> * Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2016-03-16
> 11:08:50 +0000]:
>
> > It seems ok, though some testing is required.
>
> What testing would you like to see done? I ran the binutils tests
> with no regressions, and I inspected some generated ELF files by eye,
> and that all looked fine. I'm happy to run any reasonable testing if
> you can specify what you'd like done :)
>
> Thanks,
> Andrew
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCHv3 6/7] arc/opcodes: Use flag operand class to handle multiple flag matches
2016-03-15 23:02 ` [PATCHv3 6/7] arc/opcodes: Use flag operand class to handle multiple flag matches Andrew Burgess
@ 2016-03-16 11:51 ` Claudiu Zissulescu
2016-03-18 10:00 ` Nick Clifton
1 sibling, 0 replies; 50+ messages in thread
From: Claudiu Zissulescu @ 2016-03-16 11:51 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Cupertino.Miranda, noamca, Nick Clifton, Andreas Schwab
It looks sane, thanks for clearing out one of the todos.
//Claudiu
> -----Original Message-----
> From: Andrew Burgess [mailto:andrew.burgess@embecosm.com]
> Sent: Wednesday, March 16, 2016 12:02 AM
> To: binutils@sourceware.org
> Cc: Claudiu.Zissulescu@synopsys.com; Cupertino.Miranda@synopsys.com;
> noamca@mellanox.com; Nick Clifton; Andreas Schwab; Andrew Burgess
> Subject: [PATCHv3 6/7] arc/opcodes: Use flag operand class to handle
> multiple flag matches
>
> When parsing the operand instruction flags we don't currently detect the
> case where multiple flags are provided from the same class set, these
> will be accepted and the bit values merged together, resulting in the
> wrong instruction being assembled. For example:
>
> adc.n.eq r0,r0,r2
>
> Will assemble without error, yet, upon disassembly, the instruction will
> actually be:
>
> adc.c r0,r0,r2
>
> In a later commit the concept of required flags will be introduced.
> Required flags are just like normal instruction flags, except that they
> must be present for the instruction to match. Adding this will allow
> for simpler instructions in the instruction table, and allow for more
> sharing of operand extraction and insertion functions.
>
> To solve both of the above issues (multiple flags being invalid, and
> required flags), this commit reworks the flag class mechanism.
> Currently the flag class is never used. Each instruction can reference
> multiple flag classes, each flag class has a class type and a set of
> flags. However, at present, the class type is never used. The current
> values identify the type of instruction that the flag will be used in,
> but this is not required information.
>
> Instead, this commit discards the old flag classes, and introduces 3 new
> classes. The first F_CLASS_NONE, is just a NULL marker value, and is
> only used in the NULL marker flag class. The other two flag classes are
> F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.
>
> The class F_FLAG_OPTIONAL has the property that at most one of the flags
> in the flag set for that class must be present in the instruction. The
> "at most" one means that no flags being present is fine.
>
> The class F_FLAG_REQUIRED is not currently used, but will be soon. With
> this class, exactly one of the flags from this class must be present in
> the instruction. If the flag class contains a single flag, then of
> course that flag must be present. However, if the flag class contained
> two or more, then one, and only one of them must be present.
>
> gas/ChangeLog:
>
> * config/tc-arc.c (find_opcode_match): Move lnflg, and i
> declarations to start of block. Reset code on all flags before
> attempting to match them. Handle multiple hits on the same flag.
> Handle flag class.
> * testsuite/gas/arc/asm-errors.d: New file.
> * testsuite/gas/arc/asm-errors.err: New file.
> * testsuite/gas/arc/asm-errors.s: New file.
>
> include/ChangeLog:
>
> * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
> new classes instead.
>
> opcodes/ChangeLog:
>
> * arc-opc.c (arc_flag_classes): Convert all flag classes to use
> the new class enum values.
> ---
> gas/ChangeLog | 10 +++++++
> gas/config/tc-arc.c | 22 +++++++++++-----
> gas/testsuite/gas/arc/asm-errors.d | 2 ++
> gas/testsuite/gas/arc/asm-errors.err | 4 +++
> gas/testsuite/gas/arc/asm-errors.s | 4 +++
> include/ChangeLog | 5 ++++
> include/opcode/arc.h | 18 ++++++-------
> opcodes/ChangeLog | 5 ++++
> opcodes/arc-opc.c | 51 ++++++++++++++++++------------------
> 9 files changed, 81 insertions(+), 40 deletions(-)
> create mode 100644 gas/testsuite/gas/arc/asm-errors.d
> create mode 100644 gas/testsuite/gas/arc/asm-errors.err
> create mode 100644 gas/testsuite/gas/arc/asm-errors.s
>
> diff --git a/gas/ChangeLog b/gas/ChangeLog
> index 8df40e9..71f7ec0 100644
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,5 +1,15 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * config/tc-arc.c (find_opcode_match): Move lnflg, and i
> + declarations to start of block. Reset code on all flags before
> + attempting to match them. Handle multiple hits on the same flag.
> + Handle flag class.
> + * testsuite/gas/arc/asm-errors.d: New file.
> + * testsuite/gas/arc/asm-errors.err: New file.
> + * testsuite/gas/arc/asm-errors.s: New file.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * config/tc-arc.c (cpu_types): Add nps400 entry.
> (check_zol): Handle nps400.
>
> diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
> index 2bf7f13..736143e 100644
> --- a/gas/config/tc-arc.c
> +++ b/gas/config/tc-arc.c
> @@ -1370,7 +1370,7 @@ find_opcode_match (const struct arc_opcode
> *first_opcode,
> {
> const unsigned char *opidx;
> const unsigned char *flgidx;
> - int tokidx = 0;
> + int tokidx = 0, lnflg, i;
> const expressionS *t = &emptyE;
>
> pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
> @@ -1596,20 +1596,23 @@ find_opcode_match (const struct arc_opcode
> *first_opcode,
> }
> pr_debug ("opr ");
>
> - /* Check the flags. Iterate over the valid flag classes. */
> - int lnflg = nflgs;
> + /* Setup ready for flag parsing. */
> + lnflg = nflgs;
> + for (i = 0; i < nflgs; i++)
> + first_pflag [i].code = 0;
>
> - for (flgidx = opcode->flags; *flgidx && lnflg; ++flgidx)
> + /* Check the flags. Iterate over the valid flag classes. */
> + for (flgidx = opcode->flags; *flgidx; ++flgidx)
> {
> /* Get a valid flag class. */
> const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
> const unsigned *flgopridx;
> + int cl_matches = 0;
>
> for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
> {
> const struct arc_flag_operand *flg_operand;
> struct arc_flags *pflag = first_pflag;
> - int i;
>
> flg_operand = &arc_flag_operands[*flgopridx];
> for (i = 0; i < nflgs; i++, pflag++)
> @@ -1617,13 +1620,20 @@ find_opcode_match (const struct arc_opcode
> *first_opcode,
> /* Match against the parsed flags. */
> if (!strcmp (flg_operand->name, pflag->name))
> {
> - /*TODO: Check if it is duplicated. */
> + if (pflag->code != 0)
> + goto match_failed;
> + cl_matches++;
> pflag->code = *flgopridx;
> lnflg--;
> break; /* goto next flag class and parsed flag. */
> }
> }
> }
> +
> + if (cl_flags->class == F_CLASS_REQUIRED && cl_matches == 0)
> + goto match_failed;
> + if (cl_flags->class == F_CLASS_OPTIONAL && cl_matches > 1)
> + goto match_failed;
> }
> /* Did I check all the parsed flags? */
> if (lnflg)
> diff --git a/gas/testsuite/gas/arc/asm-errors.d b/gas/testsuite/gas/arc/asm-
> errors.d
> new file mode 100644
> index 0000000..9255a27
> --- /dev/null
> +++ b/gas/testsuite/gas/arc/asm-errors.d
> @@ -0,0 +1,2 @@
> +#as: -mcpu=arc700
> +#error-output: asm-errors.err
> diff --git a/gas/testsuite/gas/arc/asm-errors.err
> b/gas/testsuite/gas/arc/asm-errors.err
> new file mode 100644
> index 0000000..35390fc
> --- /dev/null
> +++ b/gas/testsuite/gas/arc/asm-errors.err
> @@ -0,0 +1,4 @@
> +[^:]*: Assembler messages:
> +[^:]*:2: Error: inappropriate arguments for opcode 'adc'
> +[^:]*:3: Error: inappropriate arguments for opcode 'adc'
> +[^:]*:4: Error: inappropriate arguments for opcode 'adc'
> diff --git a/gas/testsuite/gas/arc/asm-errors.s b/gas/testsuite/gas/arc/asm-
> errors.s
> new file mode 100644
> index 0000000..6e0fd6a
> --- /dev/null
> +++ b/gas/testsuite/gas/arc/asm-errors.s
> @@ -0,0 +1,4 @@
> + .text
> + adc.al.ra r0,r0,r2
> + adc.eq.eq r0,r0,r2
> + adc.n.eq r0,r0,r2
> diff --git a/include/ChangeLog b/include/ChangeLog
> index d531748..7742efa 100644
> --- a/include/ChangeLog
> +++ b/include/ChangeLog
> @@ -1,5 +1,10 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
> + new classes instead.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * elf/arc.h (E_ARC_MACH_NPS400): Define.
> * opcode/arc.h (ARC_OPCODE_NPS400): Define.
>
> diff --git a/include/opcode/arc.h b/include/opcode/arc.h
> index 85ea735..3310c10 100644
> --- a/include/opcode/arc.h
> +++ b/include/opcode/arc.h
> @@ -72,15 +72,15 @@ typedef enum
> /* Flags class. */
> typedef enum
> {
> - FNONE,
> - CND, /* Conditional flags. */
> - WBM, /* Write-back modes. */
> - FLG, /* F Flag. */
> - SBP, /* Static branch prediction. */
> - DLY, /* Delay slot. */
> - DIF, /* Bypass caches. */
> - SGX, /* Sign extend modes. */
> - SZM /* Data size modes. */
> + F_CLASS_NONE,
> +
> + /* At most one flag from the set of flags can appear in the
> + instruction. */
> + F_CLASS_OPTIONAL,
> +
> + /* Exactly one from from the set of flags must appear in the
> + instruction. */
> + F_CLASS_REQUIRED,
> } flag_class_t;
>
> /* The opcode table is an array of struct arc_opcode. */
> diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
> index f9c5f77..f590a43 100644
> --- a/opcodes/ChangeLog
> +++ b/opcodes/ChangeLog
> @@ -1,5 +1,10 @@
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
>
> + * arc-opc.c (arc_flag_classes): Convert all flag classes to use
> + the new class enum values.
> +
> +2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> +
> * arc-dis.c (print_insn_arc): Handle nps400.
>
> 2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
> diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
> index a4fdaff..f126fa8 100644
> --- a/opcodes/arc-opc.c
> +++ b/opcodes/arc-opc.c
> @@ -803,65 +803,66 @@ const unsigned arc_num_flag_operands =
> ARRAY_SIZE (arc_flag_operands);
> const struct arc_flag_class arc_flag_classes[] =
> {
> #define C_EMPTY 0
> - { FNONE, { F_NULL } },
> + { F_CLASS_NONE, { F_NULL } },
>
> #define C_CC (C_EMPTY + 1)
> - { CND, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO,
> - F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET,
> - F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER,
> F_OVERFLOWSET,
> - F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE,
> F_LT,
> - F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
> + { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO,
> F_NOTEQUAL,
> + F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE,
> F_MINUS,
> + F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
> + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET,
> F_OVERFLOW,
> + F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE,
> F_LT,
> + F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
>
> #define C_AA_ADDR3 (C_CC + 1)
> #define C_AA27 (C_CC + 1)
> - { WBM, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
> + { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
> #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
> #define C_AA21 (C_AA_ADDR3 + 1)
> - { WBM, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
> + { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
> #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
> #define C_AA8 (C_AA_ADDR9 + 1)
> - { WBM, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
> + { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
>
> #define C_F (C_AA_ADDR22 + 1)
> - { FLG, { F_FLAG, F_NULL } },
> + { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
> #define C_FHARD (C_F + 1)
> - { FLG, { F_FFAKE, F_NULL } },
> + { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
>
> #define C_T (C_FHARD + 1)
> - { SBP, { F_NT, F_T, F_NULL } },
> + { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
> #define C_D (C_T + 1)
> - { DLY, { F_ND, F_D, F_NULL } },
> + { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
>
> #define C_DHARD (C_D + 1)
> - { DLY, { F_DFAKE, F_NULL } },
> + { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
>
> #define C_DI20 (C_DHARD + 1)
> - { DIF, { F_DI11, F_NULL }},
> + { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
> #define C_DI16 (C_DI20 + 1)
> - { DIF, { F_DI15, F_NULL }},
> + { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
> #define C_DI26 (C_DI16 + 1)
> - { DIF, { F_DI5, F_NULL }},
> + { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
>
> #define C_X25 (C_DI26 + 1)
> - { SGX, { F_SIGN6, F_NULL }},
> + { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
> #define C_X15 (C_X25 + 1)
> - { SGX, { F_SIGN16, F_NULL }},
> + { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
> #define C_XHARD (C_X15 + 1)
> #define C_X (C_X15 + 1)
> - { SGX, { F_SIGNX, F_NULL }},
> + { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
>
> #define C_ZZ13 (C_X + 1)
> - { SZM, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
> + { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
> #define C_ZZ23 (C_ZZ13 + 1)
> - { SZM, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
> + { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
> #define C_ZZ29 (C_ZZ23 + 1)
> - { SZM, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
> + { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
>
> #define C_AS (C_ZZ29 + 1)
> - { SZM, { F_ASFAKE, F_NULL}},
> + { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
>
> #define C_NE (C_AS + 1)
> - { CND, { F_NE, F_NULL}},
> + { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
> };
>
> /* The operands table.
> --
> 2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant.
2016-03-16 11:23 ` Claudiu Zissulescu
@ 2016-03-16 21:24 ` Andrew Burgess
2016-03-18 9:59 ` Nick Clifton
0 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-16 21:24 UTC (permalink / raw)
To: Claudiu Zissulescu
Cc: binutils, Cupertino.Miranda, noamca, Nick Clifton, Andreas Schwab
* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2016-03-16 11:23:36 +0000]:
> > No I only considered the GNU tools. I will try to create a test and
> > see what happens, I may revise, or drop this patch from the series
> > then.
>
> Yeah, I need to come up with a "compatibility" test here.
> >
> > Out of interest, how do you tell if an ELF is ARC700 / ARCEM / etc
> > when it is compiled with the official tools if not by using the
> > e_flags? Is there some other field that should be used?
> >
> The ARC700/ARC600 has a different machine than ARCHS/ARCEM.
I hacked up a version of bfd that deliberately clears the
EF_ARC_MACH_MSK field in e_flags when creating ELFs, which I believe
should give results inline with the non-gnu synopsys arc compiler.
I've now tweaked the patch a little, and I looked at the differences
when viewing the ELF headers in readelf for and arc600, arc700, archs,
and arcem file all produced using the above hacked bfd.
With the revised patch the only change is that I've moved from
describing the files as "Generic" arc to "Unknown" arc. I don't know
if you'll be happy with the change, but I think "Unknown" is a better
description of what we have.
To me generic means "would run on anything". Now the machine type
does split the problem space in two, older and new architectures, but
I think the point about generic is still sound.
However, the each ELF might contains instructions that limits the file
to only being suitable for one, specific architecture, we just don't
know which one, I think "Unknown" reflects that situation better than
"Generic".
Commit message and patch below for your consideration.
Thanks,
Andrew
---
The constant EF_ARC_CPU_GENERIC is defined in the include/elf/arc.h
file, and is used in a few places in binutils, however, this constant
should never make it into the elf header flags; we always set a valid
cpu type in the assembler, which should then be copied over during
linking.
There are some non-gnu arc compilers that don't write an architecture
type into the e_flags field, instead leaving the field as 0, which is
the EF_ARC_CPU_GENERIC value. This non-gnu compiler uses the machine
type to distinguish between the old and newer arc architectures, setting
the machine type to EM_ARC_COMPACT for old arc600, arc601, and arc700
architectures, while using EM_ARC_COMPACT2 for newer arcem and archs
architectures.
Previously when displaying the machine flags for an older EM_ARC_COMPACT
machine, if the e_flags had not been filled in, then we relied on the
default case statement to display the message "Generic ARCompact", while
in the EM_ARC_COMPACT2 case we specifically handled EF_ARC_CPU_GENERIC
to print "ARC Generic", leaving the default case to print a message
about unrecognised cpu flag.
After this commit EF_ARC_CPU_GENERIC has been removed, for both machine
types EM_ARC_COMPACT and EM_ARC_COMPACT2 we now rely on the default case
statement to handle the situation where the e_flags has not been filled
in. The message displayed is now "Unknown ARCompact" (for older arc
architectures) and "Unknown ARC" (for the newer architectures). The
switch from "Generic" to "Unknown" in the message string is for clarity,
calling the file "Generic" can give the impression that the file is
compiled for a common sub-set of the architectures, and would therefore
run on any type of machine (or at least any type of new or old machine
depending on if the machine type is ARC or ARCv2). However, this was
not what "Generic" meant, it really meant "Unknown", so that's what we
now say.
As part of the merging of the readelf flag reading code, I have unified
the strings used in displaying the ELF ABI. This means that for older
arc machines (arc600, arc601, and arc700) the string used for the
original ABI, and ABIv2 have changed, the current ABIv3 remains the
same. For the newer architectures (arcem and archs) the abi strings
remain unchanged in all cases.
bfd/ChangeLog:
* elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
EF_ARC_CPU_GENERIC.
(arc_elf_final_write_processing): Don't bother setting cpu field
in e_flags, this will have been set elsewhere.
binutils/ChangeLog:
* readelf.c (get_machine_flags): Move arc processing into...
(decode_ARC_machine_flags): ... new function. Remove use of
EF_ARC_CPU_GENERIC, change default case from "generic arc" to
"unknown arc". Merged ABI printing between two machine types.
gas/ChangeLog:
* config/tc-arc.c (arc_select_cpu): Remove use of
EF_ARC_CPU_GENERIC.
include/ChangeLog:
* elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
---
bfd/ChangeLog | 7 +++
bfd/elf32-arc.c | 10 ----
binutils/ChangeLog | 7 +++
binutils/readelf.c | 143 +++++++++++++++++++++++++---------------------------
gas/ChangeLog | 5 ++
gas/config/tc-arc.c | 7 ++-
include/ChangeLog | 4 ++
include/elf/arc.h | 6 +--
8 files changed, 97 insertions(+), 92 deletions(-)
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index d2532f0..20c1904 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,5 +1,12 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
+ EF_ARC_CPU_GENERIC.
+ (arc_elf_final_write_processing): Don't bother setting cpu field
+ in e_flags, this will have been set elsewhere.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* elf32-arc.c (arc_elf_final_write_processing): Switch to using
EF_ARC_MACH_MSK.
diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index 7c856d0..ec81852 100644
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -415,7 +415,6 @@ arc_elf_print_private_bfd_data (bfd *abfd, void * ptr)
switch (flags & EF_ARC_MACH_MSK)
{
- case EF_ARC_CPU_GENERIC : fprintf (file, " -mcpu=generic"); break;
case EF_ARC_CPU_ARCV2HS : fprintf (file, " -mcpu=ARCv2HS"); break;
case EF_ARC_CPU_ARCV2EM : fprintf (file, " -mcpu=ARCv2EM"); break;
case E_ARC_MACH_ARC600 : fprintf (file, " -mcpu=ARC600"); break;
@@ -647,34 +646,25 @@ static void
arc_elf_final_write_processing (bfd * abfd,
bfd_boolean linker ATTRIBUTE_UNUSED)
{
- unsigned long val;
unsigned long emf;
switch (bfd_get_mach (abfd))
{
case bfd_mach_arc_arc600:
- val = E_ARC_MACH_ARC600;
emf = EM_ARC_COMPACT;
break;
case bfd_mach_arc_arc601:
- val = E_ARC_MACH_ARC601;
emf = EM_ARC_COMPACT;
break;
case bfd_mach_arc_arc700:
- val = E_ARC_MACH_ARC700;
emf = EM_ARC_COMPACT;
break;
case bfd_mach_arc_arcv2:
- val = EF_ARC_CPU_GENERIC;
emf = EM_ARC_COMPACT2;
- /* TODO: Check validity of this. It can also be ARCV2EM here.
- Previous version sets the e_machine here. */
break;
default:
abort ();
}
- if ((elf_elfheader (abfd)->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_GENERIC)
- elf_elfheader (abfd)->e_flags |= val;
elf_elfheader (abfd)->e_machine = emf;
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 9328815..f96ee49 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,5 +1,12 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * readelf.c (get_machine_flags): Move arc processing into...
+ (decode_ARC_machine_flags): ... new function. Remove use of
+ EF_ARC_CPU_GENERIC, change default case from "generic arc" to
+ "unknown arc". Merged ABI printing between two machine types.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
to the architecture list.
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 7deac04..fe23d45 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -2271,6 +2271,73 @@ get_machine_name (unsigned e_machine)
}
static void
+decode_ARC_machine_flags (unsigned e_flags, unsigned e_machine, char buf[])
+{
+ /* ARC has two machine types EM_ARC_COMPACT and EM_ARC_COMPACT2. Some
+ other compilers don't a specific architecture type in the e_flags, and
+ instead use EM_ARC_COMPACT for old ARC600, ARC601, and ARC700
+ architectures, and switch to EM_ARC_COMPACT2 for newer ARCEM and ARCHS
+ architectures.
+
+ Th GNU tools follows this use of EM_ARC_COMPACT and EM_ARC_COMPACT2,
+ but also sets a specific architecture type in the e_flags field.
+
+ However, when decoding the flags we don't worry if we see an
+ unexpected pairing, for example EM_ARC_COMPACT machine type, with
+ ARCEM architecture type. */
+
+ switch (e_flags & EF_ARC_MACH_MSK)
+ {
+ /* We only expect these to occur for EM_ARC_COMPACT2. */
+ case EF_ARC_CPU_ARCV2EM:
+ strcat (buf, ", ARC EM");
+ break;
+ case EF_ARC_CPU_ARCV2HS:
+ strcat (buf, ", ARC HS");
+ break;
+
+ /* We only expect these to occur for EM_ARC_COMPACT. */
+ case E_ARC_MACH_ARC600:
+ strcat (buf, ", ARC600");
+ break;
+ case E_ARC_MACH_ARC601:
+ strcat (buf, ", ARC601");
+ break;
+ case E_ARC_MACH_ARC700:
+ strcat (buf, ", ARC700");
+ break;
+
+ /* The only times we should end up here are (a) A corrupt ELF, (b) A
+ new ELF with new architecture being read by an old version of
+ readelf, or (c) An ELF built with non-GNU compiler that does not
+ set the architecture in the e_flags. */
+ default:
+ if (e_machine == EM_ARC_COMPACT)
+ strcat (buf, ", Unknown ARCompact");
+ else
+ strcat (buf, ", Unknown ARC");
+ break;
+ }
+
+ switch (e_flags & EF_ARC_OSABI_MSK)
+ {
+ case E_ARC_OSABI_ORIG:
+ strcat (buf, ", (ABI:legacy)");
+ break;
+ case E_ARC_OSABI_V2:
+ strcat (buf, ", (ABI:v2)");
+ break;
+ /* Only upstream 3.9+ kernels will support ARCv2 ISA. */
+ case E_ARC_OSABI_V3:
+ strcat (buf, ", v3 no-legacy-syscalls ABI");
+ break;
+ default:
+ strcat (buf, ", unrecognised ARC OSABI flag");
+ break;
+ }
+}
+
+static void
decode_ARM_machine_flags (unsigned e_flags, char buf[])
{
unsigned eabi;
@@ -2768,81 +2835,9 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
break;
case EM_ARC_COMPACT2:
- switch (e_flags & EF_ARC_MACH_MSK)
- {
- case EF_ARC_CPU_ARCV2EM:
- strcat (buf, ", ARC EM");
- break;
- case EF_ARC_CPU_ARCV2HS:
- strcat (buf, ", ARC HS");
- break;
- case EF_ARC_CPU_GENERIC:
- strcat (buf, ", ARC generic");
- break;
- case E_ARC_MACH_ARC600:
- strcat (buf, ", ARC600");
- break;
- case E_ARC_MACH_ARC601:
- strcat (buf, ", ARC601");
- break;
- case E_ARC_MACH_ARC700:
- strcat (buf, ", ARC700");
- break;
- default:
- strcat (buf, ", unrecognized cpu flag for ARCv2");
- break;
- }
- switch (e_flags & EF_ARC_OSABI_MSK)
- {
- case E_ARC_OSABI_ORIG:
- strcat (buf, ", (ABI:legacy)");
- break;
- case E_ARC_OSABI_V2:
- strcat (buf, ", (ABI:v2)");
- break;
- /* Only upstream 3.9+ kernels will support ARCv2 ISA. */
- case E_ARC_OSABI_V3:
- strcat (buf, ", v3 no-legacy-syscalls ABI");
- break;
- default:
- strcat (buf, ", unrecognised ARC OSABI flag");
- break;
- }
- break;
-
case EM_ARC_COMPACT:
- switch (e_flags & EF_ARC_MACH_MSK)
- {
- case E_ARC_MACH_ARC600:
- strcat (buf, ", ARC 600");
- break;
- case E_ARC_MACH_ARC601:
- strcat (buf, ", ARC 601");
- break;
- case E_ARC_MACH_ARC700:
- strcat (buf, ", ARC 700");
- break;
- default:
- strcat (buf, ", Generic ARCompact");
- break;
- }
- switch (e_flags & EF_ARC_OSABI_MSK)
- {
- case E_ARC_OSABI_ORIG:
- strcat (buf, ", legacy syscall ABI");
- break;
- case E_ARC_OSABI_V2:
- /* For 3.2+ Linux kernels which use asm-generic
- hdrs. */
- strcat (buf, ", v2 syscall ABI");
- break;
- case E_ARC_OSABI_V3:
- /* Upstream 3.9+ kernels which don't use any legacy
- syscalls. */
- strcat (buf, ", v3 no-legacy-syscalls ABI");
- break;
- }
- break;
+ decode_ARC_machine_flags (e_flags, e_machine, buf);
+ break;
case EM_ARM:
decode_ARM_machine_flags (e_flags, buf);
diff --git a/gas/ChangeLog b/gas/ChangeLog
index fc026ea..16d7f34 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * config/tc-arc.c (arc_select_cpu): Remove use of
+ EF_ARC_CPU_GENERIC.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* config/tc-arc.c (arc_target): Delay initialisation until
arc_select_cpu.
(arc_target_name): Likewise.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 5633905..65eb0e9 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -573,7 +573,7 @@ md_number_to_chars_midend (char *buf, valueT val, int n)
static void
arc_select_cpu (const char *arg)
{
- int cpu_flags = EF_ARC_CPU_GENERIC;
+ int cpu_flags = 0;
int i;
for (i = 0; cpu_types[i].name; ++i)
@@ -591,9 +591,8 @@ arc_select_cpu (const char *arg)
if (!cpu_types[i].name)
as_fatal (_("unknown architecture: %s\n"), arg);
-
- if (cpu_flags != EF_ARC_CPU_GENERIC)
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+ gas_assert (cpu_flags != 0);
+ arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
}
/* Here ends all the ARCompact extension instruction assembling
diff --git a/include/ChangeLog b/include/ChangeLog
index b083a8d..102d1c0 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,9 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* elf/arc.h (EF_ARC_MACH): Delete.
(EF_ARC_MACH_MSK): Remove out of date comment.
diff --git a/include/elf/arc.h b/include/elf/arc.h
index 0b75465..47381f3 100644
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -43,13 +43,11 @@ END_RELOC_NUMBERS (R_ARC_max)
#define EF_ARC_OSABI_MSK 0x00000f00
#define EF_ARC_ALL_MSK (EF_ARC_MACH_MSK | EF_ARC_OSABI_MSK)
-/* Various CPU types. */
+/* Various CPU types. These numbers are exposed in the ELF header flags
+ (e_flags field), and so must never change. */
#define E_ARC_MACH_ARC600 0x00000002
#define E_ARC_MACH_ARC601 0x00000004
#define E_ARC_MACH_ARC700 0x00000003
-
-/* Processor specific flags for the ELF header e_flags field. */
-#define EF_ARC_CPU_GENERIC 0x00000000
#define EF_ARC_CPU_ARCV2EM 0x00000005
#define EF_ARC_CPU_ARCV2HS 0x00000006
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag.
2016-03-15 23:02 ` [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag Andrew Burgess
2016-03-16 11:09 ` Claudiu Zissulescu
@ 2016-03-16 21:27 ` Andrew Burgess
2016-03-18 10:02 ` Nick Clifton
1 sibling, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-16 21:27 UTC (permalink / raw)
To: binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab
This is a minor tweak to update this patch based on the new version of
patch #4 that I just posted. Only difference is in readelf.c, the
change now applies in a different function.
Thanks,
Andrew
---
This commit introduces the nps400 machine type as a variant of arc.
There's a new flag in the assembler to select this machine type. All
other changes are just adding handling of the new machine type into the
relevant places.
The nps400 is an arc700 variant with some vendor specific instructions
added into the instruction set. This commit does not add any of the new
instructions, this is just laying the groundwork for future commits.
However, in preparation for these new instructions a new opcode define for
nps400 has been added to include/opcode/arc.h, this new opcode define is
used in the assembler and disassembler along with the existing define
for arc700 such that when assembling and disassembling for nps400 the
user will have access to all arc700 instructions and all the nps400
vendor extension instructions.
bfd/ChangeLog:
* archures.c (bfd_mach_arc_nps400): Define.
* bfd-in2.h: Regenerate.
* cpu-arc.c (arch_info_struct): New entry for nps400, renumber
some existing entries to make space.
* elf32-arc.c (arc_elf_object_p): Add nps400 case.
(arc_elf_final_write_processing): Likewise.
binutils/ChangeLog:
* readelf.c (decode_ARC_machine_flags): Handle nps400.
gas/ChangeLog:
* config/tc-arc.c (cpu_types): Add nps400 entry.
(check_zol): Handle nps400.
include/ChangeLog:
* elf/arc.h (E_ARC_MACH_NPS400): Define.
* opcode/arc.h (ARC_OPCODE_NPS400): Define.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Handle nps400.
---
bfd/ChangeLog | 9 +++++++++
bfd/archures.c | 1 +
bfd/bfd-in2.h | 1 +
bfd/cpu-arc.c | 5 +++--
bfd/elf32-arc.c | 6 ++++++
binutils/ChangeLog | 4 ++++
binutils/readelf.c | 3 +++
gas/ChangeLog | 5 +++++
gas/config/tc-arc.c | 3 +++
include/ChangeLog | 5 +++++
include/elf/arc.h | 1 +
include/opcode/arc.h | 1 +
opcodes/ChangeLog | 4 ++++
opcodes/arc-dis.c | 4 ++++
14 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 20c1904..0c82aea 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,5 +1,14 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * archures.c (bfd_mach_arc_nps400): Define.
+ * bfd-in2.h: Regenerate.
+ * cpu-arc.c (arch_info_struct): New entry for nps400, renumber
+ some existing entries to make space.
+ * elf32-arc.c (arc_elf_object_p): Add nps400 case.
+ (arc_elf_final_write_processing): Likewise.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
EF_ARC_CPU_GENERIC.
(arc_elf_final_write_processing): Don't bother setting cpu field
diff --git a/bfd/archures.c b/bfd/archures.c
index 12e3342..7ff1e82 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -359,6 +359,7 @@ DESCRIPTION
.#define bfd_mach_arc_arc601 4
.#define bfd_mach_arc_arc700 3
.#define bfd_mach_arc_arcv2 5
+.#define bfd_mach_arc_nps400 6
. bfd_arch_m32c, {* Renesas M16C/M32C. *}
.#define bfd_mach_m16c 0x75
.#define bfd_mach_m32c 0x78
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 13f2d6e..f02e2aa 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2174,6 +2174,7 @@ enum bfd_architecture
#define bfd_mach_arc_arc601 4
#define bfd_mach_arc_arc700 3
#define bfd_mach_arc_arcv2 5
+#define bfd_mach_arc_nps400 6
bfd_arch_m32c, /* Renesas M16C/M32C. */
#define bfd_mach_m16c 0x75
#define bfd_mach_m32c 0x78
diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c
index 07a052b..472af8d 100644
--- a/bfd/cpu-arc.c
+++ b/bfd/cpu-arc.c
@@ -47,8 +47,9 @@ static const bfd_arch_info_type arch_info_struct[] =
ARC (bfd_mach_arc_arc601, "ARC601", FALSE, &arch_info_struct[3]),
ARC (bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[4]),
ARC (bfd_mach_arc_arc700, "A7", FALSE, &arch_info_struct[5]),
- ARC (bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[6]),
- ARC (bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[7]),
+ ARC (bfd_mach_arc_nps400, "NPS400", FALSE, &arch_info_struct[6]),
+ ARC (bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[7]),
+ ARC (bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[8]),
ARC (bfd_mach_arc_arcv2, "HS", FALSE, NULL),
};
diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index ec81852..488b86f 100644
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -610,6 +610,9 @@ arc_elf_object_p (bfd * abfd)
case E_ARC_MACH_ARC700:
mach = bfd_mach_arc_arc700;
break;
+ case E_ARC_MACH_NPS400:
+ mach = bfd_mach_arc_nps400;
+ break;
case EF_ARC_CPU_ARCV2HS:
case EF_ARC_CPU_ARCV2EM:
mach = bfd_mach_arc_arcv2;
@@ -659,6 +662,9 @@ arc_elf_final_write_processing (bfd * abfd,
case bfd_mach_arc_arc700:
emf = EM_ARC_COMPACT;
break;
+ case bfd_mach_arc_nps400:
+ emf = EM_ARC_COMPACT;
+ break;
case bfd_mach_arc_arcv2:
emf = EM_ARC_COMPACT2;
break;
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index f96ee49..aaf40ec 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,5 +1,9 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * readelf.c (decode_ARC_machine_flags): Handle nps400.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* readelf.c (get_machine_flags): Move arc processing into...
(decode_ARC_machine_flags): ... new function. Remove use of
EF_ARC_CPU_GENERIC, change default case from "generic arc" to
diff --git a/binutils/readelf.c b/binutils/readelf.c
index fe23d45..5755b6b 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -2306,6 +2306,9 @@ decode_ARC_machine_flags (unsigned e_flags, unsigned e_machine, char buf[])
case E_ARC_MACH_ARC700:
strcat (buf, ", ARC700");
break;
+ case E_ARC_MACH_NPS400:
+ strcat (buf, ", NPS400");
+ break;
/* The only times we should end up here are (a) A corrupt ELF, (b) A
new ELF with new architecture being read by an old version of
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 16d7f34..8df40e9 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * config/tc-arc.c (cpu_types): Add nps400 entry.
+ (check_zol): Handle nps400.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* config/tc-arc.c (arc_select_cpu): Remove use of
EF_ARC_CPU_GENERIC.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 65eb0e9..2bf7f13 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -342,6 +342,8 @@ static const struct cpu_type
E_ARC_MACH_ARC600, 0x00},
{ "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
E_ARC_MACH_ARC700, 0x00},
+ { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400,
+ E_ARC_MACH_NPS400, 0x00},
{ "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
EF_ARC_CPU_ARCV2EM, ARC_CD},
{ "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
@@ -3655,6 +3657,7 @@ check_zol (symbolS *s)
end of the ZOL label @%s"), S_GET_NAME (s));
/* Fall through. */
+ case bfd_mach_arc_nps400:
case bfd_mach_arc_arc700:
if (arc_last_insns[0].has_delay_slot)
as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
diff --git a/include/ChangeLog b/include/ChangeLog
index 102d1c0..d531748 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * elf/arc.h (E_ARC_MACH_NPS400): Define.
+ * opcode/arc.h (ARC_OPCODE_NPS400): Define.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
diff --git a/include/elf/arc.h b/include/elf/arc.h
index 47381f3..2aed25d 100644
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -48,6 +48,7 @@ END_RELOC_NUMBERS (R_ARC_max)
#define E_ARC_MACH_ARC600 0x00000002
#define E_ARC_MACH_ARC601 0x00000004
#define E_ARC_MACH_ARC700 0x00000003
+#define E_ARC_MACH_NPS400 0x00000007
#define EF_ARC_CPU_ARCV2EM 0x00000005
#define EF_ARC_CPU_ARCV2HS 0x00000006
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index d33b878..85ea735 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -132,6 +132,7 @@ extern const unsigned arc_num_opcodes;
#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
+#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
/* CPU extensions. */
#define ARC_EA 0x0001
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e367f65..f9c5f77 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,9 @@
2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+ * arc-dis.c (print_insn_arc): Handle nps400.
+
+2016-03-15 Andrew Burgess <andrew.burgess@embecosm.com>
+
* arc-opc.c (BASE): Delete.
2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 7320c9f..aeb3ba6 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -132,6 +132,10 @@ print_insn_arc (bfd_vma memaddr,
switch (info->mach)
{
+ case bfd_mach_arc_nps400:
+ isa_mask = ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400;
+ break;
+
case bfd_mach_arc_arc700:
isa_mask = ARC_OPCODE_ARC700;
break;
--
2.5.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 0/7] Add initial arc nps400 support
2016-03-15 23:02 ` [PATCHv3 0/7] Add initial arc nps400 support Andrew Burgess
@ 2016-03-17 16:15 ` Pedro Alves
2016-03-17 17:15 ` Andrew Burgess
0 siblings, 1 reply; 50+ messages in thread
From: Pedro Alves @ 2016-03-17 16:15 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Nick Clifton,
Andreas Schwab
On 03/15/2016 11:01 PM, Andrew Burgess wrote:
> Here's a rewrite that removes the need to use the vendor string in
> order change the behaviour of binutils[1].
>
> [1] I still don't understand why that's a bad thing though....
In an --enable-targets=all world, you need to be able to select
any supported target at run time. Thus, IIUC, in the vendor string
version, an --enable-targets=all build wouldn't include
nps400 support, unless you also specified the primary
target as --target=arm-mellanox.
Nowadays, the vendor/manufacturer string is meant to be free
form, and set by whoever builds the tools to whatever they
like, for branding purposes and $PATH coexistence.
Thanks,
Pedro Alves
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 0/7] Add initial arc nps400 support
2016-03-17 16:15 ` Pedro Alves
@ 2016-03-17 17:15 ` Andrew Burgess
2016-03-17 17:27 ` Pedro Alves
0 siblings, 1 reply; 50+ messages in thread
From: Andrew Burgess @ 2016-03-17 17:15 UTC (permalink / raw)
To: Pedro Alves
Cc: binutils, Claudiu.Zissulescu, Cupertino.Miranda, noamca,
Nick Clifton, Andreas Schwab
* Pedro Alves <palves@redhat.com> [2016-03-17 16:15:07 +0000]:
> On 03/15/2016 11:01 PM, Andrew Burgess wrote:
> > Here's a rewrite that removes the need to use the vendor string in
> > order change the behaviour of binutils[1].
> >
>
> > [1] I still don't understand why that's a bad thing though....
>
> In an --enable-targets=all world, you need to be able to select
> any supported target at run time. Thus, IIUC, in the vendor string
> version, an --enable-targets=all build wouldn't include
> nps400 support, unless you also specified the primary
> target as --target=arm-mellanox.
>
> Nowadays, the vendor/manufacturer string is meant to be free
> form, and set by whoever builds the tools to whatever they
> like, for branding purposes and $PATH coexistence.
Thanks for the explanation. And remembering that I've already updated
the patch, so I ask only out of interest...
... I still think that allowing the vendor string to control some
defaults would be nice. So in my case it would be great if the
default architecture for an arc-mellanox toolchain was nps400, from a
user PoV that seems like it would be a nicer experience .... maybe.
Anyway, thanks again for the explanation,
Andrew
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 0/7] Add initial arc nps400 support
2016-03-17 17:15 ` Andrew Burgess
@ 2016-03-17 17:27 ` Pedro Alves
0 siblings, 0 replies; 50+ messages in thread
From: Pedro Alves @ 2016-03-17 17:27 UTC (permalink / raw)
To: Andrew Burgess
Cc: binutils, Claudiu.Zissulescu, Cupertino.Miranda, noamca,
Nick Clifton, Andreas Schwab
On 03/17/2016 05:15 PM, Andrew Burgess wrote:
> Thanks for the explanation. And remembering that I've already updated
> the patch, so I ask only out of interest...
>
> ... I still think that allowing the vendor string to control some
> defaults would be nice. So in my case it would be great if the
> default architecture for an arc-mellanox toolchain was nps400, from a
> user PoV that seems like it would be a nicer experience .... maybe.
There's precedent for setting defaults with configure switches.
See e.g,. gcc's --with-cpu= and --with-arch=.
And I see gas/configure.ac handles --with-arch for nds32.
Thanks,
Pedro Alves
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 1/7] gas/arc: Fix test for big-endian arc
2016-03-15 23:02 ` [PATCHv3 1/7] gas/arc: Fix test for big-endian arc Andrew Burgess
2016-03-16 10:56 ` Claudiu Zissulescu
@ 2016-03-18 9:55 ` Nick Clifton
1 sibling, 0 replies; 50+ messages in thread
From: Nick Clifton @ 2016-03-18 9:55 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Andreas Schwab
Hi Andrew,
> gas/ChangeLog:
>
> * testsuite/gas/arc/inline-data-1.d: Add target restriction.
> * testsuite/gas/arc/inline-data-2.d: New file.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 3/7] arc: Remove duplicated constant in include/elf/arc.h
2016-03-15 23:02 ` [PATCHv3 3/7] arc: Remove duplicated constant in include/elf/arc.h Andrew Burgess
2016-03-16 11:00 ` Claudiu Zissulescu
@ 2016-03-18 9:58 ` Nick Clifton
1 sibling, 0 replies; 50+ messages in thread
From: Nick Clifton @ 2016-03-18 9:58 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Andreas Schwab
Hi Andrew,
> bfd/ChangeLog:
>
> * elf32-arc.c (arc_elf_final_write_processing): Switch to using
> EF_ARC_MACH_MSK.
>
> include/ChangeLog:
>
> * elf/arc.h (EF_ARC_MACH): Delete.
> (EF_ARC_MACH_MSK): Remove out of date comment.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 2/7] arc/gas: default mach is arc700, initialised in md_begin
2016-03-15 23:02 ` [PATCHv3 2/7] arc/gas: default mach is arc700, initialised in md_begin Andrew Burgess
@ 2016-03-18 9:58 ` Nick Clifton
0 siblings, 0 replies; 50+ messages in thread
From: Nick Clifton @ 2016-03-18 9:58 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Andreas Schwab
Hi Andrew,
> binutils/ChangeLog:
>
> * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700
> to the architecture list.
>
> gas/ChangeLog:
>
> * config/tc-arc.c (arc_target): Delay initialisation until
> arc_select_cpu.
> (arc_target_name): Likewise.
> (arc_features): Likewise.
> (arc_mach_type): Likewise.
> (cpu_types): Remove "all" entry.
> (arc_select_cpu): New function, most of the content is from...
> (md_parse_option): ... here. Call new arc_select_cpu.
> (md_begin): Call arc_select_cpu if needed, default is now arc700.
>
> include/ChangeLog:
>
> * opcode/arc.h (ARC_OPCODE_BASE): Delete.
>
> opcodes/ChangeLog:
>
> * arc-opc.c (BASE): Delete.
Approved - please apply.
(Note - to save space in emails, it is customary to omit the patch(es)
to ChangeLog entries. The text should already be in the body of the email
so there is no need to repeat the changes in the patch itself. Also,
given the pace at which the sources change, it is often impossible to
apply a patch to a ChangeLog entry without manual intervention).
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant.
2016-03-16 21:24 ` Andrew Burgess
@ 2016-03-18 9:59 ` Nick Clifton
0 siblings, 0 replies; 50+ messages in thread
From: Nick Clifton @ 2016-03-18 9:59 UTC (permalink / raw)
To: Andrew Burgess, Claudiu Zissulescu
Cc: binutils, Cupertino.Miranda, noamca, Andreas Schwab
Hi Andrew,
> bfd/ChangeLog:
>
> * elf32-arc.c (arc_elf_print_private_bfd_data): Remove use of
> EF_ARC_CPU_GENERIC.
> (arc_elf_final_write_processing): Don't bother setting cpu field
> in e_flags, this will have been set elsewhere.
>
> binutils/ChangeLog:
>
> * readelf.c (get_machine_flags): Move arc processing into...
> (decode_ARC_machine_flags): ... new function. Remove use of
> EF_ARC_CPU_GENERIC, change default case from "generic arc" to
> "unknown arc". Merged ABI printing between two machine types.
>
> gas/ChangeLog:
>
> * config/tc-arc.c (arc_select_cpu): Remove use of
> EF_ARC_CPU_GENERIC.
>
> include/ChangeLog:
>
> * elf/arc.h (EF_ARC_CPU_GENERIC): Delete. Update related comment.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 6/7] arc/opcodes: Use flag operand class to handle multiple flag matches
2016-03-15 23:02 ` [PATCHv3 6/7] arc/opcodes: Use flag operand class to handle multiple flag matches Andrew Burgess
2016-03-16 11:51 ` Claudiu Zissulescu
@ 2016-03-18 10:00 ` Nick Clifton
1 sibling, 0 replies; 50+ messages in thread
From: Nick Clifton @ 2016-03-18 10:00 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Andreas Schwab
Hi Andrew,
> gas/ChangeLog:
>
> * config/tc-arc.c (find_opcode_match): Move lnflg, and i
> declarations to start of block. Reset code on all flags before
> attempting to match them. Handle multiple hits on the same flag.
> Handle flag class.
> * testsuite/gas/arc/asm-errors.d: New file.
> * testsuite/gas/arc/asm-errors.err: New file.
> * testsuite/gas/arc/asm-errors.s: New file.
>
> include/ChangeLog:
>
> * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
> new classes instead.
>
> opcodes/ChangeLog:
>
> * arc-opc.c (arc_flag_classes): Convert all flag classes to use
> the new class enum values.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 7/7] arc/nps400: Add first nps400 instructions
2016-03-15 23:02 ` [PATCHv3 7/7] arc/nps400: Add first nps400 instructions Andrew Burgess
@ 2016-03-18 10:01 ` Nick Clifton
0 siblings, 0 replies; 50+ messages in thread
From: Nick Clifton @ 2016-03-18 10:01 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Andreas Schwab
Hi Andrew,
> gas/ChangeLog:
>
> * testsuite/gas/arc/nps400-0.d: New file.
> * testsuite/gas/arc/nps400-0.s: New file.
> * testsuite/gas/arc/nps400-1.d: New file.
> * testsuite/gas/arc/nps400-1.s: New file.
>
> include/ChangeLog:
>
> * opcodes/arc.h (insn_class_t): Add BITOP type.
>
> opcodes/ChangeLog:
>
> * arc-nps400-tbl.h: New file.
> * arc-opc.c: Add top level comment.
> (insert_nps_3bit_dst): New function.
> (extract_nps_3bit_dst): New function.
> (insert_nps_3bit_src2): New function.
> (extract_nps_3bit_src2): New function.
> (insert_nps_bitop_size): New function.
> (extract_nps_bitop_size): New function.
> (arc_flag_operands): Add nps400 entries.
> (arc_flag_classes): Add nps400 entries.
> (arc_operands): Add nps400 entries.
> (arc_opcodes): Add nps400 include.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag.
2016-03-16 21:27 ` Andrew Burgess
@ 2016-03-18 10:02 ` Nick Clifton
0 siblings, 0 replies; 50+ messages in thread
From: Nick Clifton @ 2016-03-18 10:02 UTC (permalink / raw)
To: Andrew Burgess, binutils
Cc: Claudiu.Zissulescu, Cupertino.Miranda, noamca, Andreas Schwab
Hi Andrew,
> bfd/ChangeLog:
>
> * archures.c (bfd_mach_arc_nps400): Define.
> * bfd-in2.h: Regenerate.
> * cpu-arc.c (arch_info_struct): New entry for nps400, renumber
> some existing entries to make space.
> * elf32-arc.c (arc_elf_object_p): Add nps400 case.
> (arc_elf_final_write_processing): Likewise.
>
> binutils/ChangeLog:
>
> * readelf.c (decode_ARC_machine_flags): Handle nps400.
>
> gas/ChangeLog:
>
> * config/tc-arc.c (cpu_types): Add nps400 entry.
> (check_zol): Handle nps400.
>
> include/ChangeLog:
>
> * elf/arc.h (E_ARC_MACH_NPS400): Define.
> * opcode/arc.h (ARC_OPCODE_NPS400): Define.
>
> opcodes/ChangeLog:
>
> * arc-dis.c (print_insn_arc): Handle nps400.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 50+ messages in thread
end of thread, other threads:[~2016-03-18 10:02 UTC | newest]
Thread overview: 50+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-25 23:39 [PATCH] gas/opcodes: Add initial arc nps400 support Andrew Burgess
2016-02-29 11:00 ` Claudiu Zissulescu
2016-03-01 15:15 ` Andrew Burgess
2016-03-01 20:53 ` Claudiu Zissulescu
2016-03-02 19:37 ` Andrew Burgess
2016-03-02 19:47 ` [PATCHv2 0/2] " Andrew Burgess
2016-03-02 19:47 ` [PATCHv2 2/2] gas/opcodes: " Andrew Burgess
2016-03-03 6:47 ` Claudiu Zissulescu
2016-03-15 13:20 ` Andreas Schwab
2016-03-15 13:50 ` Andrew Burgess
2016-03-15 14:05 ` Andreas Schwab
2016-03-15 15:53 ` Nick Clifton
2016-03-02 19:47 ` [PATCHv2 1/2] arc/gas: default mach is arc700, initialised in md_begin Andrew Burgess
2016-03-03 6:44 ` Claudiu Zissulescu
2016-03-05 21:24 ` Andrew Burgess
2016-03-11 20:13 ` PING: Re: [PATCHv2 0/2] Add initial arc nps400 support Andrew Burgess
2016-03-15 11:14 ` Nick Clifton
2016-03-15 11:38 ` Andrew Burgess
2016-03-15 12:48 ` Nick Clifton
2016-03-15 13:41 ` Andrew Burgess
2016-03-15 15:46 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 3/7] arc: Remove duplicated constant in include/elf/arc.h Andrew Burgess
2016-03-16 11:00 ` Claudiu Zissulescu
2016-03-18 9:58 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 7/7] arc/nps400: Add first nps400 instructions Andrew Burgess
2016-03-18 10:01 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 2/7] arc/gas: default mach is arc700, initialised in md_begin Andrew Burgess
2016-03-18 9:58 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 1/7] gas/arc: Fix test for big-endian arc Andrew Burgess
2016-03-16 10:56 ` Claudiu Zissulescu
2016-03-18 9:55 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 0/7] Add initial arc nps400 support Andrew Burgess
2016-03-17 16:15 ` Pedro Alves
2016-03-17 17:15 ` Andrew Burgess
2016-03-17 17:27 ` Pedro Alves
2016-03-15 23:02 ` [PATCHv3 6/7] arc/opcodes: Use flag operand class to handle multiple flag matches Andrew Burgess
2016-03-16 11:51 ` Claudiu Zissulescu
2016-03-18 10:00 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 5/7] arc: Add nps400 machine type, and assembler flag Andrew Burgess
2016-03-16 11:09 ` Claudiu Zissulescu
2016-03-16 11:23 ` Andrew Burgess
2016-03-16 11:27 ` Claudiu Zissulescu
2016-03-16 21:27 ` Andrew Burgess
2016-03-18 10:02 ` Nick Clifton
2016-03-15 23:02 ` [PATCHv3 4/7] arc: Remove EF_ARC_CPU_GENERIC constant Andrew Burgess
2016-03-16 11:06 ` Claudiu Zissulescu
2016-03-16 11:16 ` Andrew Burgess
2016-03-16 11:23 ` Claudiu Zissulescu
2016-03-16 21:24 ` Andrew Burgess
2016-03-18 9:59 ` Nick Clifton
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