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a=rsa-sha256; c=relaxed/relaxed; d=eagercon.com; s=dreamhost; t=1696619825; bh=tnafcdgAciOtq+I7uB0NF62zNcOnaYfklUboyLmellw=; h=Date:Subject:To:Cc:From:Content-Type:Content-Transfer-Encoding; b=rzQLZYoSkOFEabSZxvb0GEAriMMpDBbFxmBBywsvbraXZlFT4kZAlgLo6pCIZAonM m0AL/wq20ZIfhqxvTf0tLszGdDUBBBIv0SJjXPQVbXDcbRQrhlntlZXanEszOM47YF pD7QdfvLPVTxerbUGvH6tKKlTPtHtaSmFHHo6Hc/IrLKh0M415wU7lLzAUPqmgWSgn ntEkELpT8VWSu3egRwBS2oheKDTG367f65yb/XeZHyTtzoi2xmNh9kxzaICZxNtMJR qwUwZF92VNPAT/BDAWPPXxAOTwz6Fao124jD33Kh7b4E0Sq6ISFkCZEFWj9v3AqeZL VK8M+r3Qmij6Q== Message-ID: <5d2ce973-6287-db3d-fc82-966914f765a7@eagercon.com> Date: Fri, 6 Oct 2023 12:17:03 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v2 1/1] opcodes: microblaze: Add new bit-field instructions Content-Language: en-US To: Neal Frager , binutils@sourceware.org Cc: ibai.erkiaga-elorza@amd.com, nagaraju.mekala@amd.com, mark.hatle@amd.com, sadanand.mutyala@amd.com, appa.rao.nali@amd.com, vidhumouli.hunsigida@amd.com, luca.ceresoli@bootlin.com, nickc@redhat.com References: <20231005125103.1330807-1-neal.frager@amd.com> From: Michael Eager In-Reply-To: <20231005125103.1330807-1-neal.frager@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 10/5/23 05:51, Neal Frager via Binutils wrote: > This patches adds new bsefi and bsifi instructions. > BSEFI- The instruction shall extract a bit field from a > register and place it right-adjusted in the destination register. > The other bits in the destination register shall be set to zero. > BSIFI- The instruction shall insert a right-adjusted bit field > from a register at another position in the destination register. > The rest of the bits in the destination register shall be unchanged. > > Further documentation of these instructions can be found here: > https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref > > This patch has been tested for years of AMD Xilinx Yocto > releases as part of the following patch set: > > https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils > > Signed-off-by: nagaraju > Signed-off-by: Ibai Erkiaga > Signed-off-by: Neal Frager Committed. Please add test cases for these instructions. -- Michael Eager