From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 57331 invoked by alias); 5 Mar 2020 15:22:04 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 57316 invoked by uid 89); 5 Mar 2020 15:22:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-4.4 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx2.suse.de Received: from mx2.suse.de (HELO mx2.suse.de) (195.135.220.15) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 05 Mar 2020 15:22:02 +0000 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id A4232B028; Thu, 5 Mar 2020 15:22:00 +0000 (UTC) Subject: Re: [PATCH 1/9] x86: refine TPAUSE and UMWAIT To: "H.J. Lu" Cc: "binutils@sourceware.org" References: <3923caf7-f52b-a5d3-890f-4ffe312320e9@suse.com> <82ff27a0-e4a7-1f79-16a7-597563ceeb4c@suse.com> <6c6fdbc1-2de1-ec66-9c99-88f9cafde57c@suse.com> From: Jan Beulich Message-ID: <606a6c7d-a55a-eee6-3259-3131af142810@suse.com> Date: Thu, 05 Mar 2020 15:22:00 -0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2020-03/txt/msg00126.txt On 05.03.2020 15:04, H.J. Lu wrote: > On Thu, Mar 5, 2020 at 12:08 AM Jan Beulich wrote: >> >> On 04.03.2020 12:44, H.J. Lu wrote: >>> On Wed, Mar 4, 2020 at 3:40 AM Jan Beulich wrote: >>>> On 04.03.2020 12:36, H.J. Lu wrote: >>>>> On Wed, Mar 4, 2020 at 1:37 AM Jan Beulich wrote: >>>>>> Allowing 64-bit registers is misleading here: Elsewhere these get allowed >>>>>> when there's no difference between either variant, because of 32-bit >>>>>> destination registers having their upper halves zeroed in 64-bit mode. >>>>>> Here, however, they're source registers, and hence specifying 64-bit >>>>>> registers would lead to the ambiguity of whether the upper 32 bits >>>>>> actually matter. >>>>>> >>>>>> Additionally, for proper code generation in 16-bit mode, IgnoreSize is >>>>>> needed on both. >>>>> >>>>> Are there testcases to show IgnoreSize is needed on them? >>>> >>>> The situation with 16-bit test cases is rather poor anyway. I didn't >>>> consider it reasonable to add such very special ones when far more >>>> general ones don't exist. But if your question is to mean you demand >>> >>> Let's start from somewhere. >>> >>>> such to be added, then I'll (somewhat hesitantly) add/extend some. >>>> Please clarify. >>> >>> Please add testcases. >> >> Actually they were there, in patch 2. I've moved them to this patch >> and have just sent v1.1 for just this one patch. > > Do we need to adjust disassembler for 16-bit mode? I've checked now - no, we don't. Jan