From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12089 invoked by alias); 1 May 2019 17:05:18 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 12078 invoked by uid 89); 1 May 2019 17:05:17 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.8 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 May 2019 17:05:15 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2A38580D for ; Wed, 1 May 2019 10:05:14 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A21933F719 for ; Wed, 1 May 2019 10:05:13 -0700 (PDT) Subject: [PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsr To: binutils@sourceware.org References: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> From: "Andre Vieira (lists)" Message-ID: <6093cd14-e552-f897-ef5f-52b6ece89885@arm.com> Date: Wed, 01 May 2019 17:05:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> Content-Type: multipart/mixed; boundary="------------EE6CB9F03F3B9EFCE83B3DC6" X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00040.txt.bz2 This is a multi-part message in MIME format. --------------EE6CB9F03F3B9EFCE83B3DC6 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 768 Hi, This patch adds support for MVE instructions VADC, VSBC and VBRSR. gas/ChangeLog: 2019-05-01 Andre Vieira * config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr): New instruction encodings. (do_mve_vadc): New encoding instruction. (do_mve_vbrsr): Likewise. (do_mve_vsbc): Likewise. * testsuite/gas/arm/mve-vadc-bad.d: New test. * testsuite/gas/arm/mve-vadc-bad.l: New test. * testsuite/gas/arm/mve-vadc-bad.s: New test. * testsuite/gas/arm/mve-vbrsr-bad.d: New test. * testsuite/gas/arm/mve-vbrsr-bad.l: New test. * testsuite/gas/arm/mve-vbrsr-bad.s: New test. * testsuite/gas/arm/mve-vsbc-bad.d: New test. * testsuite/gas/arm/mve-vsbc-bad.l: New test. * testsuite/gas/arm/mve-vsbc-bad.s: New test. --------------EE6CB9F03F3B9EFCE83B3DC6 Content-Type: text/x-patch; name="11.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="11.patch" Content-length: 11365 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index b6ca4a48626f199347b7f1b2d281065198fd43ca..91754e3da9d500300443e28455ee6f248ded249b 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -14139,6 +14139,9 @@ do_t_loloop (void) #define M_MNEM_vmovlb 0xeea00f40 #define M_MNEM_vmovnt 0xfe311e81 #define M_MNEM_vmovnb 0xfe310e81 +#define M_MNEM_vadc 0xee300f00 +#define M_MNEM_vadci 0xee301f00 +#define M_MNEM_vbrsr 0xfe011e60 /* Neon instruction encoder helpers. */ @@ -16761,6 +16764,52 @@ do_neon_qdmulh (void) } } +static void +do_mve_vadc (void) +{ + enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); + struct neon_type_el et + = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK); + + if (et.type == NT_invtype) + first_error (BAD_EL_TYPE); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + mve_encode_qqq (0, 64); +} + +static void +do_mve_vbrsr (void) +{ + enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); + struct neon_type_el et + = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + mve_encode_qqr (et.size, 0); +} + +static void +do_mve_vsbc (void) +{ + neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + mve_encode_qqq (1, 64); +} + static void do_mve_vmull (void) { @@ -23911,6 +23960,10 @@ static const struct asm_opcode insns[] = ToC("vpsteee", fe712f4d, 0, (), mve_vpt), /* MVE and MVE FP only. */ + mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc), + mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc), + mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc), + mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc), mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull), mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav), mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav), @@ -23947,6 +24000,7 @@ static const struct asm_opcode insns[] = mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn), mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn), + mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr), #undef ARM_VARIANT #define ARM_VARIANT & fpu_vfp_ext_v1 diff --git a/gas/testsuite/gas/arm/mve-vadc-bad.d b/gas/testsuite/gas/arm/mve-vadc-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..81d95c2c57f970f833cc2059ddef5164948b85fd --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vadc-bad.d @@ -0,0 +1,5 @@ +#name: Bad MVE VADC instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vadc-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vadc-bad.l b/gas/testsuite/gas/arm/mve-vadc-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..ca1c3a579fa7ccbe803a7ea92407b4e594367433 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vadc-bad.l @@ -0,0 +1,31 @@ +[^:]*: Assembler messages: +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Error: bad type in SIMD instruction -- `vadc.i8 q0,q1,q2' +[^:]*:14: Error: bad type in SIMD instruction -- `vadc.i16 q0,q1,q2' +[^:]*:15: Error: bad type in SIMD instruction -- `vadc.i64 q0,q1,q2' +[^:]*:16: Error: bad type in SIMD instruction -- `vadc.f32 q0,q1,q2' +[^:]*:17: Error: bad type in SIMD instruction -- `vadci.i8 q0,q1,q2' +[^:]*:18: Error: bad type in SIMD instruction -- `vadci.i16 q0,q1,q2' +[^:]*:19: Error: bad type in SIMD instruction -- `vadci.i64 q0,q1,q2' +[^:]*:20: Error: bad type in SIMD instruction -- `vadci.f32 q0,q1,q2' +[^:]*:22: Error: syntax error -- `vadceq.i32 q0,q1,q2' +[^:]*:23: Error: syntax error -- `vadceq.i32 q0,q1,q2' +[^:]*:25: Error: syntax error -- `vadceq.i32 q0,q1,q2' +[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vadct.i32 q0,q1,q2' +[^:]*:28: Error: instruction missing MVE vector predication code -- `vadc.i32 q0,q1,q2' +[^:]*:30: Error: syntax error -- `vadcieq.i32 q0,q1,q2' +[^:]*:31: Error: syntax error -- `vadcieq.i32 q0,q1,q2' +[^:]*:33: Error: syntax error -- `vadcieq.i32 q0,q1,q2' +[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vadcit.i32 q0,q1,q2' +[^:]*:36: Error: instruction missing MVE vector predication code -- `vadci.i32 q0,q1,q2' diff --git a/gas/testsuite/gas/arm/mve-vadc-bad.s b/gas/testsuite/gas/arm/mve-vadc-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..6627c9e54f081c2f7811ce15072dc0839f3739cb --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vadc-bad.s @@ -0,0 +1,36 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +.irp mnem, vadc.i32, vadci.i32 +it \cond +\mnem q0, q1, q2 +.endr +.endr +.endm + +.syntax unified +.thumb +cond +vadc.i8 q0, q1, q2 +vadc.i16 q0, q1, q2 +vadc.i64 q0, q1, q2 +vadc.f32 q0, q1, q2 +vadci.i8 q0, q1, q2 +vadci.i16 q0, q1, q2 +vadci.i64 q0, q1, q2 +vadci.f32 q0, q1, q2 +it eq +vadceq.i32 q0, q1, q2 +vadceq.i32 q0, q1, q2 +vpst +vadceq.i32 q0, q1, q2 +vadct.i32 q0, q1, q2 +vpst +vadc.i32 q0, q1, q2 +it eq +vadcieq.i32 q0, q1, q2 +vadcieq.i32 q0, q1, q2 +vpst +vadcieq.i32 q0, q1, q2 +vadcit.i32 q0, q1, q2 +vpst +vadci.i32 q0, q1, q2 diff --git a/gas/testsuite/gas/arm/mve-vbrsr-bad.d b/gas/testsuite/gas/arm/mve-vbrsr-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..b4fc21aba00d159293ba9a9656060a2f612ccf25 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vbrsr-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VBRSR instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vbrsr-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vbrsr-bad.l b/gas/testsuite/gas/arm/mve-vbrsr-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..d0b8de9178e2f74eff436f53c5f69411403d1922 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vbrsr-bad.l @@ -0,0 +1,14 @@ +[^:]*: Assembler messages: +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Error: bad type in SIMD instruction -- `vbrsr.64 q0,q1,r2' +[^:]*:12: Error: ARM register expected -- `vbrsr.32 q0,q1,q2' +[^:]*:14: Error: syntax error -- `vbrsreq.32 q0,q1,r2' +[^:]*:15: Error: syntax error -- `vbrsreq.32 q0,q1,r2' +[^:]*:17: Error: syntax error -- `vbrsreq.32 q0,q1,r2' +[^:]*:19: Error: instruction missing MVE vector predication code -- `vbrsr.32 q0,q1,r2' +[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vbrsrt.32 q0,q1,r2' diff --git a/gas/testsuite/gas/arm/mve-vbrsr-bad.s b/gas/testsuite/gas/arm/mve-vbrsr-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..af02bd941d721d6b1be27953746260038892b6fd --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vbrsr-bad.s @@ -0,0 +1,20 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vbrsr.16 q0, q1, r2 +.endr +.endm + +.syntax unified +.thumb +cond +vbrsr.64 q0, q1, r2 +vbrsr.32 q0, q1, q2 +it eq +vbrsreq.32 q0, q1, r2 +vbrsreq.32 q0, q1, r2 +vpst +vbrsreq.32 q0, q1, r2 +vpst +vbrsr.32 q0, q1, r2 +vbrsrt.32 q0, q1, r2 diff --git a/gas/testsuite/gas/arm/mve-vsbc-bad.d b/gas/testsuite/gas/arm/mve-vsbc-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..29186c1cac47f2d35068a00d026ab6858fc84eda --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vsbc-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VSBC instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vsbc-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vsbc-bad.l b/gas/testsuite/gas/arm/mve-vsbc-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..e730751262dd0d3765a8bd6d1947a724a3236979 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vsbc-bad.l @@ -0,0 +1,25 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vsbc.i16 q0,q1,q2' +[^:]*:11: Error: bad type in SIMD instruction -- `vsbci.i16 q0,q1,q2' +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Error: syntax error -- `vsbceq.i32 q0,q1,q2' +[^:]*:16: Error: syntax error -- `vsbceq.i32 q0,q1,q2' +[^:]*:18: Error: syntax error -- `vsbceq.i32 q0,q1,q2' +[^:]*:20: Error: instruction missing MVE vector predication code -- `vsbc.i32 q0,q1,q2' +[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vsbct.i32 q0,q1,q2' +[^:]*:23: Error: syntax error -- `vsbcieq.i32 q0,q1,q2' +[^:]*:24: Error: syntax error -- `vsbcieq.i32 q0,q1,q2' +[^:]*:26: Error: syntax error -- `vsbcieq.i32 q0,q1,q2' +[^:]*:28: Error: instruction missing MVE vector predication code -- `vsbci.i32 q0,q1,q2' +[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vsbcit.i32 q0,q1,q2' diff --git a/gas/testsuite/gas/arm/mve-vsbc-bad.s b/gas/testsuite/gas/arm/mve-vsbc-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..869ba6e228bdd21b6f9282b62447e66a3c7adb81 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vsbc-bad.s @@ -0,0 +1,29 @@ +.macro cond op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().i32 q0, q1, q2 +.endr +.endm + +.syntax unified +.thumb +vsbc.i16 q0, q1, q2 +vsbci.i16 q0, q1, q2 +cond vsbc +cond vsbci +it eq +vsbceq.i32 q0, q1, q2 +vsbceq.i32 q0, q1, q2 +vpst +vsbceq.i32 q0, q1, q2 +vpst +vsbc.i32 q0, q1, q2 +vsbct.i32 q0, q1, q2 +it eq +vsbcieq.i32 q0, q1, q2 +vsbcieq.i32 q0, q1, q2 +vpst +vsbcieq.i32 q0, q1, q2 +vpst +vsbci.i32 q0, q1, q2 +vsbcit.i32 q0, q1, q2 --------------EE6CB9F03F3B9EFCE83B3DC6--