From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 6D6EA3858002 for ; Wed, 18 May 2022 09:31:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6D6EA3858002 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id C613D300089; Wed, 18 May 2022 09:31:01 +0000 (UTC) Message-ID: <60d3cc0a-1a49-b66c-c72e-69fb32babf43@irq.a4lg.com> Date: Wed, 18 May 2022 18:31:00 +0900 Mime-Version: 1.0 Subject: Re: [RFC PATCH 0/5] RISC-V: Add Half-precision floating point extensions Content-Language: en-US To: Kito Cheng , Nelson Chu Cc: Binutils References: From: Tsukasa OI In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-6.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 May 2022 09:31:08 -0000 Hi Kito, Thanks for letting me know. I think I can rebase or port my work to Nelson's implementation. Hi Nelson, It's good to know that you implemented Zfh. I think I can port my Zfhmin patch and testcases based on your work. My original submission did not contain floating point data pseudo-op in the assembler (like F, D and Q) and I didn't know .float, .single and .double are already available on GAS (non arch-specific). Since .float16 is currently RISC-V+GNU-specific, it would be nicer if we have discussion on ... for instance, riscv-asm-manual. Best Regards, Tsukasa On 2022/05/18 10:43, Kito Cheng wrote: > HI Tsukasa: > > Nelson has ported his zfh implementation from integration branch to > trunk, did you mind base that on to adding zfhmin? > > On Tue, Jan 11, 2022 at 6:48 PM Tsukasa OI via Binutils > wrote: >> >> This patchset adds support for two recently ratified RISC-V extensions: >> >> - Zfhmin (Half-precision floating point: conversion only) >> - Zfh (Half-precision floating point: full arithmetic) >> >> This patchset was intended to be a part of Binutils 2.38 but I was >> getting too impatient. I tested this patchset with Spike simulator and >> tested that a few programs with fp16 was working nicely. However, this >> patchset lacks full testsuite. >> >> The only reason I didn't make one was simple: all of floating point >> extensions ('F', 'D' and 'Q') didn't have full testsuite. Thanks to the >> fact that this patchset is too late for Binutils 2.38, we have time to >> add full testsuite for all floating point extensions. >> >> Also, this patchset lacks pseudoinstructions (intentionally). Possible >> pseudoinstructions to implement later would be: >> >> - fmv.h >> - fneg.h >> - fabs.h >> >> Besides that, we can begin testing 'Zfh' and 'Zfhmin' extensions with >> this patchset. >> >> >> >> >> Tsukasa OI (5): >> RISC-V: Add 'Zfh' and 'Zfhmin' extensions >> RISC-V: Add insn classes for Zfh/Zfhmin extensions >> RISC-V: Add 'Zfh' and 'Zfhmin' instructions >> RISC-V: Add 'flh' and 'fsh' macro instructions >> RISC-V: Add 'Zfh'/'Zfhmin' conflict message >> >> bfd/elfxx-riscv.c | 16 +++++- >> gas/config/tc-riscv.c | 10 ++++ >> include/opcode/riscv-opc.h | 108 +++++++++++++++++++++++++++++++++++++ >> include/opcode/riscv.h | 6 +++ >> opcodes/riscv-opc.c | 62 +++++++++++++++++++++ >> 5 files changed, 201 insertions(+), 1 deletion(-) >> >> >> base-commit: 9ed5be5650ba7c315cd7cfacccc9208de2f555df >> -- >> 2.32.0 >> >