From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id DFA0F3858D28 for ; Wed, 30 Aug 2023 02:48:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DFA0F3858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 7F6BC300089; Wed, 30 Aug 2023 02:48:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1693363702; bh=Zx1oyPE9gYyRvVko8OQrLDIpvVs7RK1d+0aBx6PZHH4=; h=Message-ID:Date:Mime-Version:Subject:To:References:Cc:From: In-Reply-To:Content-Type:Content-Transfer-Encoding; b=XrV8nXrePivQEc8ZAcYk/qocZz6U3hhVO0vOxnnwOQJaevXGIZrCmAmm4Tde8f6Z0 obyVBUJ1hz3cioavK3bpFJG55a+6AaDGvQNXhIAT1QypU1aLZFeLBNSSB0TGpZKosP FzpNp+KTnboRNFCHAQMdB8gicdstgj81o4gaKz7k= Message-ID: <611f69c2-1486-4cb3-bdfa-f0f73a3dbbf1@irq.a4lg.com> Date: Wed, 30 Aug 2023 11:48:22 +0900 Mime-Version: 1.0 Subject: Re: [PATCH 1/1] RISC-V: Make XVentanaCondOps RV64 only Content-Language: en-US To: Nelson Chu References: <0af2c2372b816ba128cef7165227d905e419357a.1693359513.git.research_trasio@irq.a4lg.com> Cc: Binutils From: Tsukasa OI In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 2023/08/30 11:45, Nelson Chu wrote: > OKay, thanks. > > Nelson Approve confirmed. Just to make sure, I'll wait for a few days (for feedback from Ventana) before merging. Thanks, Tsukasa > > On Wed, Aug 30, 2023 at 9:38 AM Tsukasa OI > wrote: > > From: Tsukasa OI > > > Although XVentanaCondOps instructions are XLEN-agonistic, Ventana's > manual > only defines them only for RV64 (because all Ventana's processors > implement > RV64). > > This commit limits XVentanaCondOps instructions RV64-only to match the > behavior of the manual and LLVM. > > Note that this commit alone will not make XVentanaCondOps extension with > RV32 invalid (it just makes XVentanaCondOps on RV32 empty). > > opcodes/ChangeLog: > >         * riscv-opc.c (riscv_opcodes): Restrict "vt.maskc" and > "vt.maskcn" >         to XLEN=64. > > gas/ChangeLog: > >         * testsuite/gas/riscv/x-ventana-condops-32.d: New failure test. >         * testsuite/gas/riscv/x-ventana-condops-32.l: Likewise. > --- >  gas/testsuite/gas/riscv/x-ventana-condops-32.d | 3 +++ >  gas/testsuite/gas/riscv/x-ventana-condops-32.l | 3 +++ >  opcodes/riscv-opc.c                            | 4 ++-- >  3 files changed, 8 insertions(+), 2 deletions(-) >  create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops-32.d >  create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops-32.l > > diff --git a/gas/testsuite/gas/riscv/x-ventana-condops-32.d > b/gas/testsuite/gas/riscv/x-ventana-condops-32.d > new file mode 100644 > index 000000000000..ea67515da0e3 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/x-ventana-condops-32.d > @@ -0,0 +1,3 @@ > +#as: -march=rv32i_xventanacondops > +#source: x-ventana-condops.s > +#error_output: x-ventana-condops-32.l > diff --git a/gas/testsuite/gas/riscv/x-ventana-condops-32.l > b/gas/testsuite/gas/riscv/x-ventana-condops-32.l > new file mode 100644 > index 000000000000..e434caf15f60 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/x-ventana-condops-32.l > @@ -0,0 +1,3 @@ > +.*Assembler messages: > +.*Error: unrecognized opcode `vt.maskc a0,a1,a2' > +.*Error: unrecognized opcode `vt.maskcn a0,a3,a4' > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 067e9fdb611f..f5416605dcc3 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -2174,8 +2174,8 @@ const struct riscv_opcode riscv_opcodes[] = >  {"th.sync.s",        0, INSN_CLASS_XTHEADSYNC,  "",  >  MATCH_TH_SYNC_S,        MASK_TH_SYNC_S,        match_opcode, 0}, > >  /* Vendor-specific (Ventana Microsystems) XVentanaCondOps > instructions */ > -{"vt.maskc",    0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", > MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, > -{"vt.maskcn",   0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", > MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, > +{"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", > MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, > +{"vt.maskcn",  64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", > MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, > >  /* Terminate the list.  */ >  {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} > -- > 2.42.0 >