From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9200 invoked by alias); 1 May 2019 17:32:52 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 9185 invoked by uid 89); 1 May 2019 17:32:51 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.4 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 May 2019 17:32:48 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 68D6780D for ; Wed, 1 May 2019 10:32:47 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E20ED3F719 for ; Wed, 1 May 2019 10:32:46 -0700 (PDT) Subject: [PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb] To: binutils@sourceware.org References: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> From: "Andre Vieira (lists)" Message-ID: <61943cb3-4edc-562d-f467-a97ce4786073@arm.com> Date: Wed, 01 May 2019 17:32:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> Content-Type: multipart/mixed; boundary="------------F8F3C5E25A88FFF9C854CE63" X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00061.txt.bz2 This is a multi-part message in MIME format. --------------F8F3C5E25A88FFF9C854CE63 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 884 Hi, This patch adds support for MVE instructions VSHRNT, VSHRNB, VRSHRNT, VRSHRNB, VQSHRUNT, VQSHRUNT, VQRSHRNT, VQRSHRNB, VQRSHRUNT, and VQRSHRUNB. gas/ChangeLog: 2019-05-01 Andre Vieira * config/tc-arm.c (M_MNEM_vshrnt, M_MNEM_vshrnb, M_MNEM_vrshrnt, M_MNEM_vqshrnt, M_MNEM_vqshrnb, M_MNEM_vqshrunt, M_MNEM_vqshrunb, M_MNEM_vrshrnb, M_MNEM_vqrshrnt, M_MNEM_vqrshrnb, M_MNEM_vqrshrunt, M_MNEM_vqrshrunb): New instruction encodings. (do_mve_vshrn): New encoding function. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vqrshrn-bad.d: New test. * testsuite/gas/arm/mve-vqrshrn-bad.l: New test. * testsuite/gas/arm/mve-vqrshrn-bad.s: New test. * testsuite/gas/arm/mve-vshrn-bad.d: New test. * testsuite/gas/arm/mve-vshrn-bad.l: New test. * testsuite/gas/arm/mve-vshrn-bad.s: New test. --------------F8F3C5E25A88FFF9C854CE63 Content-Type: text/x-patch; name="31.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="31.patch" Content-length: 17347 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 9cf70bfe5f9c8bbe3445ad4b07d1a5d1f02de32b..af7723f8ba5577156544166a392a3a94b26bcdb5 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -14209,6 +14209,18 @@ do_t_loloop (void) #define M_MNEM_vqmovnb 0xee330e01 #define M_MNEM_vqmovunt 0xee311e81 #define M_MNEM_vqmovunb 0xee310e81 +#define M_MNEM_vshrnt 0xee801fc1 +#define M_MNEM_vshrnb 0xee800fc1 +#define M_MNEM_vrshrnt 0xfe801fc1 +#define M_MNEM_vqshrnt 0xee801f40 +#define M_MNEM_vqshrnb 0xee800f40 +#define M_MNEM_vqshrunt 0xee801fc0 +#define M_MNEM_vqshrunb 0xee800fc0 +#define M_MNEM_vrshrnb 0xfe800fc1 +#define M_MNEM_vqrshrnt 0xee801f41 +#define M_MNEM_vqrshrnb 0xee800f41 +#define M_MNEM_vqrshrunt 0xfe801fc0 +#define M_MNEM_vqrshrunb 0xfe800fc0 /* Neon instruction encoder helpers. */ @@ -15753,6 +15765,58 @@ do_mve_vmlas (void) inst.is_neon = 1; } +static void +do_mve_vshrn (void) +{ + unsigned types; + switch (inst.instruction) + { + case M_MNEM_vshrnt: + case M_MNEM_vshrnb: + case M_MNEM_vrshrnt: + case M_MNEM_vrshrnb: + types = N_I16 | N_I32; + break; + case M_MNEM_vqshrnt: + case M_MNEM_vqshrnb: + case M_MNEM_vqrshrnt: + case M_MNEM_vqrshrnb: + types = N_U16 | N_U32 | N_S16 | N_S32; + break; + case M_MNEM_vqshrunt: + case M_MNEM_vqshrunb: + case M_MNEM_vqrshrunt: + case M_MNEM_vqrshrunb: + types = N_S16 | N_S32; + break; + default: + abort (); + } + + struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + unsigned Qd = inst.operands[0].reg; + unsigned Qm = inst.operands[1].reg; + unsigned imm = inst.operands[2].imm; + constraint (imm < 1 || ((unsigned) imm) > (et.size / 2), + et.size == 16 + ? _("immediate operand expected in the range [1,8]") + : _("immediate operand expected in the range [1,16]")); + + inst.instruction |= (et.type == NT_unsigned) << 28; + inst.instruction |= HI1 (Qd) << 22; + inst.instruction |= (et.size - imm) << 16; + inst.instruction |= LOW4 (Qd) << 12; + inst.instruction |= HI1 (Qm) << 5; + inst.instruction |= LOW4 (Qm); + inst.is_neon = 1; +} + static void do_mve_vqmovn (void) { @@ -24949,6 +25013,19 @@ static const struct asm_opcode insns[] = mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn), mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn), + mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn), + mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn), + #undef THUMB_VARIANT #define THUMB_VARIANT & mve_fp_ext mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul), diff --git a/gas/testsuite/gas/arm/mve-vqrshrn-bad.d b/gas/testsuite/gas/arm/mve-vqrshrn-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..6673336252e16c3bf90fbb580af3a2f663d1194c --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vqrshrn-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VQRSHRNT, VQRSHRNB, VQRHSRUNT and MVQRSHRUNB instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vqrshrn-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vqrshrn-bad.l b/gas/testsuite/gas/arm/mve-vqrshrn-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..df4f79f836ef389ef9650b1a1567cea1b4086428 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vqrshrn-bad.l @@ -0,0 +1,71 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vqrshrnt.s8 q0,q1,#1' +[^:]*:11: Error: bad type in SIMD instruction -- `vqrshrnt.s64 q0,q1,#1' +[^:]*:12: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnt.s16 q0,q1,#0' +[^:]*:13: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnt.s16 q0,q1,#9' +[^:]*:14: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnt.s32 q0,q1,#0' +[^:]*:15: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnt.s32 q0,q1,#17' +[^:]*:16: Error: bad type in SIMD instruction -- `vqrshrnb.s8 q0,q1,#1' +[^:]*:17: Error: bad type in SIMD instruction -- `vqrshrnb.s64 q0,q1,#1' +[^:]*:18: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnb.s16 q0,q1,#0' +[^:]*:19: Error: immediate operand expected in the range \[1,8\] -- `vqrshrnb.s16 q0,q1,#9' +[^:]*:20: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnb.s32 q0,q1,#0' +[^:]*:21: Error: immediate operand expected in the range \[1,16\] -- `vqrshrnb.s32 q0,q1,#17' +[^:]*:22: Error: bad type in SIMD instruction -- `vqrshrunt.s8 q0,q1,#1' +[^:]*:23: Error: bad type in SIMD instruction -- `vqrshrunt.s64 q0,q1,#1' +[^:]*:24: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunt.s16 q0,q1,#0' +[^:]*:25: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunt.s16 q0,q1,#9' +[^:]*:26: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunt.s32 q0,q1,#0' +[^:]*:27: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunt.s32 q0,q1,#17' +[^:]*:28: Error: bad type in SIMD instruction -- `vqrshrunt.u16 q0,q1,#1' +[^:]*:29: Error: bad type in SIMD instruction -- `vqrshrunb.s8 q0,q1,#1' +[^:]*:30: Error: bad type in SIMD instruction -- `vqrshrunb.s64 q0,q1,#1' +[^:]*:31: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunb.s16 q0,q1,#0' +[^:]*:32: Error: immediate operand expected in the range \[1,8\] -- `vqrshrunb.s16 q0,q1,#9' +[^:]*:33: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunb.s32 q0,q1,#0' +[^:]*:34: Error: immediate operand expected in the range \[1,16\] -- `vqrshrunb.s32 q0,q1,#17' +[^:]*:35: Error: bad type in SIMD instruction -- `vqrshrunb.u16 q0,q1,#1' +[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:41: Error: syntax error -- `vqrshrnteq.s16 q0,q1,#1' +[^:]*:42: Error: syntax error -- `vqrshrnteq.s16 q0,q1,#1' +[^:]*:44: Error: syntax error -- `vqrshrnteq.s16 q0,q1,#1' +[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshrntt.s16 q0,q1,#1' +[^:]*:47: Error: instruction missing MVE vector predication code -- `vqrshrnt.s16 q0,q1,#1' +[^:]*:49: Error: syntax error -- `vqrshrnbeq.s16 q0,q1,#1' +[^:]*:50: Error: syntax error -- `vqrshrnbeq.s16 q0,q1,#1' +[^:]*:52: Error: syntax error -- `vqrshrnbeq.s16 q0,q1,#1' +[^:]*:53: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshrnbt.s16 q0,q1,#1' +[^:]*:55: Error: instruction missing MVE vector predication code -- `vqrshrnb.s16 q0,q1,#1' +[^:]*:57: Error: syntax error -- `vqrshrunteq.s16 q0,q1,#1' +[^:]*:58: Error: syntax error -- `vqrshrunteq.s16 q0,q1,#1' +[^:]*:60: Error: syntax error -- `vqrshrunteq.s16 q0,q1,#1' +[^:]*:61: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshruntt.s16 q0,q1,#1' +[^:]*:63: Error: instruction missing MVE vector predication code -- `vqrshrunt.s16 q0,q1,#1' +[^:]*:65: Error: syntax error -- `vqrshrunbeq.s16 q0,q1,#1' +[^:]*:66: Error: syntax error -- `vqrshrunbeq.s16 q0,q1,#1' +[^:]*:68: Error: syntax error -- `vqrshrunbeq.s16 q0,q1,#1' +[^:]*:69: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshrunbt.s16 q0,q1,#1' +[^:]*:71: Error: instruction missing MVE vector predication code -- `vqrshrunb.s16 q0,q1,#1' diff --git a/gas/testsuite/gas/arm/mve-vqrshrn-bad.s b/gas/testsuite/gas/arm/mve-vqrshrn-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..1905943b4649066fa3af31de12ec48cd5dfed00e --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vqrshrn-bad.s @@ -0,0 +1,71 @@ +.macro cond op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s16 q0, q0, #1 +.endr +.endm + +.syntax unified +.thumb +vqrshrnt.s8 q0, q1, #1 +vqrshrnt.s64 q0, q1, #1 +vqrshrnt.s16 q0, q1, #0 +vqrshrnt.s16 q0, q1, #9 +vqrshrnt.s32 q0, q1, #0 +vqrshrnt.s32 q0, q1, #17 +vqrshrnb.s8 q0, q1, #1 +vqrshrnb.s64 q0, q1, #1 +vqrshrnb.s16 q0, q1, #0 +vqrshrnb.s16 q0, q1, #9 +vqrshrnb.s32 q0, q1, #0 +vqrshrnb.s32 q0, q1, #17 +vqrshrunt.s8 q0, q1, #1 +vqrshrunt.s64 q0, q1, #1 +vqrshrunt.s16 q0, q1, #0 +vqrshrunt.s16 q0, q1, #9 +vqrshrunt.s32 q0, q1, #0 +vqrshrunt.s32 q0, q1, #17 +vqrshrunt.u16 q0, q1, #1 +vqrshrunb.s8 q0, q1, #1 +vqrshrunb.s64 q0, q1, #1 +vqrshrunb.s16 q0, q1, #0 +vqrshrunb.s16 q0, q1, #9 +vqrshrunb.s32 q0, q1, #0 +vqrshrunb.s32 q0, q1, #17 +vqrshrunb.u16 q0, q1, #1 +cond vqrshrnt +cond vqrshrnb +cond vqrshrunt +cond vqrshrunb +it eq +vqrshrnteq.s16 q0, q1, #1 +vqrshrnteq.s16 q0, q1, #1 +vpst +vqrshrnteq.s16 q0, q1, #1 +vqrshrntt.s16 q0, q1, #1 +vpst +vqrshrnt.s16 q0, q1, #1 +it eq +vqrshrnbeq.s16 q0, q1, #1 +vqrshrnbeq.s16 q0, q1, #1 +vpst +vqrshrnbeq.s16 q0, q1, #1 +vqrshrnbt.s16 q0, q1, #1 +vpst +vqrshrnb.s16 q0, q1, #1 +it eq +vqrshrunteq.s16 q0, q1, #1 +vqrshrunteq.s16 q0, q1, #1 +vpst +vqrshrunteq.s16 q0, q1, #1 +vqrshruntt.s16 q0, q1, #1 +vpst +vqrshrunt.s16 q0, q1, #1 +it eq +vqrshrunbeq.s16 q0, q1, #1 +vqrshrunbeq.s16 q0, q1, #1 +vpst +vqrshrunbeq.s16 q0, q1, #1 +vqrshrunbt.s16 q0, q1, #1 +vpst +vqrshrunb.s16 q0, q1, #1 diff --git a/gas/testsuite/gas/arm/mve-vshrn-bad.d b/gas/testsuite/gas/arm/mve-vshrn-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..d63fa6f8e27da537f1a1f8444dd7ddf81248427c --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vshrn-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VSHRN and VRSHRN instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vshrn-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vshrn-bad.l b/gas/testsuite/gas/arm/mve-vshrn-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..51bbf30d31c670056f26f39b7185d65640d097a3 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vshrn-bad.l @@ -0,0 +1,57 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vshrnt.i64 q0,q1,#1' +[^:]*:11: Error: bad type in SIMD instruction -- `vshrnb.i64 q0,q1,#1' +[^:]*:12: Error: bad type in SIMD instruction -- `vrshrnt.i64 q0,q1,#1' +[^:]*:13: Error: bad type in SIMD instruction -- `vrshrnb.i64 q0,q1,#1' +[^:]*:14: Error: immediate operand expected in the range \[1,8\] -- `vshrnt.i16 q0,q1,#0' +[^:]*:15: Error: immediate operand expected in the range \[1,8\] -- `vshrnt.i16 q0,q1,#9' +[^:]*:16: Error: immediate operand expected in the range \[1,16\] -- `vshrnt.i32 q0,q1,#0' +[^:]*:17: Error: immediate operand expected in the range \[1,16\] -- `vshrnt.i32 q0,q1,#17' +[^:]*:18: Error: immediate operand expected in the range \[1,8\] -- `vshrnb.i16 q0,q1,#0' +[^:]*:19: Error: immediate operand expected in the range \[1,8\] -- `vshrnb.i16 q0,q1,#9' +[^:]*:20: Error: immediate operand expected in the range \[1,16\] -- `vshrnb.i32 q0,q1,#0' +[^:]*:21: Error: immediate operand expected in the range \[1,16\] -- `vshrnb.i32 q0,q1,#17' +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:27: Error: syntax error -- `vshrnteq.i32 q0,q1,#1' +[^:]*:28: Error: syntax error -- `vshrnteq.i32 q0,q1,#1' +[^:]*:30: Error: syntax error -- `vshrnteq.i32 q0,q1,#1' +[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vshrntt.i32 q0,q1,#1' +[^:]*:33: Error: instruction missing MVE vector predication code -- `vshrnt.i32 q0,q1,#1' +[^:]*:35: Error: syntax error -- `vshrnbeq.i32 q0,q1,#1' +[^:]*:36: Error: syntax error -- `vshrnbeq.i32 q0,q1,#1' +[^:]*:38: Error: syntax error -- `vshrnbeq.i32 q0,q1,#1' +[^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vshrnbt.i32 q0,q1,#1' +[^:]*:41: Error: instruction missing MVE vector predication code -- `vshrnb.i32 q0,q1,#1' +[^:]*:43: Error: syntax error -- `vrshrnteq.i32 q0,q1,#1' +[^:]*:44: Error: syntax error -- `vrshrnteq.i32 q0,q1,#1' +[^:]*:46: Error: syntax error -- `vrshrnteq.i32 q0,q1,#1' +[^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vrshrntt.i32 q0,q1,#1' +[^:]*:49: Error: instruction missing MVE vector predication code -- `vrshrnt.i32 q0,q1,#1' +[^:]*:51: Error: syntax error -- `vrshrnbeq.i32 q0,q1,#1' +[^:]*:52: Error: syntax error -- `vrshrnbeq.i32 q0,q1,#1' +[^:]*:54: Error: syntax error -- `vrshrnbeq.i32 q0,q1,#1' +[^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vrshrnbt.i32 q0,q1,#1' +[^:]*:57: Error: instruction missing MVE vector predication code -- `vrshrnb.i32 q0,q1,#1' diff --git a/gas/testsuite/gas/arm/mve-vshrn-bad.s b/gas/testsuite/gas/arm/mve-vshrn-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..5faa09865f0ebdca16b6f8c2c47d04629ae0cc0f --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vshrn-bad.s @@ -0,0 +1,57 @@ +.macro cond op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().i32 q0, q1, #1 +.endr +.endm + +.syntax unified +.thumb +vshrnt.i64 q0, q1, #1 +vshrnb.i64 q0, q1, #1 +vrshrnt.i64 q0, q1, #1 +vrshrnb.i64 q0, q1, #1 +vshrnt.i16 q0, q1, #0 +vshrnt.i16 q0, q1, #9 +vshrnt.i32 q0, q1, #0 +vshrnt.i32 q0, q1, #17 +vshrnb.i16 q0, q1, #0 +vshrnb.i16 q0, q1, #9 +vshrnb.i32 q0, q1, #0 +vshrnb.i32 q0, q1, #17 +cond vshrnt +cond vshrnb +cond vrshrnt +cond vrshrnb +it eq +vshrnteq.i32 q0, q1, #1 +vshrnteq.i32 q0, q1, #1 +vpst +vshrnteq.i32 q0, q1, #1 +vshrntt.i32 q0, q1, #1 +vpst +vshrnt.i32 q0, q1, #1 +it eq +vshrnbeq.i32 q0, q1, #1 +vshrnbeq.i32 q0, q1, #1 +vpst +vshrnbeq.i32 q0, q1, #1 +vshrnbt.i32 q0, q1, #1 +vpst +vshrnb.i32 q0, q1, #1 +it eq +vrshrnteq.i32 q0, q1, #1 +vrshrnteq.i32 q0, q1, #1 +vpst +vrshrnteq.i32 q0, q1, #1 +vrshrntt.i32 q0, q1, #1 +vpst +vrshrnt.i32 q0, q1, #1 +it eq +vrshrnbeq.i32 q0, q1, #1 +vrshrnbeq.i32 q0, q1, #1 +vpst +vrshrnbeq.i32 q0, q1, #1 +vrshrnbt.i32 q0, q1, #1 +vpst +vrshrnb.i32 q0, q1, #1 --------------F8F3C5E25A88FFF9C854CE63--