* Re:[PATCH 0/3] RISC-V: Support CORE-V XCVELW, XCVBI and XCVMEM extensions
@ 2024-06-09 12:56 yulong
0 siblings, 0 replies; only message in thread
From: yulong @ 2024-06-09 12:56 UTC (permalink / raw)
To: mary.bennett682; +Cc: binutils
>This patch series presents the comprehensive implementation of the
ELW, BI and
>MEM extensions for CORE-V.
>
>Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
>ensure its correctness and compatibility with the existing codebase.
>However, your input, reviews, and suggestions are invaluable in making
this
>extension even more robust.
>
>The CORE-V instructions are described in the specification [1] and
work can be
>found in the OpenHW group's Github repository [2].
>
>[1]
docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
>
>[2] github.com/openhwgroup/corev-binutils-gdb
>
>Contributors:
> Mary Bennett <mary.bennett682@gmail.com>
> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Pietra Ferreira <pietra.ferreira@embecosm.com>
> Charlie Keaney
> Jessica Mills
> Craig Blackmore <craig.blackmore@embecosm.com>
> Simon Cook <simon.cook@embecosm.com>
> Jeremy Bennett <jeremy.bennett@embecosm.com>
> Helene Chelin <helene.chelin@embecosm.com>
> Nazareno Bruschi <nazareno.bruschi@embecosm.com>
> Lin Sinan
>
>
>RISC-V: Add support for XCVelw extension in CV32E40P
>RISC-V: Add support for XCVbi extension in CV32E40P
>RISC-V: Add support for XCVmem extension in CV32E40P
>
>
> bfd/elfxx-riscv.c | 15 +++++
> gas/config/tc-riscv.c | 12 +++-
> gas/doc/c-riscv.texi | 15 +++++
> gas/testsuite/gas/riscv/cv-bi-beqimm.d | 12 ++++
> gas/testsuite/gas/riscv/cv-bi-beqimm.s | 4 ++
> gas/testsuite/gas/riscv/cv-bi-bneimm.d | 12 ++++
> gas/testsuite/gas/riscv/cv-bi-bneimm.s | 4 ++
> gas/testsuite/gas/riscv/cv-bi-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-bi-fail-march.l | 3 +
> gas/testsuite/gas/riscv/cv-bi-fail-march.s | 5 ++
> .../gas/riscv/cv-bi-fail-operand-01.d | 3 +
> .../gas/riscv/cv-bi-fail-operand-01.l | 3 +
> .../gas/riscv/cv-bi-fail-operand-01.s | 4 ++
> .../gas/riscv/cv-bi-fail-operand-02.d | 3 +
> .../gas/riscv/cv-bi-fail-operand-02.l | 3 +
> .../gas/riscv/cv-bi-fail-operand-02.s | 4 ++
> .../gas/riscv/cv-bi-fail-operand-03.d | 3 +
> .../gas/riscv/cv-bi-fail-operand-03.l | 9 +++
> .../gas/riscv/cv-bi-fail-operand-03.s | 10 ++++
> gas/testsuite/gas/riscv/cv-elw-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-elw-fail-march.l | 38 +++++++++++++
> gas/testsuite/gas/riscv/cv-elw-fail-march.s | 42 ++++++++++++++
> gas/testsuite/gas/riscv/cv-elw-fail.d | 3 +
> gas/testsuite/gas/riscv/cv-elw-fail.l | 5 ++
> gas/testsuite/gas/riscv/cv-elw-fail.s | 8 +++
> gas/testsuite/gas/riscv/cv-elw-pass.d | 46 +++++++++++++++
> gas/testsuite/gas/riscv/cv-elw-pass.s | 42 ++++++++++++++
> gas/testsuite/gas/riscv/cv-mem-fail-march.d | 3 +
> gas/testsuite/gas/riscv/cv-mem-fail-march.l | 25 ++++++++
> gas/testsuite/gas/riscv/cv-mem-fail-march.s | 26 +++++++++
> .../gas/riscv/cv-mem-fail-operand-01.d | 3 +
> .../gas/riscv/cv-mem-fail-operand-01.l | 21 +++++++
> .../gas/riscv/cv-mem-fail-operand-01.s | 22 +++++++
> .../gas/riscv/cv-mem-fail-operand-02.d | 3 +
> .../gas/riscv/cv-mem-fail-operand-02.l | 13 +++++
> .../gas/riscv/cv-mem-fail-operand-02.s | 14 +++++
> .../gas/riscv/cv-mem-fail-operand-03.d | 3 +
> .../gas/riscv/cv-mem-fail-operand-03.l | 33 +++++++++++
> .../gas/riscv/cv-mem-fail-operand-03.s | 34 +++++++++++
> .../gas/riscv/cv-mem-fail-operand-04.d | 3 +
> .../gas/riscv/cv-mem-fail-operand-04.l | 41 +++++++++++++
> .../gas/riscv/cv-mem-fail-operand-04.s | 42 ++++++++++++++
> .../gas/riscv/cv-mem-fail-operand-05.d | 3 +
> .../gas/riscv/cv-mem-fail-operand-05.l | 25 ++++++++
> .../gas/riscv/cv-mem-fail-operand-05.s | 26 +++++++++
> gas/testsuite/gas/riscv/cv-mem-lbpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lbpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lbrr.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lbrr.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lbrrpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lbrrpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lbupost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lbupost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lburr.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lburr.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lburrpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lburrpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lhpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lhpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lhrr.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lhrr.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lhrrpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lhrrpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lhupost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lhupost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lhurr.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lhurr.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lhurrpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lhurrpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lwpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lwpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lwrr.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lwrr.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-lwrrpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-lwrrpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-sbpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-sbpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-sbrr.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-sbrr.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-sbrrpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-sbrrpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-shpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-shpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-shrr.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-shrr.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-shrrpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-shrrpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-swpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-swpost.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-swrr.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-swrr.s | 4 ++
> gas/testsuite/gas/riscv/cv-mem-swrrpost.d | 12 ++++
> gas/testsuite/gas/riscv/cv-mem-swrrpost.s | 4 ++
> gas/testsuite/gas/riscv/march-help.l | 3 +
> include/opcode/riscv-opc.h | 57 +++++++++++++++++++
> include/opcode/riscv.h | 6 ++
> ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d | 21 +++++++
> ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s | 11 ++++
> ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d | 21 +++++++
> ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s | 11 ++++
> ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 2 +
> opcodes/riscv-dis.c | 4 ++
> opcodes/riscv-opc.c | 33 +++++++++++
> 103 files changed, 1206 insertions(+), 1 deletion(-)
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l
> create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s
> create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.d
> create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.l
> create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.s
> create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.d
> create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrr.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrr.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrrpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrrpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbupost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbupost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburr.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburr.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburrpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburrpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrr.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrr.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrrpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrrpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhupost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhupost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurr.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurr.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurrpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurrpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrr.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrr.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrrpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrrpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrr.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrr.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrrpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrrpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-shpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-shpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrr.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrr.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrrpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrrpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-swpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-swpost.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrr.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrr.s
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrrpost.d
> create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrrpost.s
> create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d
> create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s
> create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d
> create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s
>
>--
>2.43.0
>
>
LGTM!
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2024-06-09 12:56 Re:[PATCH 0/3] RISC-V: Support CORE-V XCVELW, XCVBI and XCVMEM extensions yulong
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