From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) by sourceware.org (Postfix) with ESMTPS id 6B7813858CDB for ; Sun, 9 Jun 2024 12:56:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6B7813858CDB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6B7813858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717937778; cv=none; b=AOGy/bRkhIS4Ibd29w41lOHsqgjY0p1CFQnLAChc+cMUm8gk7r6lyDHPdgHfwO3gZSELCmtzIB3fzeD4POhGyqIxYq1bH89kj1Fd1i2qvjrj7wDwH4TsSsIZFCXWrgpzqjPF7R9qilt0fs78JEBJckZFlZ1GNLutvXTeHZ4ZVk8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1717937778; c=relaxed/simple; bh=tpY3ffe7Fd1GLpWL6RAdlbwDpv5LF3+l/NbNClFEJN4=; h=Message-ID:Date:MIME-Version:To:From:Subject; b=Xj+D4RgJrX522ofowZIIc6BGtRoQcMkzEedIXxz1GpDe3wMQUa/xZ2SSV4spP1JodnXJzuRxQxTXfJuj/0Xe5mmJhqpX4jMKyZHzkSQhJOG91ALS6Qz0r4bQ1BXojltStJ7HNLxdFSI6/eax2yOATS1VlPH9qKQGKf3tvEKSIrU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from [192.168.0.102] (unknown [114.238.11.19]) by APP-03 (Coremail) with SMTP id rQCowAD3GSxkpmVmKlDeDw--.12394S3; Sun, 09 Jun 2024 20:56:05 +0800 (CST) Message-ID: <6214a734-1fb8-4fa2-968f-099224ad9a63@iscas.ac.cn> Date: Sun, 9 Jun 2024 20:56:05 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird To: mary.bennett682@gmail.com From: yulong Cc: binutils@sourceware.org Subject: Re:[PATCH 0/3] RISC-V: Support CORE-V XCVELW, XCVBI and XCVMEM extensions Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CM-TRANSID:rQCowAD3GSxkpmVmKlDeDw--.12394S3 X-Coremail-Antispam: 1UD129KBjvAXoW3tw43XryDGr1kJrWkKryrXrb_yoW8Xw4xuo Z5GF4UGa1FgF129r1jvw45JFn3KF1DGr90qa98uF43Z3Wruw1rJ34UK395Z3yIgr1xGr4q gFy8JFyUWF9rXF1fn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUU5W7k0a2IF6w4kM7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0 x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj4 1l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0 I7IYx2IY6xkF7I0E14v26r1j6r4UM28EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwV C2z280aVCY1x0267AKxVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVAC Y4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJV W8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41l42xK82IYc2Ij64vIr41l4I8I 3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxV WUGVWUWwC2zVAF1VAY17CE14v26r1Y6r17MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAF wI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcI k0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j 6r4UYxBIdaVFxhVjvjDU0xZFpf9x07bOoGdUUUUU= X-Originating-IP: [114.238.11.19] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,BODY_8BITS,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: >This patch series presents the comprehensive implementation of the ELW, BI and >MEM extensions for CORE-V. > >Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to >ensure its correctness and compatibility with the existing codebase. >However, your input, reviews, and suggestions are invaluable in making this >extension even more robust. > >The CORE-V instructions are described in the specification [1] and work can be >found in the OpenHW group's Github repository [2]. > >[1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html > >[2] github.com/openhwgroup/corev-binutils-gdb > >Contributors: >  Mary Bennett >  Nandni Jamnadas >  Pietra Ferreira >  Charlie Keaney >  Jessica Mills >  Craig Blackmore >  Simon Cook >  Jeremy Bennett >  Helene Chelin >  Nazareno Bruschi >  Lin Sinan > > >RISC-V: Add support for XCVelw extension in CV32E40P >RISC-V: Add support for XCVbi extension in CV32E40P >RISC-V: Add support for XCVmem extension in CV32E40P > > > bfd/elfxx-riscv.c                             | 15 +++++ > gas/config/tc-riscv.c                         | 12 +++- > gas/doc/c-riscv.texi                          | 15 +++++ > gas/testsuite/gas/riscv/cv-bi-beqimm.d        | 12 ++++ > gas/testsuite/gas/riscv/cv-bi-beqimm.s        |  4 ++ > gas/testsuite/gas/riscv/cv-bi-bneimm.d        | 12 ++++ > gas/testsuite/gas/riscv/cv-bi-bneimm.s        |  4 ++ > gas/testsuite/gas/riscv/cv-bi-fail-march.d    |  3 + > gas/testsuite/gas/riscv/cv-bi-fail-march.l    |  3 + > gas/testsuite/gas/riscv/cv-bi-fail-march.s    |  5 ++ > .../gas/riscv/cv-bi-fail-operand-01.d         |  3 + > .../gas/riscv/cv-bi-fail-operand-01.l         |  3 + > .../gas/riscv/cv-bi-fail-operand-01.s         |  4 ++ > .../gas/riscv/cv-bi-fail-operand-02.d         |  3 + > .../gas/riscv/cv-bi-fail-operand-02.l         |  3 + > .../gas/riscv/cv-bi-fail-operand-02.s         |  4 ++ > .../gas/riscv/cv-bi-fail-operand-03.d         |  3 + > .../gas/riscv/cv-bi-fail-operand-03.l         |  9 +++ > .../gas/riscv/cv-bi-fail-operand-03.s         | 10 ++++ > gas/testsuite/gas/riscv/cv-elw-fail-march.d   |  3 + > gas/testsuite/gas/riscv/cv-elw-fail-march.l   | 38 +++++++++++++ > gas/testsuite/gas/riscv/cv-elw-fail-march.s   | 42 ++++++++++++++ > gas/testsuite/gas/riscv/cv-elw-fail.d         |  3 + > gas/testsuite/gas/riscv/cv-elw-fail.l         |  5 ++ > gas/testsuite/gas/riscv/cv-elw-fail.s         |  8 +++ > gas/testsuite/gas/riscv/cv-elw-pass.d         | 46 +++++++++++++++ > gas/testsuite/gas/riscv/cv-elw-pass.s         | 42 ++++++++++++++ > gas/testsuite/gas/riscv/cv-mem-fail-march.d   |  3 + > gas/testsuite/gas/riscv/cv-mem-fail-march.l   | 25 ++++++++ > gas/testsuite/gas/riscv/cv-mem-fail-march.s   | 26 +++++++++ > .../gas/riscv/cv-mem-fail-operand-01.d        |  3 + > .../gas/riscv/cv-mem-fail-operand-01.l        | 21 +++++++ > .../gas/riscv/cv-mem-fail-operand-01.s        | 22 +++++++ > .../gas/riscv/cv-mem-fail-operand-02.d        |  3 + > .../gas/riscv/cv-mem-fail-operand-02.l        | 13 +++++ > .../gas/riscv/cv-mem-fail-operand-02.s        | 14 +++++ > .../gas/riscv/cv-mem-fail-operand-03.d        |  3 + > .../gas/riscv/cv-mem-fail-operand-03.l        | 33 +++++++++++ > .../gas/riscv/cv-mem-fail-operand-03.s        | 34 +++++++++++ > .../gas/riscv/cv-mem-fail-operand-04.d        |  3 + > .../gas/riscv/cv-mem-fail-operand-04.l        | 41 +++++++++++++ > .../gas/riscv/cv-mem-fail-operand-04.s        | 42 ++++++++++++++ > .../gas/riscv/cv-mem-fail-operand-05.d        |  3 + > .../gas/riscv/cv-mem-fail-operand-05.l        | 25 ++++++++ > .../gas/riscv/cv-mem-fail-operand-05.s        | 26 +++++++++ > gas/testsuite/gas/riscv/cv-mem-lbpost.d       | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lbpost.s       |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lbrr.d         | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lbrr.s         |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lbrrpost.d     | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lbrrpost.s     |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lbupost.d      | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lbupost.s      |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lburr.d        | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lburr.s        |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lburrpost.d    | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lburrpost.s    |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lhpost.d       | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lhpost.s       |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lhrr.d         | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lhrr.s         |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lhrrpost.d     | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lhrrpost.s     |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lhupost.d      | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lhupost.s      |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lhurr.d        | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lhurr.s        |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lhurrpost.d    | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lhurrpost.s    |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lwpost.d       | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lwpost.s       |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lwrr.d         | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lwrr.s         |  4 ++ > gas/testsuite/gas/riscv/cv-mem-lwrrpost.d     | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-lwrrpost.s     |  4 ++ > gas/testsuite/gas/riscv/cv-mem-sbpost.d       | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-sbpost.s       |  4 ++ > gas/testsuite/gas/riscv/cv-mem-sbrr.d         | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-sbrr.s         |  4 ++ > gas/testsuite/gas/riscv/cv-mem-sbrrpost.d     | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-sbrrpost.s     |  4 ++ > gas/testsuite/gas/riscv/cv-mem-shpost.d       | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-shpost.s       |  4 ++ > gas/testsuite/gas/riscv/cv-mem-shrr.d         | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-shrr.s         |  4 ++ > gas/testsuite/gas/riscv/cv-mem-shrrpost.d     | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-shrrpost.s     |  4 ++ > gas/testsuite/gas/riscv/cv-mem-swpost.d       | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-swpost.s       |  4 ++ > gas/testsuite/gas/riscv/cv-mem-swrr.d         | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-swrr.s         |  4 ++ > gas/testsuite/gas/riscv/cv-mem-swrrpost.d     | 12 ++++ > gas/testsuite/gas/riscv/cv-mem-swrrpost.s     |  4 ++ > gas/testsuite/gas/riscv/march-help.l          |  3 + > include/opcode/riscv-opc.h                    | 57 +++++++++++++++++++ > include/opcode/riscv.h                        |  6 ++ > ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d      | 21 +++++++ > ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s      | 11 ++++ > ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d      | 21 +++++++ > ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s      | 11 ++++ > ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp    |  2 + > opcodes/riscv-dis.c                           |  4 ++ > opcodes/riscv-opc.c                           | 33 +++++++++++ > 103 files changed, 1206 insertions(+), 1 deletion(-) > create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.d > create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.s > create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.d > create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.s > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.d > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.l > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.s > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l > create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.d > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.l > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.s > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.d > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.l > create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.s > create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.d > create mode 100644 gas/testsuite/gas/riscv/cv-elw-pass.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.l > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-march.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.l > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-01.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.l > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-02.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.l > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-03.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.l > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-04.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.l > create mode 100644 gas/testsuite/gas/riscv/cv-mem-fail-operand-05.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrr.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrr.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrrpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbrrpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbupost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lbupost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburr.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburr.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburrpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lburrpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrr.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrr.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrrpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhrrpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhupost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhupost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurr.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurr.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurrpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lhurrpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrr.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrr.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrrpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-lwrrpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrr.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrr.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrrpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-sbrrpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-shpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-shpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrr.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrr.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrrpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-shrrpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-swpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-swpost.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrr.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrr.s > create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrrpost.d > create mode 100644 gas/testsuite/gas/riscv/cv-mem-swrrpost.s > create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d > create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s > create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d > create mode 100644 ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s > >-- >2.43.0 > > LGTM!