From: "Richard Earnshaw (lists)" <Richard.Earnshaw@arm.com>
To: binutils@sourceware.org, richard.sandiford@arm.com
Subject: Re: [AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element size
Date: Thu, 25 Aug 2016 13:48:00 -0000 [thread overview]
Message-ID: <65431c27-e765-b26f-1594-e244dd1e3f29@arm.com> (raw)
In-Reply-To: <87fupv3kyu.fsf@e105548-lin.cambridge.arm.com>
On 23/08/16 10:15, Richard Sandiford wrote:
> SVE supports logical immediate operations on 8-bit, 16-bit and 32-bit
> elements, treating them as aliases of operations on 64-bit elements in
> which the immediate is replicated. This patch therefore replaces the
> "32-bit/64-bit" input to aarch64_logical_immediate_p with a more
> general "number of bytes" input.
>
> OK to install?
>
> Thanks,
> Richard
>
>
> opcodes/
> * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
> with an esize parameter.
> (operand_general_constraint_met_p): Update accordingly.
> Fix misindented code.
> * aarch64-asm.c (aarch64_ins_limm): Update call to
> aarch64_logical_immediate_p.
OK
R.
>
> diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
> index 2430be5..8fbd66f 100644
> --- a/opcodes/aarch64-asm.c
> +++ b/opcodes/aarch64-asm.c
> @@ -436,11 +436,11 @@ aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
> {
> aarch64_insn value;
> uint64_t imm = info->imm.value;
> - int is32 = aarch64_get_qualifier_esize (inst->operands[0].qualifier) == 4;
> + int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
>
> if (inst->opcode->op == OP_BIC)
> imm = ~imm;
> - if (aarch64_logical_immediate_p (imm, is32, &value) == FALSE)
> + if (aarch64_logical_immediate_p (imm, esize, &value) == FALSE)
> /* The constraint check should have guaranteed this wouldn't happen. */
> assert (0);
>
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index d870fd6..84da821 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -1062,16 +1062,18 @@ build_immediate_table (void)
> be accepted by logical (immediate) instructions
> e.g. ORR <Xd|SP>, <Xn>, #<imm>.
>
> - IS32 indicates whether or not VALUE is a 32-bit immediate.
> + ESIZE is the number of bytes in the decoded immediate value.
> If ENCODING is not NULL, on the return of TRUE, the standard encoding for
> VALUE will be returned in *ENCODING. */
>
> bfd_boolean
> -aarch64_logical_immediate_p (uint64_t value, int is32, aarch64_insn *encoding)
> +aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
> {
> simd_imm_encoding imm_enc;
> const simd_imm_encoding *imm_encoding;
> static bfd_boolean initialized = FALSE;
> + uint64_t upper;
> + int i;
>
> DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), is32: %d", value,
> value, is32);
> @@ -1082,17 +1084,16 @@ aarch64_logical_immediate_p (uint64_t value, int is32, aarch64_insn *encoding)
> initialized = TRUE;
> }
>
> - if (is32)
> - {
> - /* Allow all zeros or all ones in top 32-bits, so that
> - constant expressions like ~1 are permitted. */
> - if (value >> 32 != 0 && value >> 32 != 0xffffffff)
> - return FALSE;
> + /* Allow all zeros or all ones in top bits, so that
> + constant expressions like ~1 are permitted. */
> + upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
> + if ((value & ~upper) != value && (value | upper) != value)
> + return FALSE;
>
> - /* Replicate the 32 lower bits to the 32 upper bits. */
> - value &= 0xffffffff;
> - value |= value << 32;
> - }
> + /* Replicate to a full 64-bit value. */
> + value &= ~upper;
> + for (i = esize * 8; i < 64; i *= 2)
> + value |= (value << i);
>
> imm_enc.imm = value;
> imm_encoding = (const simd_imm_encoding *)
> @@ -1645,7 +1646,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
>
> case AARCH64_OPND_IMM_MOV:
> {
> - int is32 = aarch64_get_qualifier_esize (opnds[0].qualifier) == 4;
> + int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
> imm = opnd->imm.value;
> assert (idx == 1);
> switch (opcode->op)
> @@ -1654,7 +1655,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
> imm = ~imm;
> /* Fall through... */
> case OP_MOV_IMM_WIDE:
> - if (!aarch64_wide_constant_p (imm, is32, NULL))
> + if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
> {
> set_other_error (mismatch_detail, idx,
> _("immediate out of range"));
> @@ -1662,7 +1663,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
> }
> break;
> case OP_MOV_IMM_LOG:
> - if (!aarch64_logical_immediate_p (imm, is32, NULL))
> + if (!aarch64_logical_immediate_p (imm, esize, NULL))
> {
> set_other_error (mismatch_detail, idx,
> _("immediate out of range"));
> @@ -1707,18 +1708,18 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
> break;
>
> case AARCH64_OPND_LIMM:
> - {
> - int is32 = opnds[0].qualifier == AARCH64_OPND_QLF_W;
> - uint64_t uimm = opnd->imm.value;
> - if (opcode->op == OP_BIC)
> - uimm = ~uimm;
> - if (aarch64_logical_immediate_p (uimm, is32, NULL) == FALSE)
> - {
> - set_other_error (mismatch_detail, idx,
> - _("immediate out of range"));
> - return 0;
> - }
> - }
> + {
> + int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
> + uint64_t uimm = opnd->imm.value;
> + if (opcode->op == OP_BIC)
> + uimm = ~uimm;
> + if (aarch64_logical_immediate_p (uimm, esize, NULL) == FALSE)
> + {
> + set_other_error (mismatch_detail, idx,
> + _("immediate out of range"));
> + return 0;
> + }
> + }
> break;
>
> case AARCH64_OPND_IMM0:
>
next prev parent reply other threads:[~2016-08-25 13:48 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-23 9:05 [AArch64][SVE 00/32] Add support for the ARMv8-A Scalable Vector Extension Richard Sandiford
2016-08-23 9:06 ` [AArch64][SVE 02/32] Avoid hard-coded limit in indented_print Richard Sandiford
2016-08-23 14:35 ` Richard Earnshaw (lists)
2016-08-23 9:06 ` [AArch64][SVE 01/32] Remove parse_neon_operand_type Richard Sandiford
2016-08-23 14:28 ` Richard Earnshaw (lists)
2016-08-23 9:07 ` [AArch64][SVE 04/32] Rename neon_type_el to vector_type_el Richard Sandiford
2016-08-23 14:37 ` Richard Earnshaw (lists)
2016-08-23 9:07 ` [AArch64][SVE 03/32] Rename neon_el_type to vector_el_type Richard Sandiford
2016-08-23 14:36 ` Richard Earnshaw (lists)
2016-08-23 9:08 ` [AArch64][SVE 06/32] Generalise parse_neon_reg_list Richard Sandiford
2016-08-23 14:39 ` Richard Earnshaw (lists)
2016-08-23 9:08 ` [AArch64][SVE 05/32] Rename parse_neon_type_for_operand Richard Sandiford
2016-08-23 14:37 ` Richard Earnshaw (lists)
2016-08-23 9:09 ` [AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_V Richard Sandiford
2016-08-25 10:36 ` Richard Earnshaw (lists)
2016-08-23 9:10 ` [AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovable Richard Sandiford
2016-08-25 13:17 ` Richard Earnshaw (lists)
2016-08-23 9:11 ` [AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_float Richard Sandiford
2016-08-25 13:20 ` Richard Earnshaw (lists)
2016-08-23 9:11 ` [AArch64][SVE 09/32] Improve error messages for invalid floats Richard Sandiford
2016-08-25 13:19 ` Richard Earnshaw (lists)
2016-08-23 9:12 ` [AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interface Richard Sandiford
2016-08-25 13:27 ` Richard Earnshaw (lists)
2016-09-16 11:51 ` Richard Sandiford
2016-09-20 10:47 ` Richard Earnshaw (lists)
2016-08-23 9:13 ` [AArch64][SVE 12/32] Make more use of bfd_boolean Richard Sandiford
2016-08-25 13:39 ` Richard Earnshaw (lists)
2016-09-16 11:56 ` Richard Sandiford
2016-09-20 12:39 ` Richard Earnshaw (lists)
2016-08-23 9:14 ` [AArch64][SVE 13/32] Add an F_STRICT flag Richard Sandiford
2016-08-25 13:45 ` Richard Earnshaw (lists)
2016-08-23 9:15 ` [AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element size Richard Sandiford
2016-08-25 13:48 ` Richard Earnshaw (lists) [this message]
2016-08-23 9:15 ` [AArch64][SVE 15/32] Add {insert,extract}_all_fields helpers Richard Sandiford
2016-08-25 13:50 ` Richard Earnshaw (lists)
2016-08-23 9:16 ` [AArch64][SVE 16/32] Use specific insert/extract methods for fpimm Richard Sandiford
2016-08-25 13:52 ` Richard Earnshaw (lists)
2016-08-23 9:16 ` [AArch64][SVE 17/32] Add a prefix parameter to print_register_list Richard Sandiford
2016-08-25 13:53 ` Richard Earnshaw (lists)
2016-08-23 9:16 ` [AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_reg Richard Sandiford
2016-08-25 13:55 ` Richard Earnshaw (lists)
2016-08-23 9:17 ` [AArch64][SVE 19/32] Refactor address-printing code Richard Sandiford
2016-08-25 13:57 ` Richard Earnshaw (lists)
2016-08-23 9:18 ` [AArch64][SVE 20/32] Add support for tied operands Richard Sandiford
2016-08-25 13:59 ` Richard Earnshaw (lists)
2016-08-23 9:18 ` [AArch64][SVE 21/32] Add Zn and Pn registers Richard Sandiford
2016-08-25 14:07 ` Richard Earnshaw (lists)
2016-08-23 9:19 ` [AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication Richard Sandiford
2016-08-25 14:08 ` Richard Earnshaw (lists)
2016-08-23 9:20 ` [AArch64][SVE 23/32] Add SVE pattern and prfop operands Richard Sandiford
2016-08-25 14:12 ` Richard Earnshaw (lists)
2016-08-23 9:21 ` [AArch64][SVE 25/32] Add support for SVE addressing modes Richard Sandiford
2016-08-25 14:38 ` Richard Earnshaw (lists)
2016-09-16 12:06 ` Richard Sandiford
2016-09-20 13:40 ` Richard Earnshaw (lists)
2016-08-23 9:21 ` [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED Richard Sandiford
2016-08-25 14:28 ` Richard Earnshaw (lists)
2016-08-23 9:23 ` [AArch64][SVE 26/32] Add SVE MUL VL addressing modes Richard Sandiford
2016-08-25 14:44 ` Richard Earnshaw (lists)
2016-09-16 12:10 ` Richard Sandiford
2016-09-20 13:51 ` Richard Earnshaw (lists)
2016-08-23 9:24 ` [AArch64][SVE 27/32] Add SVE integer immediate operands Richard Sandiford
2016-08-25 14:51 ` Richard Earnshaw (lists)
2016-08-23 9:25 ` [AArch64][SVE 28/32] Add SVE FP " Richard Sandiford
2016-08-25 14:59 ` Richard Earnshaw (lists)
2016-08-23 9:25 ` [AArch64][SVE 29/32] Add new SVE core & FP register operands Richard Sandiford
2016-08-25 15:01 ` Richard Earnshaw (lists)
2016-08-23 9:26 ` [AArch64][SVE 30/32] Add SVE instruction classes Richard Sandiford
2016-08-25 15:07 ` Richard Earnshaw (lists)
2016-08-23 9:29 ` [AArch64][SVE 31/32] Add SVE instructions Richard Sandiford
2016-08-25 15:18 ` Richard Earnshaw (lists)
2016-08-23 9:31 ` [AArch64][SVE 32/32] Add SVE tests Richard Sandiford
2016-08-25 15:23 ` Richard Earnshaw (lists)
2016-08-30 21:23 ` Richard Sandiford
2016-08-31 9:47 ` Richard Earnshaw (lists)
2016-08-30 13:04 ` [AArch64][SVE 00/32] Add support for the ARMv8-A Scalable Vector Extension Nick Clifton
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