From: "Richard Earnshaw (lists)" <Richard.Earnshaw@arm.com>
To: binutils@sourceware.org, richard.sandiford@arm.com
Subject: Re: [AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_reg
Date: Thu, 25 Aug 2016 13:55:00 -0000 [thread overview]
Message-ID: <694681de-1051-2175-e3b8-69228373724f@arm.com> (raw)
In-Reply-To: <87y43n26bk.fsf@e105548-lin.cambridge.arm.com>
On 23/08/16 10:16, Richard Sandiford wrote:
> Use a macro to define 31 regular registers followed by a supplied
> value for 0b11111. The SVE code will also use this for vector base
> and offset registers.
>
> OK to install?
>
> Thanks,
> Richard
>
>
> opcodes/
> * aarch64-opc.c (BANK): New macro.
> (R32, R64): Take a register number as argument
> (int_reg): Use BANK.
>
OK.
R.
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index 6eac70a..3f9be62 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -2149,32 +2149,25 @@ aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd oper
> return -1;
> }
> \f
> +/* R0...R30, followed by FOR31. */
> +#define BANK(R, FOR31) \
> + { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
> + R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
> + R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
> + R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
> /* [0][0] 32-bit integer regs with sp Wn
> [0][1] 64-bit integer regs with sp Xn sf=1
> [1][0] 32-bit integer regs with #0 Wn
> [1][1] 64-bit integer regs with #0 Xn sf=1 */
> static const char *int_reg[2][2][32] = {
> -#define R32 "w"
> -#define R64 "x"
> - { { R32 "0", R32 "1", R32 "2", R32 "3", R32 "4", R32 "5", R32 "6", R32 "7",
> - R32 "8", R32 "9", R32 "10", R32 "11", R32 "12", R32 "13", R32 "14", R32 "15",
> - R32 "16", R32 "17", R32 "18", R32 "19", R32 "20", R32 "21", R32 "22", R32 "23",
> - R32 "24", R32 "25", R32 "26", R32 "27", R32 "28", R32 "29", R32 "30", "wsp" },
> - { R64 "0", R64 "1", R64 "2", R64 "3", R64 "4", R64 "5", R64 "6", R64 "7",
> - R64 "8", R64 "9", R64 "10", R64 "11", R64 "12", R64 "13", R64 "14", R64 "15",
> - R64 "16", R64 "17", R64 "18", R64 "19", R64 "20", R64 "21", R64 "22", R64 "23",
> - R64 "24", R64 "25", R64 "26", R64 "27", R64 "28", R64 "29", R64 "30", "sp" } },
> - { { R32 "0", R32 "1", R32 "2", R32 "3", R32 "4", R32 "5", R32 "6", R32 "7",
> - R32 "8", R32 "9", R32 "10", R32 "11", R32 "12", R32 "13", R32 "14", R32 "15",
> - R32 "16", R32 "17", R32 "18", R32 "19", R32 "20", R32 "21", R32 "22", R32 "23",
> - R32 "24", R32 "25", R32 "26", R32 "27", R32 "28", R32 "29", R32 "30", R32 "zr" },
> - { R64 "0", R64 "1", R64 "2", R64 "3", R64 "4", R64 "5", R64 "6", R64 "7",
> - R64 "8", R64 "9", R64 "10", R64 "11", R64 "12", R64 "13", R64 "14", R64 "15",
> - R64 "16", R64 "17", R64 "18", R64 "19", R64 "20", R64 "21", R64 "22", R64 "23",
> - R64 "24", R64 "25", R64 "26", R64 "27", R64 "28", R64 "29", R64 "30", R64 "zr" } }
> +#define R32(X) "w" #X
> +#define R64(X) "x" #X
> + { BANK (R32, "wsp"), BANK (R64, "sp") },
> + { BANK (R32, "wzr"), BANK (R64, "xzr") }
> #undef R64
> #undef R32
> };
> +#undef BANK
>
> /* Return the integer register name.
> if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
>
next prev parent reply other threads:[~2016-08-25 13:55 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-23 9:05 [AArch64][SVE 00/32] Add support for the ARMv8-A Scalable Vector Extension Richard Sandiford
2016-08-23 9:06 ` [AArch64][SVE 02/32] Avoid hard-coded limit in indented_print Richard Sandiford
2016-08-23 14:35 ` Richard Earnshaw (lists)
2016-08-23 9:06 ` [AArch64][SVE 01/32] Remove parse_neon_operand_type Richard Sandiford
2016-08-23 14:28 ` Richard Earnshaw (lists)
2016-08-23 9:07 ` [AArch64][SVE 03/32] Rename neon_el_type to vector_el_type Richard Sandiford
2016-08-23 14:36 ` Richard Earnshaw (lists)
2016-08-23 9:07 ` [AArch64][SVE 04/32] Rename neon_type_el to vector_type_el Richard Sandiford
2016-08-23 14:37 ` Richard Earnshaw (lists)
2016-08-23 9:08 ` [AArch64][SVE 05/32] Rename parse_neon_type_for_operand Richard Sandiford
2016-08-23 14:37 ` Richard Earnshaw (lists)
2016-08-23 9:08 ` [AArch64][SVE 06/32] Generalise parse_neon_reg_list Richard Sandiford
2016-08-23 14:39 ` Richard Earnshaw (lists)
2016-08-23 9:09 ` [AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_V Richard Sandiford
2016-08-25 10:36 ` Richard Earnshaw (lists)
2016-08-23 9:10 ` [AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovable Richard Sandiford
2016-08-25 13:17 ` Richard Earnshaw (lists)
2016-08-23 9:11 ` [AArch64][SVE 09/32] Improve error messages for invalid floats Richard Sandiford
2016-08-25 13:19 ` Richard Earnshaw (lists)
2016-08-23 9:11 ` [AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_float Richard Sandiford
2016-08-25 13:20 ` Richard Earnshaw (lists)
2016-08-23 9:12 ` [AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interface Richard Sandiford
2016-08-25 13:27 ` Richard Earnshaw (lists)
2016-09-16 11:51 ` Richard Sandiford
2016-09-20 10:47 ` Richard Earnshaw (lists)
2016-08-23 9:13 ` [AArch64][SVE 12/32] Make more use of bfd_boolean Richard Sandiford
2016-08-25 13:39 ` Richard Earnshaw (lists)
2016-09-16 11:56 ` Richard Sandiford
2016-09-20 12:39 ` Richard Earnshaw (lists)
2016-08-23 9:14 ` [AArch64][SVE 13/32] Add an F_STRICT flag Richard Sandiford
2016-08-25 13:45 ` Richard Earnshaw (lists)
2016-08-23 9:15 ` [AArch64][SVE 15/32] Add {insert,extract}_all_fields helpers Richard Sandiford
2016-08-25 13:50 ` Richard Earnshaw (lists)
2016-08-23 9:15 ` [AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element size Richard Sandiford
2016-08-25 13:48 ` Richard Earnshaw (lists)
2016-08-23 9:16 ` [AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_reg Richard Sandiford
2016-08-25 13:55 ` Richard Earnshaw (lists) [this message]
2016-08-23 9:16 ` [AArch64][SVE 17/32] Add a prefix parameter to print_register_list Richard Sandiford
2016-08-25 13:53 ` Richard Earnshaw (lists)
2016-08-23 9:16 ` [AArch64][SVE 16/32] Use specific insert/extract methods for fpimm Richard Sandiford
2016-08-25 13:52 ` Richard Earnshaw (lists)
2016-08-23 9:17 ` [AArch64][SVE 19/32] Refactor address-printing code Richard Sandiford
2016-08-25 13:57 ` Richard Earnshaw (lists)
2016-08-23 9:18 ` [AArch64][SVE 20/32] Add support for tied operands Richard Sandiford
2016-08-25 13:59 ` Richard Earnshaw (lists)
2016-08-23 9:18 ` [AArch64][SVE 21/32] Add Zn and Pn registers Richard Sandiford
2016-08-25 14:07 ` Richard Earnshaw (lists)
2016-08-23 9:19 ` [AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication Richard Sandiford
2016-08-25 14:08 ` Richard Earnshaw (lists)
2016-08-23 9:20 ` [AArch64][SVE 23/32] Add SVE pattern and prfop operands Richard Sandiford
2016-08-25 14:12 ` Richard Earnshaw (lists)
2016-08-23 9:21 ` [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED Richard Sandiford
2016-08-25 14:28 ` Richard Earnshaw (lists)
2016-08-23 9:21 ` [AArch64][SVE 25/32] Add support for SVE addressing modes Richard Sandiford
2016-08-25 14:38 ` Richard Earnshaw (lists)
2016-09-16 12:06 ` Richard Sandiford
2016-09-20 13:40 ` Richard Earnshaw (lists)
2016-08-23 9:23 ` [AArch64][SVE 26/32] Add SVE MUL VL " Richard Sandiford
2016-08-25 14:44 ` Richard Earnshaw (lists)
2016-09-16 12:10 ` Richard Sandiford
2016-09-20 13:51 ` Richard Earnshaw (lists)
2016-08-23 9:24 ` [AArch64][SVE 27/32] Add SVE integer immediate operands Richard Sandiford
2016-08-25 14:51 ` Richard Earnshaw (lists)
2016-08-23 9:25 ` [AArch64][SVE 29/32] Add new SVE core & FP register operands Richard Sandiford
2016-08-25 15:01 ` Richard Earnshaw (lists)
2016-08-23 9:25 ` [AArch64][SVE 28/32] Add SVE FP immediate operands Richard Sandiford
2016-08-25 14:59 ` Richard Earnshaw (lists)
2016-08-23 9:26 ` [AArch64][SVE 30/32] Add SVE instruction classes Richard Sandiford
2016-08-25 15:07 ` Richard Earnshaw (lists)
2016-08-23 9:29 ` [AArch64][SVE 31/32] Add SVE instructions Richard Sandiford
2016-08-25 15:18 ` Richard Earnshaw (lists)
2016-08-23 9:31 ` [AArch64][SVE 32/32] Add SVE tests Richard Sandiford
2016-08-25 15:23 ` Richard Earnshaw (lists)
2016-08-30 21:23 ` Richard Sandiford
2016-08-31 9:47 ` Richard Earnshaw (lists)
2016-08-30 13:04 ` [AArch64][SVE 00/32] Add support for the ARMv8-A Scalable Vector Extension Nick Clifton
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