From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18108 invoked by alias); 4 Apr 2019 13:38:51 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 18085 invoked by uid 89); 4 Apr 2019 13:38:50 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.7 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH,KAM_NUMSUBJECT,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 04 Apr 2019 13:38:48 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7D4A2169E for ; Thu, 4 Apr 2019 06:38:47 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 292123F59C for ; Thu, 4 Apr 2019 06:38:47 -0700 (PDT) Subject: [PATCH, binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 To: binutils@sourceware.org References: From: "Andre Vieira (lists)" Message-ID: <69a0cdd0-89a9-5dd2-da7b-caecef5fdd9e@arm.com> Date: Thu, 04 Apr 2019 13:38:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/mixed; boundary="------------F9B5746D250F0CDB14871982" X-IsSubscribed: yes X-SW-Source: 2019-04/txt/msg00040.txt.bz2 This is a multi-part message in MIME format. --------------F9B5746D250F0CDB14871982 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1764 Hi This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. Relocation specified in https://developer.arm.com/docs/ihi0044/latest/elf-for-the-arm-architecture-abi-2019q1-documentation#aaelf32-table4-9 The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. Testing: Builds successfully and no regressions. Thanks Sudi ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. --------------F9B5746D250F0CDB14871982 Content-Type: text/x-patch; name="8.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="8.patch" Content-length: 8823 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index b5922ff222b48e0699a814c9742e0a61cdca9cb8..99b0db4ec6d6ddfde74f47215510e0905b910e95 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -3570,6 +3570,9 @@ field in the instruction. */ /* ARM 17-bit pc-relative branch for Branch Future instructions. */ BFD_RELOC_ARM_THUMB_BF17, +/* ARM 19-bit pc-relative branch for Branch Future Link instruction. */ + BFD_RELOC_ARM_THUMB_BF19, + /* Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. The lowest bit must be zero and is not stored in the instruction. Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c index f5dc61b79ed2c6f5eb5800c3807f79438d1e3f1c..744d92515e81f558d5aacdeff53ef74cc2749437 100644 --- a/bfd/elf32-arm.c +++ b/bfd/elf32-arm.c @@ -1756,6 +1756,20 @@ static reloc_howto_type elf32_arm_howto_table_1[] = 0x001f0ffe, /* src_mask. */ 0x001f0ffe, /* dst_mask. */ TRUE), /* pcrel_offset. */ + EMPTY_HOWTO (137), + HOWTO (R_ARM_THM_BF18, /* type. */ + 0, /* rightshift. */ + 1, /* size (0 = byte, 1 = short, 2 = long). */ + 18, /* bitsize. */ + TRUE, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_dont,/* do not complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_ARM_THM_BF18", /* name. */ + FALSE, /* partial_inplace. */ + 0x007f0ffe, /* src_mask. */ + 0x007f0ffe, /* dst_mask. */ + TRUE), /* pcrel_offset. */ }; /* 160 onwards: */ @@ -2068,7 +2082,8 @@ static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] = {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC}, {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC}, {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}, - {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16} + {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16}, + {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18} }; static reloc_howto_type * @@ -12968,6 +12983,51 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, return bfd_reloc_ok; } + case R_ARM_THM_BF18: + { + bfd_vma relocation; + bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data); + bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2); + + if (globals->use_rel) + { + bfd_vma immA = (upper_insn & 0x007f); + bfd_vma immB = (lower_insn & 0x07fe) >> 1; + bfd_vma immC = (lower_insn & 0x0800) >> 11; + addend = (immA << 12); + addend |= (immB << 2); + addend |= (immC << 1); + addend |= 1; + /* Sign extend. */ + addend = (addend & 0x40000) ? addend - (1 << 19) : addend; + } + + value = get_value_helper (plt_offset, splt, input_section, sym_sec, h, + info, input_bfd, rel, sym_name, st_type, + globals, unresolved_reloc_p); + + relocation = value + addend; + relocation -= (input_section->output_section->vma + + input_section->output_offset + + rel->r_offset); + + /* Put RELOCATION back into the insn. */ + { + bfd_vma immA = (relocation & 0x0007f000) >> 12; + bfd_vma immB = (relocation & 0x00000ffc) >> 2; + bfd_vma immC = (relocation & 0x00000002) >> 1; + + upper_insn = (upper_insn & 0xff80) | immA; + lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1); + } + + /* Put the relocated value back in the object file: */ + bfd_put_16 (input_bfd, upper_insn, hit_data); + bfd_put_16 (input_bfd, lower_insn, hit_data + 2); + + return bfd_reloc_ok; + } + default: return bfd_reloc_notsupported; } diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 4a3fa144ad25b5a800501c352e6f0aa79509bb27..7f775acf9178d70ad8351064f2e2291dd79c73a0 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1531,6 +1531,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_ARM_PCREL_JUMP", "BFD_RELOC_THUMB_PCREL_BRANCH5", "BFD_RELOC_ARM_THUMB_BF17", + "BFD_RELOC_ARM_THUMB_BF19", "BFD_RELOC_THUMB_PCREL_BRANCH7", "BFD_RELOC_THUMB_PCREL_BRANCH9", "BFD_RELOC_THUMB_PCREL_BRANCH12", diff --git a/bfd/reloc.c b/bfd/reloc.c index b351d120d1d1894ba64a3eb2d32e21884648fd6a..9e3899ab4e7f3485cc2bd0f0953f652e0b28f48a 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -3024,6 +3024,11 @@ ENUM ENUMDOC ARM 17-bit pc-relative branch for Branch Future instructions. +ENUM + BFD_RELOC_ARM_THUMB_BF19 +ENUMDOC + ARM 19-bit pc-relative branch for Branch Future Link instruction. + ENUM BFD_RELOC_THUMB_PCREL_BRANCH7 ENUMX diff --git a/elfcpp/arm.h b/elfcpp/arm.h index e70f8bb01cc24b4445147d76c8a9bd28c562e017..a505a1ba37568c8b82d1ccc6dfebb63bf2595e75 100644 --- a/elfcpp/arm.h +++ b/elfcpp/arm.h @@ -197,6 +197,7 @@ enum // 131 - 135 Unallocated // New relocations for Armv8.1-M Mainline (BF/BFL) R_ARM_THM_BF16 = 136, // Static Thumb32 ((S + A) | T) – P + R_ARM_THM_BF18 = 138, // Static Thumb32 ((S + A) | T) – P // 139 Unallocated // 140 - 159 Dynamic Reserved for future allocation R_ARM_IRELATIVE = 160, // Dynamic diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index c7c1a82a998ce08330e05f3f2b3e34e453b87b2c..177d90f1c6fdc9ad99a395b479b16e5b9f8ae0b6 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -22924,6 +22924,7 @@ md_pcrel_from_section (fixS * fixP, segT seg) case BFD_RELOC_THUMB_PCREL_BRANCH20: case BFD_RELOC_THUMB_PCREL_BRANCH25: case BFD_RELOC_ARM_THUMB_BF17: + case BFD_RELOC_ARM_THUMB_BF19: return base + 4; case BFD_RELOC_THUMB_PCREL_BRANCH23: @@ -24854,6 +24855,39 @@ md_apply_fix (fixS * fixP, } break; + case BFD_RELOC_ARM_THUMB_BF19: + if (fixP->fx_addsy + && (S_GET_SEGMENT (fixP->fx_addsy) == seg) + && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) + && ARM_IS_FUNC (fixP->fx_addsy) + && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main)) + { + /* Force a relocation for a branch 19 bits wide. */ + fixP->fx_done = 0; + } + + if (v8_1_branch_value_check (value, 19, TRUE) == FAIL) + as_bad_where (fixP->fx_file, fixP->fx_line, + BAD_BRANCH_OFF); + + if (fixP->fx_done || !seg->use_rela_p) + { + offsetT newval2; + addressT immA, immB, immC; + + immA = (value & 0x0007f000) >> 12; + immB = (value & 0x00000ffc) >> 2; + immC = (value & 0x00000002) >> 1; + + newval = md_chars_to_number (buf, THUMB_SIZE); + newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + newval |= immA; + newval2 |= (immC << 11) | (immB << 1); + md_number_to_chars (buf, newval, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); + } + break; + case BFD_RELOC_ARM_V4BX: /* This will need to go in the object file. */ fixP->fx_done = 0; @@ -25037,6 +25071,7 @@ tc_gen_reloc (asection *section, fixS *fixp) case BFD_RELOC_ARM_GOTOFFFUNCDESC: case BFD_RELOC_ARM_FUNCDESC: case BFD_RELOC_ARM_THUMB_BF17: + case BFD_RELOC_ARM_THUMB_BF19: code = fixp->fx_r_type; break; diff --git a/include/elf/arm.h b/include/elf/arm.h index 2c6d4ef18a96e10fb206248df151c44a67757042..b8f2d2fa416e4516860ec049b642d331e0a3600e 100644 --- a/include/elf/arm.h +++ b/include/elf/arm.h @@ -242,6 +242,7 @@ START_RELOC_NUMBERS (elf_arm_reloc_type) RELOC_NUMBER (R_ARM_THM_ALU_ABS_G2_NC,134) RELOC_NUMBER (R_ARM_THM_ALU_ABS_G3_NC,135) RELOC_NUMBER (R_ARM_THM_BF16, 136) + RELOC_NUMBER (R_ARM_THM_BF18, 138) RELOC_NUMBER (R_ARM_IRELATIVE, 160) RELOC_NUMBER (R_ARM_GOTFUNCDESC, 161) diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 2929522fa359bd55305d50da84598a17813c2510..a70ed814fb1177132df1d5121cc68b2fef876b0c 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2716,6 +2716,7 @@ static const struct opcode16 thumb_opcodes[] = %F print the lsb and width fields of a sbfx/ubfx instruction %G print a fallback offset for Branch Future instructions %W print an offset for BF instruction + %Y print an offset for BFL instruction %b print a conditional branch offset %B print an unconditional branch offset %s print the shift field of an SSAT instruction @@ -5899,6 +5900,23 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'Y': + { + unsigned int immA = (given & 0x007f0000u) >> 16; + unsigned int immB = (given & 0x000007feu) >> 1; + unsigned int immC = (given & 0x00000800u) >> 11; + bfd_vma offset = 0; + + offset |= immA << 12; + offset |= immB << 2; + offset |= immC << 1; + /* Sign extend. */ + offset = (offset & 0x40000) ? offset - (1 << 19) : offset; + + info->print_address_func (pc + 4 + offset, info); + } + break; + case 'b': { unsigned int S = (given & 0x04000000u) >> 26; --------------F9B5746D250F0CDB14871982--