diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c index 337961d26e16c6458f41d54b2e8dbe6891a5017c..a4fd7de7aa2354dd25ebca8a5c222716a5468197 100644 --- a/bfd/elf32-arm.c +++ b/bfd/elf32-arm.c @@ -10293,59 +10293,6 @@ identify_add_or_sub (bfd_vma insn) return 0; } -/* Helper function to compute the Addend for Armv8.1-M Mainline relocations. */ -static bfd_vma -get_value_helper (bfd_vma plt_offset, - asection *splt, - asection *input_section, - asection *sym_sec, - struct elf_link_hash_entry * h, - struct bfd_link_info *info, - bfd *input_bfd, - Elf_Internal_Rela *rel, - const char *sym_name, - unsigned char st_type, - struct elf32_arm_link_hash_table *globals, - bfd_boolean *unresolved_reloc_p) -{ - bfd_vma value = 0; - enum arm_st_branch_type branch_type; - enum elf32_arm_stub_type stub_type = arm_stub_none; - struct elf32_arm_stub_hash_entry *stub_entry; - struct elf32_arm_link_hash_entry *hash - = (struct elf32_arm_link_hash_entry *)h; - - - if (plt_offset != (bfd_vma) -1) - { - value = (splt->output_section->vma - + splt->output_offset - + plt_offset); - value -= PLT_THUMB_STUB_SIZE; - *unresolved_reloc_p = FALSE; - } - - stub_type = arm_type_of_stub (info, input_section, rel, - st_type, &branch_type, - hash, value, sym_sec, - input_bfd, sym_name); - - if (stub_type != arm_stub_none) - { - stub_entry = elf32_arm_get_stub_entry (input_section, - sym_sec, h, - rel, globals, - stub_type); - if (stub_entry != NULL) - { - value = (stub_entry->stub_offset - + stub_entry->stub_sec->output_offset - + stub_entry->stub_sec->output_section->vma); - } - } - return value; -} - /* Perform a relocation as part of a final link. */ static bfd_reloc_status_type @@ -12968,14 +12915,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, addend |= (immC << 1); addend |= 1; /* Sign extend. */ - addend = (addend & 0x10000) ? addend - (1 << 17) : addend; + signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend; } - value = get_value_helper (plt_offset, splt, input_section, sym_sec, h, - info, input_bfd, rel, sym_name, st_type, - globals, unresolved_reloc_p); - - relocation = value + addend; + relocation = value + signed_addend; relocation -= (input_section->output_section->vma + input_section->output_offset + rel->r_offset); @@ -13014,13 +12957,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, addend |= 1; /* Sign extend. */ addend = (addend & 0x1000) ? addend - (1 << 13) : addend; + signed_addend = addend; } - value = get_value_helper (plt_offset, splt, input_section, sym_sec, h, - info, input_bfd, rel, sym_name, st_type, - globals, unresolved_reloc_p); - - relocation = value + addend; + relocation = value + signed_addend; relocation -= (input_section->output_section->vma + input_section->output_offset + rel->r_offset); @@ -13059,13 +12999,10 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, addend |= 1; /* Sign extend. */ addend = (addend & 0x40000) ? addend - (1 << 19) : addend; + signed_addend = addend; } - value = get_value_helper (plt_offset, splt, input_section, sym_sec, h, - info, input_bfd, rel, sym_name, st_type, - globals, unresolved_reloc_p); - - relocation = value + addend; + relocation = value + signed_addend; relocation -= (input_section->output_section->vma + input_section->output_offset + rel->r_offset); diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d index e429c136f2ea7818de2a7479a21f0cc6bc0702e1..bdb265c5a3aa8cc4f4d0112562249b559d468784 100644 --- a/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rel.d @@ -1,7 +1,7 @@ -#name: Valid Armv8.1-M Mainline BF instruction with relocation +#name: Valid Armv8.1-M Mainline BF instruction with REL #as: -march=armv8.1-m.main #objdump: -dr --prefix-addresses --show-raw-insn -#skip: *-*-pe *-wince-* +#skip: *-*-pe *-wince-* *-vxworks .*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d b/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d new file mode 100644 index 0000000000000000000000000000000000000000..d363d098523ae5ef54870f595b7aa8dd1bc7a226 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-rela.d @@ -0,0 +1,12 @@ +#name: Valid Armv8.1-M Mainline BF instruction with RELA +#as: -march=armv8.1-m.main +#objdump: -dr --prefix-addresses --show-raw-insn +#source:armv8_1-m-bf-rel.s +#noskip: *-vxworks + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f0c0 e001 bf 2, 00000004 <.target\+0x4> + 0: R_ARM_THM_BF16 .target-0x4 + diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf.d b/gas/testsuite/gas/arm/armv8_1-m-bf.d index dd30b2a2ff1d35cd58299813614ec5a79cbcdadf..99de065903bca1ffc407b043a0c9cd554c44a25e 100644 --- a/gas/testsuite/gas/arm/armv8_1-m-bf.d +++ b/gas/testsuite/gas/arm/armv8_1-m-bf.d @@ -5,9 +5,9 @@ .*: +file format .*arm.* Disassembly of section .text: -0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a +0[0-9a-f]+ <[^>]+> f0c0 e803 bf 2, 0000000a <.*> 0[0-9a-f]+ <[^>]+> 4609 mov r1, r1 -0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c +0[0-9a-f]+ <[^>]+> f140 e801 bf 4, 0000000c <.*> 0[0-9a-f]+ <[^>]+> 460a mov r2, r1 0[0-9a-f]+ <[^>]+> 4613 mov r3, r2 0[0-9a-f]+ <[^>]+> 4614 mov r4, r2 diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d index a498f06cd3e68370b737976ac3453855852f5b58..b66e9295f59e164533c2dd928fff5173ec6778be 100644 --- a/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d +++ b/gas/testsuite/gas/arm/armv8_1-m-bfcsel.d @@ -5,8 +5,8 @@ .*: +file format .*arm.* Disassembly of section .text: -0[0-9a-f]+ <[^>]+> f080 e803 bfcsel 2, 0000000a , 4, eq +0[0-9a-f]+ <[^>]+> f080 e803 bfcsel 2, 0000000a <.*>, 4, eq 0[0-9a-f]+ <[^>]+> 4609 mov r1, r1 -0[0-9a-f]+ <[^>]+> d000 beq.n 0000000a +0[0-9a-f]+ <[^>]+> d000 beq.n 0000000a <.*> 0[0-9a-f]+ <[^>]+> 4613 mov r3, r2 0[0-9a-f]+ <[^>]+> 4614 mov r4, r2 diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d index 13c6bf1caa5cb68844bd4b4d33acef9223edfa03..951074cff0962e5ee13ebf8219a0ab515df60f5f 100644 --- a/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d +++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rel.d @@ -1,7 +1,7 @@ -#name: Valid Armv8.1-M Mainline BFL instruction with relocation +#name: Valid Armv8.1-M Mainline BFL instruction with REL #as: -march=armv8.1-m.main #objdump: -dr --prefix-addresses --show-raw-insn -#skip: *-*-pe *-wince-* +#skip: *-*-pe *-wince-* *-vxworks .*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d b/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d new file mode 100644 index 0000000000000000000000000000000000000000..291d10b4af82d376a260d06ee6c434d6fe1b4f6a --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bfl-rela.d @@ -0,0 +1,12 @@ +#name: Valid Armv8.1-M Mainline BFL instruction with RELA +#as: -march=armv8.1-m.main +#objdump: -dr --prefix-addresses --show-raw-insn +#source: armv8_1-m-bfl-rel.s +#noskip: *-vxworks + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f080 c001 bfl 2, 00000004 <.target\+0x4> + 0: R_ARM_THM_BF18 .target-0x4 + diff --git a/gas/testsuite/gas/arm/armv8_1-m-bfl.d b/gas/testsuite/gas/arm/armv8_1-m-bfl.d index e15636b359f8db2829e46706f9cd0ea3e1d45500..b28d0b111e362c130b5c17b57749f1170c845e50 100644 --- a/gas/testsuite/gas/arm/armv8_1-m-bfl.d +++ b/gas/testsuite/gas/arm/armv8_1-m-bfl.d @@ -5,9 +5,9 @@ .*: +file format .*arm.* Disassembly of section .text: -0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a +0[0-9a-f]+ <[^>]+> f080 c803 bfl 2, 0000000a <.*> 0[0-9a-f]+ <[^>]+> 4608 mov r0, r1 -0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 0000000c +0[0-9a-f]+ <[^>]+> f100 c801 bfl 4, 0000000c <.*> 0[0-9a-f]+ <[^>]+> 460a mov r2, r1 0[0-9a-f]+ <[^>]+> 4613 mov r3, r2 0[0-9a-f]+ <[^>]+> 4614 mov r4, r2 diff --git a/gas/testsuite/gas/arm/armv8_1-m-loloop.d b/gas/testsuite/gas/arm/armv8_1-m-loloop.d index 1e02b82651f7127c5c98d3518a0a653445db4c9a..20506c692005d40e3ed328a0f27251e8663e27ed 100644 --- a/gas/testsuite/gas/arm/armv8_1-m-loloop.d +++ b/gas/testsuite/gas/arm/armv8_1-m-loloop.d @@ -6,12 +6,12 @@ .*: +file format .*arm.* Disassembly of section .text: -0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c +0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c <.*> 0[0-9a-f]+ <[^>]+> f042 e001 dls lr, r2 0[0-9a-f]+ <[^>]+> f04e e001 dls lr, lr -0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 -0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 -0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 -0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 +0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 <.*> +0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 <.*> +0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 <.*> +0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 <.*> 0[0-9a-f]+ <[^>]+> 4613 mov r3, r2 #... diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp index 5471895e63a68c0ee5e9c9644564e7b9235a4184..7d3217f87a26303f776d2390cdab9a426ef3d3e9 100644 --- a/ld/testsuite/ld-arm/arm-elf.exp +++ b/ld/testsuite/ld-arm/arm-elf.exp @@ -42,6 +42,11 @@ if {[istarget "arm-*-vxworks"]} { "" {vxworks2.s} {{readelf --segments vxworks2-static.sd}} "vxworks2"} + {"Branch future relocations for armv8.1-m.main target" + "-static -T arm.ld" + "" "" {bfs-0.s bfs-1.s} + {{objdump -dw branch-futures.d}} + "branch-futures"} } run_ld_link_tests $armvxworkstests run_dump_test "vxworks1-static" @@ -260,6 +265,10 @@ set armelftests_common_3 { {"ADDS thumb1 relocations for armv7-m target" "-static -T arm.ld" "" "" {thumb1-adds-armv7-m.s} {{objdump -dw thumb1-adds.d}} "thumb1-adds"} + {"Branch future relocations for armv8.1-m.main target" "-static -T arm.ld" + "" "" {bfs-0.s bfs-1.s} + {{objdump -dw branch-futures.d}} + "branch-futures"} } run_ld_link_tests $armelftests_common_1 diff --git a/ld/testsuite/ld-arm/bfs-0.s b/ld/testsuite/ld-arm/bfs-0.s new file mode 100644 index 0000000000000000000000000000000000000000..844417a56c6f35e56716ef929d3a81f09b7615b2 --- /dev/null +++ b/ld/testsuite/ld-arm/bfs-0.s @@ -0,0 +1,12 @@ +.arch armv8.1-m.main +.text +.syntax unified +.thumb +future: + bf branch, target + bfcsel branch, target, else, eq + bfl branch, target + add r0, r0, r1 +branch: + b target +else: diff --git a/ld/testsuite/ld-arm/bfs-1.s b/ld/testsuite/ld-arm/bfs-1.s new file mode 100644 index 0000000000000000000000000000000000000000..2b72819598edf1509d12cf8b01e5d2028bddda38 --- /dev/null +++ b/ld/testsuite/ld-arm/bfs-1.s @@ -0,0 +1,9 @@ +.arch armv8.1-m.main +.text +.syntax unified +.thumb +.global _start +.global target +_start: +target: + add r0, r0, r1 diff --git a/ld/testsuite/ld-arm/branch-futures.d b/ld/testsuite/ld-arm/branch-futures.d new file mode 100644 index 0000000000000000000000000000000000000000..427ecce62a4d2f22b3b64fe03435802845c567cf --- /dev/null +++ b/ld/testsuite/ld-arm/branch-futures.d @@ -0,0 +1,17 @@ + +.*: file format elf32-.* + + +Disassembly of section .text: + +0[0-9a-f]+ : + [0-9a-f]+: f2c0 e807 bf a, 8012 <_start> + [0-9a-f]+: f182 e805 bfcsel 6, 8012 <_start>, a, eq + [0-9a-f]+: f080 c803 bfl 2, 8012 <_start> + [0-9a-f]+: 4408 add r0, r1 + +0[0-9a-f]+ : + [0-9a-f]+: f000 b800 b.w 8012 <_start> + +0[0-9a-f]+ <_start>: + [0-9a-f]+: 4408 add r0, r1