Hi Richard,

(Apologies for you getting this twice, I hit the attachment limit)

I've now had time to run some more focussed testing on binutils, gcc, and 
glibc together to gain confidence in the new O32 ABI extensions. Assuming
the modifications made since last posting are OK I am therefore ready to
commit.	

The changes since v3 of this patch are below and shown in v3-v4.patch. 

* Merge together FPXX and odd-spreg work as they are now inseparable
* Ensure .MIPS.abiflags sections are not removed via --gc-sections
* Infer oddspreg from an object based on architecture
* Ensure there is no junk in .MIPS.abiflags:flags2.
* Re-work odd-spreg handling to support the new extensions, add new flags to
  single-precision floating-point data movement instructions to simplify logic.
* Infer -mno-odd-spreg for -mfpxx regardless of architecture.
* Fix for match_float_constant with r5900
* declassification of ctc1/cfc1 as FPU instructions. These are copro1 control
  instructions which are not 'using' the FPU.
* Add FP64A support
* Update docs for FP64A and minor typos

The biggest change is the introduction of one further O32 floating point ABI
extension, FP64A. This extension is based on FP64 but forbids the use of
odd-numbered single-precision registers. The background to this extension can
be found on:

https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#7._Defining_O32_FP64A

I've kept the testsuite changes separate in the patches but will commit
everything at once.

Thanks,
Matthew