* [PATCH][MIPS] file_mips_xxx consolidation
@ 2014-05-08 8:04 Matthew Fortune
2014-05-08 19:34 ` Richard Sandiford
0 siblings, 1 reply; 3+ messages in thread
From: Matthew Fortune @ 2014-05-08 8:04 UTC (permalink / raw)
To: Richard Sandiford; +Cc: binutils
[-- Attachment #1: Type: text/plain, Size: 875 bytes --]
Hi Richard,
Another patch split out of FPXX. This one consolidates all the file
scope variables into one new struct. I've included the change from
fp32 to fp as it makes later patches easier. All fp32 tests use
fp != 64 in preparation for FPXX.
Do you want the change to use a new FPR_SIZE macro to follow on
from this?
OK to commit? Check-gas passes for mips-mti-linux-gnu.
Regards,
Matthew
2014-05-07 Matthew Fortune <matthew.fortune@imgtec.com>
gas/
* config/tc-mips.c (mips_set_options): Rename fp32 field to fp.
Update fp32 == 0 to fp == 64 and fp32 == 1 to fp != 64 throughout.
(file_mips_gp32, file_mips_fp32, file_mips_soft_float,
file_mips_single_float, file_mips_isa, file_mips_arch): Delete.
Merge into one struct...
(file_mips_opts): Here. New static global. Update throughout
(mips_opts): Update defaults for gp32 and fp.
[-- Attachment #2: 0001-PATCH-MIPS-file_mips_xxx-consolidation.patch --]
[-- Type: application/octet-stream, Size: 16575 bytes --]
2014-05-07 Matthew Fortune <matthew.fortune@imgtec.com>
gas/
* config/tc-mips.c (mips_set_options): Rename fp32 field to fp.
Update fp32 == 0 to fp == 64 and fp32 == 1 to fp != 64 throughout.
(file_mips_gp32, file_mips_fp32, file_mips_soft_float,
file_mips_single_float, file_mips_isa, file_mips_arch): Delete.
Merge into one struct...
(file_mips_opts): Here. New static global. Update throughout
(mips_opts): Update defaults for gp32 and fp.
---
gas/config/tc-mips.c | 169 ++++++++++++++++++++++++-------------------------
1 files changed, 83 insertions(+), 86 deletions(-)
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index b80470c..798bce8 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -242,7 +242,7 @@ struct mips_set_options
to 32 bit. This is initially determined when -mgp32 or -mfp32
is passed but can changed if the assembler code uses .set mipsN. */
int gp32;
- int fp32;
+ int fp;
/* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
command line option, and the default CPU. */
int arch;
@@ -259,31 +259,30 @@ struct mips_set_options
bfd_boolean single_float;
};
-/* This is the struct we use to hold the current set of options. Note
- that we must set the isa field to ISA_UNKNOWN and the ASE fields to
- -1 to indicate that they have not been initialized. */
-
-/* True if -mgp32 was passed. */
-static int file_mips_gp32 = -1;
-
-/* True if -mfp32 was passed. */
-static int file_mips_fp32 = -1;
+/* True if -mnan=2008, false if -mnan=legacy. */
+static bfd_boolean mips_flag_nan2008 = FALSE;
-/* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
-static int file_mips_soft_float = 0;
+/* This is the struct we use to hold the module level set of options.
+ Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp32 and
+ fp fields to -1 to indicate that they have not been initialized. */
-/* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
-static int file_mips_single_float = 0;
+static struct mips_set_options file_mips_opts =
+{
+ /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
+ /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
+ /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
+ /* gp32 */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
+ /* soft_float */ FALSE, /* single_float */ FALSE
+};
-/* True if -mnan=2008, false if -mnan=legacy. */
-static bfd_boolean mips_flag_nan2008 = FALSE;
+/* This is similar to file_mips_opts, but for the current set of options. */
static struct mips_set_options mips_opts =
{
/* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
/* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
/* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
- /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
+ /* gp32 */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
/* soft_float */ FALSE, /* single_float */ FALSE
};
@@ -300,9 +299,6 @@ static unsigned int file_ase_explicit;
unsigned long mips_gprmask;
unsigned long mips_cprmask[4];
-/* MIPS ISA we are using for this output file. */
-static int file_mips_isa = ISA_UNKNOWN;
-
/* True if any MIPS16 code was produced. */
static int file_ase_mips16;
@@ -327,7 +323,6 @@ static int file_ase_micromips;
#endif
/* The argument of the -march= flag. The architecture we are assembling. */
-static int file_mips_arch = CPU_UNKNOWN;
static const char *mips_arch_string;
/* The argument of the -mtune= flag. The architecture for which we
@@ -398,7 +393,7 @@ static int mips_32bitmode = 0;
(mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
#define HAVE_32BIT_FPRS \
- (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
+ (mips_opts.fp != 64 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
@@ -1915,7 +1910,7 @@ mips_check_isa_supports_ase (const struct mips_ase *ase)
ase->name, base, size, min_rev);
}
if ((ase->flags & FP64_ASES)
- && mips_opts.fp32
+ && mips_opts.fp != 64
&& (warned_fp32 & ase->flags) != ase->flags)
{
warned_fp32 |= ase->flags;
@@ -3346,7 +3341,7 @@ md_begin (void)
g_switch_value = 0;
}
- if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
+ if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
as_warn (_("could not set architecture and machine"));
op_hash = hash_new ();
@@ -13508,39 +13503,39 @@ md_parse_option (int c, char *arg)
break;
case OPTION_MIPS1:
- file_mips_isa = ISA_MIPS1;
+ file_mips_opts.isa = ISA_MIPS1;
break;
case OPTION_MIPS2:
- file_mips_isa = ISA_MIPS2;
+ file_mips_opts.isa = ISA_MIPS2;
break;
case OPTION_MIPS3:
- file_mips_isa = ISA_MIPS3;
+ file_mips_opts.isa = ISA_MIPS3;
break;
case OPTION_MIPS4:
- file_mips_isa = ISA_MIPS4;
+ file_mips_opts.isa = ISA_MIPS4;
break;
case OPTION_MIPS5:
- file_mips_isa = ISA_MIPS5;
+ file_mips_opts.isa = ISA_MIPS5;
break;
case OPTION_MIPS32:
- file_mips_isa = ISA_MIPS32;
+ file_mips_opts.isa = ISA_MIPS32;
break;
case OPTION_MIPS32R2:
- file_mips_isa = ISA_MIPS32R2;
+ file_mips_opts.isa = ISA_MIPS32R2;
break;
case OPTION_MIPS64R2:
- file_mips_isa = ISA_MIPS64R2;
+ file_mips_opts.isa = ISA_MIPS64R2;
break;
case OPTION_MIPS64:
- file_mips_isa = ISA_MIPS64;
+ file_mips_opts.isa = ISA_MIPS64;
break;
case OPTION_MTUNE:
@@ -13748,35 +13743,35 @@ md_parse_option (int c, char *arg)
break;
case OPTION_GP32:
- file_mips_gp32 = 1;
+ file_mips_opts.gp32 = 1;
break;
case OPTION_GP64:
- file_mips_gp32 = 0;
+ file_mips_opts.gp32 = 0;
break;
case OPTION_FP32:
- file_mips_fp32 = 1;
+ file_mips_opts.fp = 32;
break;
case OPTION_FP64:
- file_mips_fp32 = 0;
+ file_mips_opts.fp = 64;
break;
case OPTION_SINGLE_FLOAT:
- file_mips_single_float = 1;
+ file_mips_opts.single_float = 1;
break;
case OPTION_DOUBLE_FLOAT:
- file_mips_single_float = 0;
+ file_mips_opts.single_float = 0;
break;
case OPTION_SOFT_FLOAT:
- file_mips_soft_float = 1;
+ file_mips_opts.soft_float = 1;
break;
case OPTION_HARD_FLOAT:
- file_mips_soft_float = 0;
+ file_mips_opts.soft_float = 0;
break;
case OPTION_MABI:
@@ -13859,7 +13854,7 @@ mips_set_architecture (const struct mips_cpu_info *info)
{
if (info != 0)
{
- file_mips_arch = info->cpu;
+ file_mips_opts.arch = info->cpu;
mips_opts.arch = info->cpu;
mips_opts.isa = info->isa;
}
@@ -13901,9 +13896,9 @@ mips_after_parse_args (void)
if (mips_arch_string != 0)
arch_info = mips_parse_cpu ("-march", mips_arch_string);
- if (file_mips_isa != ISA_UNKNOWN)
+ if (file_mips_opts.isa != ISA_UNKNOWN)
{
- /* Handle -mipsN. At this point, file_mips_isa contains the
+ /* Handle -mipsN. At this point, file_mips_opts.isa contains the
ISA level specified by -mipsN, while arch_info->isa contains
the -march selection (if any). */
if (arch_info != 0)
@@ -13911,14 +13906,14 @@ mips_after_parse_args (void)
/* -march takes precedence over -mipsN, since it is more descriptive.
There's no harm in specifying both as long as the ISA levels
are the same. */
- if (file_mips_isa != arch_info->isa)
+ if (file_mips_opts.isa != arch_info->isa)
as_bad (_("-%s conflicts with the other architecture options,"
" which imply -%s"),
- mips_cpu_info_from_isa (file_mips_isa)->name,
+ mips_cpu_info_from_isa (file_mips_opts.isa)->name,
mips_cpu_info_from_isa (arch_info->isa)->name);
}
else
- arch_info = mips_cpu_info_from_isa (file_mips_isa);
+ arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
}
if (arch_info == 0)
@@ -13933,7 +13928,8 @@ mips_after_parse_args (void)
mips_set_architecture (arch_info);
- /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
+ /* Optimize for file_mips_opts.arch, unless -mtune selects a different
+ processor. */
if (mips_tune_string != 0)
tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
@@ -13942,15 +13938,15 @@ mips_after_parse_args (void)
else
mips_set_tune (tune_info);
- if (file_mips_gp32 >= 0)
+ if (file_mips_opts.gp32 >= 0)
{
/* The user specified the size of the integer registers. Make sure
it agrees with the ABI and ISA. */
- if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
+ if (file_mips_opts.gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
as_bad (_("-mgp64 used with a 32-bit processor"));
- else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
+ else if (file_mips_opts.gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
as_bad (_("-mgp32 used with a 64-bit ABI"));
- else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
+ else if (file_mips_opts.gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
as_bad (_("-mgp64 used with a 32-bit ABI"));
}
else
@@ -13958,11 +13954,11 @@ mips_after_parse_args (void)
/* Infer the integer register size from the ABI and processor.
Restrict ourselves to 32-bit registers if that's all the
processor has, or if the ABI cannot handle 64-bit registers. */
- file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
- || !ISA_HAS_64BIT_REGS (mips_opts.isa));
+ file_mips_opts.gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
+ || !ISA_HAS_64BIT_REGS (mips_opts.isa));
}
- switch (file_mips_fp32)
+ switch (file_mips_opts.fp)
{
default:
case -1:
@@ -13973,28 +13969,28 @@ mips_after_parse_args (void)
registers would lead to spurious "register must be even" messages.
So here we assume float registers are never smaller than the
integer ones. */
- if (file_mips_gp32 == 0)
+ if (file_mips_opts.gp32 == 0)
/* 64-bit integer registers implies 64-bit float registers. */
- file_mips_fp32 = 0;
+ file_mips_opts.fp = 64;
else if ((mips_opts.ase & FP64_ASES)
&& ISA_HAS_64BIT_FPRS (mips_opts.isa))
/* -mips3d and -mdmx imply 64-bit float registers, if possible. */
- file_mips_fp32 = 0;
+ file_mips_opts.fp = 64;
else
/* 32-bit float registers. */
- file_mips_fp32 = 1;
+ file_mips_opts.fp = 32;
break;
/* The user specified the size of the float registers. Check if it
agrees with the ABI and ISA. */
- case 0:
+ case 64:
if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
as_bad (_("-mfp64 used with a 32-bit fpu"));
else if (ABI_NEEDS_32BIT_REGS (mips_abi)
&& !ISA_HAS_MXHC1 (mips_opts.isa))
as_warn (_("-mfp64 used with a 32-bit ABI"));
break;
- case 1:
+ case 32:
if (ABI_NEEDS_64BIT_REGS (mips_abi))
as_warn (_("-mfp32 used with a 64-bit ABI"));
break;
@@ -14005,7 +14001,7 @@ mips_after_parse_args (void)
/* This flag is set when we have a 64-bit capable CPU but use only
32-bit wide registers. Note that EABI does not use it. */
if (ISA_HAS_64BIT_REGS (mips_opts.isa)
- && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
+ && ((mips_abi == NO_ABI && file_mips_opts.gp32 == 1)
|| mips_abi == O32_ABI))
mips_32bitmode = 1;
@@ -14015,25 +14011,26 @@ mips_after_parse_args (void)
/* If the selected architecture includes support for ASEs, enable
generation of code for them. */
if (mips_opts.mips16 == -1)
- mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
+ mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
if (mips_opts.micromips == -1)
- mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
+ mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
+ ? 1 : 0;
/* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those
ASEs from being selected implicitly. */
- if (file_mips_fp32 == 1)
+ if (file_mips_opts.fp != 64)
file_ase_explicit |= ASE_MIPS3D | ASE_MDMX;
/* If the user didn't explicitly select or deselect a particular ASE,
use the default setting for the CPU. */
mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
- file_mips_isa = mips_opts.isa;
- file_ase = mips_opts.ase;
- mips_opts.gp32 = file_mips_gp32;
- mips_opts.fp32 = file_mips_fp32;
- mips_opts.soft_float = file_mips_soft_float;
- mips_opts.single_float = file_mips_single_float;
+ file_mips_opts.isa = mips_opts.isa;
+ file_mips_opts.ase = mips_opts.ase;
+ mips_opts.gp32 = file_mips_opts.gp32;
+ mips_opts.fp = file_mips_opts.fp;
+ mips_opts.soft_float = file_mips_opts.soft_float;
+ mips_opts.single_float = file_mips_opts.single_float;
mips_check_isa_supports_ases ();
@@ -14989,7 +14986,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
mips_opts.nobopt = 1;
}
else if (strcmp (name, "gp=default") == 0)
- mips_opts.gp32 = file_mips_gp32;
+ mips_opts.gp32 = file_mips_opts.gp32;
else if (strcmp (name, "gp=32") == 0)
mips_opts.gp32 = 1;
else if (strcmp (name, "gp=64") == 0)
@@ -15000,15 +14997,15 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
mips_opts.gp32 = 0;
}
else if (strcmp (name, "fp=default") == 0)
- mips_opts.fp32 = file_mips_fp32;
+ mips_opts.fp = file_mips_opts.fp;
else if (strcmp (name, "fp=32") == 0)
- mips_opts.fp32 = 1;
+ mips_opts.fp = 32;
else if (strcmp (name, "fp=64") == 0)
{
if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
as_warn (_("%s isa does not support 64-bit floating point registers"),
mips_cpu_info_from_isa (mips_opts.isa)->name);
- mips_opts.fp32 = 0;
+ mips_opts.fp = 64;
}
else if (strcmp (name, "softfloat") == 0)
mips_opts.soft_float = 1;
@@ -15051,8 +15048,8 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
{
reset = 1;
- mips_opts.isa = file_mips_isa;
- mips_opts.arch = file_mips_arch;
+ mips_opts.isa = file_mips_opts.isa;
+ mips_opts.arch = file_mips_opts.arch;
}
else if (strncmp (name, "arch=", 5) == 0)
{
@@ -15092,7 +15089,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
case ISA_MIPS32:
case ISA_MIPS32R2:
mips_opts.gp32 = 1;
- mips_opts.fp32 = 1;
+ mips_opts.fp = 32;
break;
case ISA_MIPS3:
case ISA_MIPS4:
@@ -15102,11 +15099,11 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
mips_opts.gp32 = 0;
if (mips_opts.arch == CPU_R5900)
{
- mips_opts.fp32 = 1;
+ mips_opts.fp = 32;
}
else
{
- mips_opts.fp32 = 0;
+ mips_opts.fp = 64;
}
break;
default:
@@ -15115,8 +15112,8 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
}
if (reset)
{
- mips_opts.gp32 = file_mips_gp32;
- mips_opts.fp32 = file_mips_fp32;
+ mips_opts.gp32 = file_mips_opts.gp32;
+ mips_opts.fp = file_mips_opts.fp;
}
}
else if (strcmp (name, "autoextend") == 0)
@@ -17340,7 +17337,7 @@ mips_elf_final_processing (void)
elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
else if (mips_abi == EABI_ABI)
{
- if (!file_mips_gp32)
+ if (!file_mips_opts.gp32)
elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
else
elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
@@ -17357,7 +17354,7 @@ mips_elf_final_processing (void)
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
/* 32 bit code with 64 bit FP registers. */
- if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
+ if (file_mips_opts.fp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
}
\f
@@ -18027,8 +18024,8 @@ mips_parse_cpu (const char *option, const char *cpu_string)
if (ABI_NEEDS_64BIT_REGS (mips_abi))
return mips_cpu_info_from_isa (ISA_MIPS3);
- if (file_mips_gp32 >= 0)
- return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
+ if (file_mips_opts.gp32 >= 0)
+ return mips_cpu_info_from_isa (file_mips_opts.gp32 ? ISA_MIPS1 : ISA_MIPS3);
return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
? ISA_MIPS3
--
1.7.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH][MIPS] file_mips_xxx consolidation
2014-05-08 8:04 [PATCH][MIPS] file_mips_xxx consolidation Matthew Fortune
@ 2014-05-08 19:34 ` Richard Sandiford
2014-05-08 21:14 ` Matthew Fortune
0 siblings, 1 reply; 3+ messages in thread
From: Richard Sandiford @ 2014-05-08 19:34 UTC (permalink / raw)
To: Matthew Fortune; +Cc: binutils
Matthew Fortune <Matthew.Fortune@imgtec.com> writes:
> Do you want the change to use a new FPR_SIZE macro to follow on
> from this?
Yeah, I think it makes sense to do that separately from this patch.
Just one minor nit:
> @@ -18027,8 +18024,8 @@ mips_parse_cpu (const char *option, const char *cpu_string)
> if (ABI_NEEDS_64BIT_REGS (mips_abi))
> return mips_cpu_info_from_isa (ISA_MIPS3);
>
> - if (file_mips_gp32 >= 0)
> - return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
> + if (file_mips_opts.gp32 >= 0)
> + return mips_cpu_info_from_isa (file_mips_opts.gp32 ? ISA_MIPS1 : ISA_MIPS3);
>
> return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
> ? ISA_MIPS3
This line is now longer than 80 chars so please break before "?" or ":".
OK with that change, thanks.
Richard
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH][MIPS] file_mips_xxx consolidation
2014-05-08 19:34 ` Richard Sandiford
@ 2014-05-08 21:14 ` Matthew Fortune
0 siblings, 0 replies; 3+ messages in thread
From: Matthew Fortune @ 2014-05-08 21:14 UTC (permalink / raw)
To: Richard Sandiford; +Cc: binutils
Richard Sandiford <rdsandiford@googlemail.com> writes:
> Matthew Fortune <Matthew.Fortune@imgtec.com> writes:
> > Do you want the change to use a new FPR_SIZE macro to follow on
> > from this?
>
> Yeah, I think it makes sense to do that separately from this patch.
>
> Just one minor nit:
>
> > @@ -18027,8 +18024,8 @@ mips_parse_cpu (const char *option, const char
> *cpu_string)
> > if (ABI_NEEDS_64BIT_REGS (mips_abi))
> > return mips_cpu_info_from_isa (ISA_MIPS3);
> >
> > - if (file_mips_gp32 >= 0)
> > - return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 :
> ISA_MIPS3);
> > + if (file_mips_opts.gp32 >= 0)
> > + return mips_cpu_info_from_isa (file_mips_opts.gp32 ? ISA_MIPS1 :
> ISA_MIPS3);
> >
> > return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
> > ? ISA_MIPS3
>
> This line is now longer than 80 chars so please break before "?" or ":".
>
> OK with that change, thanks.
Committed. I'm afraid I had to do a follow-up commit as I tested the wrong
source and missed the interaction with Andrew's mips[32|64]r[35] patch,
sorry.
Regards,
Matthew
gas/
* config/tc-mips.c (md_parse_option): Update missed file_mips_isa
references.
---
gas/ChangeLog | 5 +++++
gas/config/tc-mips.c | 8 ++++----
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 85f90a5..737f047 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2014-05-08 Matthew Fortune <matthew.fortune@imgtec.com>
+ * config/tc-mips.c (md_parse_option): Update missed file_mips_isa
+ references.
+
+2014-05-08 Matthew Fortune <matthew.fortune@imgtec.com>
+
* config/tc-mips.c (mips_set_options): Rename fp32 field to fp.
Update fp32 == 0 to fp == 64 and fp32 == 1 to fp != 64 throughout.
(file_mips_gp32, file_mips_fp32, file_mips_soft_float,
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 6e77273..12e9792 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -13573,11 +13573,11 @@ md_parse_option (int c, char *arg)
break;
case OPTION_MIPS32R3:
- file_mips_isa = ISA_MIPS32R3;
+ file_mips_opts.isa = ISA_MIPS32R3;
break;
case OPTION_MIPS32R5:
- file_mips_isa = ISA_MIPS32R5;
+ file_mips_opts.isa = ISA_MIPS32R5;
break;
case OPTION_MIPS64R2:
@@ -13585,11 +13585,11 @@ md_parse_option (int c, char *arg)
break;
case OPTION_MIPS64R3:
- file_mips_isa = ISA_MIPS64R3;
+ file_mips_opts.isa = ISA_MIPS64R3;
break;
case OPTION_MIPS64R5:
- file_mips_isa = ISA_MIPS64R5;
+ file_mips_opts.isa = ISA_MIPS64R5;
break;
case OPTION_MIPS64:
--
1.7.1
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2014-05-08 21:14 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2014-05-08 8:04 [PATCH][MIPS] file_mips_xxx consolidation Matthew Fortune
2014-05-08 19:34 ` Richard Sandiford
2014-05-08 21:14 ` Matthew Fortune
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