From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id C91E738582AF for ; Sat, 13 Aug 2022 10:11:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C91E738582AF Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 24E62300089; Sat, 13 Aug 2022 10:11:18 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , "H . Peter Anvin" , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v6 2/4] RISC-V: Fix RV32 disassembler address computation Date: Sat, 13 Aug 2022 19:10:42 +0900 Message-Id: <6cf06b9c9d9c500c934400a999fab347e373ae33.1660385389.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 13 Aug 2022 10:11:21 -0000 If either the base register is `zero', `tp' or `gp' and XLEN is 32, an incorrectly sign-extended address is produced when printing. This commit fixes this bug (including PR29342) by fitting an address into a 32-bit value on RV32. gas/ChangeLog: * testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix. opcodes/ChangeLog: * riscv-dis.c (maybe_print_address): Clarify the role of the `wide' argument and rename to `is_addiw'. Fit the address into 32-bit on RV32. (print_insn_args): Reflect bool type of `is_addiw'. --- gas/testsuite/gas/riscv/lla32.d | 2 +- opcodes/riscv-dis.c | 24 ++++++++++++++---------- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/gas/testsuite/gas/riscv/lla32.d b/gas/testsuite/gas/riscv/lla32.d index 9d875629064..8e9324c1c96 100644 --- a/gas/testsuite/gas/riscv/lla32.d +++ b/gas/testsuite/gas/riscv/lla32.d @@ -14,6 +14,6 @@ Disassembly of section .text: 10: 00001537 lui a0,0x1 14: fff50513 addi a0,a0,-1 # fff 18: 80000537 lui a0,0x80000 - 1c: fff50513 addi a0,a0,-1 # 7fffffff + 1c: fff50513 addi a0,a0,-1 # 7fffffff 20: 00000513 li a0,0 24: fff00513 li a0,-1 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index c6d80c3ba49..419c4746db9 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -172,7 +172,7 @@ arg_print (struct disassemble_info *info, unsigned long val, static void maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset, - int wide) + bool is_addiw) { if (pd->hi_addr[base_reg] != (bfd_vma)-1) { @@ -187,9 +187,13 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset, return; pd->to_print_addr = true; - /* Sign-extend a 32-bit value to a 64-bit value. */ - if (wide) + /* On ADDIW, Sign-extend a 32-bit value to a 64-bit value. */ + if (is_addiw) pd->print_addr = (bfd_vma)(int32_t) pd->print_addr; + + /* Fit into a 32-bit value on RV32. */ + if (xlen == 32) + pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr; } /* Print insn arguments for 32/64-bit code. */ @@ -239,10 +243,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case 'o': case 'j': if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0) - maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0); + maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), false); if (info->mach == bfd_mach_riscv64 && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0) - maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1); + maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), true); print (info->stream, dis_style_immediate, "%d", (int)EXTRACT_CITYPE_IMM (l)); break; @@ -402,7 +406,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case 'b': case 's': if ((l & MASK_JALR) == MATCH_JALR) - maybe_print_address (pd, rs1, 0, 0); + maybe_print_address (pd, rs1, 0, false); print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]); break; @@ -432,21 +436,21 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info break; case 'o': - maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false); /* Fall through. */ case 'j': if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) || (l & MASK_JALR) == MATCH_JALR) - maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false); if (info->mach == bfd_mach_riscv64 && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0) - maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1); + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), true); print (info->stream, dis_style_immediate, "%d", (int)EXTRACT_ITYPE_IMM (l)); break; case 'q': - maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0); + maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), false); print (info->stream, dis_style_address_offset, "%d", (int)EXTRACT_STYPE_IMM (l)); break; -- 2.34.1