From: Jan Beulich <jbeulich@suse.com>
To: "binutils@sourceware.org" <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH v5 1/5] x86: also disallow non-byte/-word registers with byte/word suffix
Date: Tue, 11 Feb 2020 10:25:00 -0000 [thread overview]
Message-ID: <6fbca201-5ae8-cf70-0614-f7f2efa6628f@suse.com> (raw)
In-Reply-To: <1e1b8eba-93ff-39ed-460a-a922d12af27e@suse.com>
Along the lines of be4c5e58bd ("x86: Always disallow double word suffix
with word general register") also adjust check_{byte,word}_reg(), to make
overall behavior consistent again in this regard.
gas/
2020-02-XX Jan Beulich <jbeulich@suse.com>
PR gas/25438
* config/tc-i386.c (REGISTER_WARNINGS): Delete.
(check_byte_reg): Skip only source operand of CRC32. Drop Non-
64-bit-only warning.
(check_word_reg): Consistently error on mismatching register
size and suffix.
* testsuite/gas/i386/general.s: Replace dword GPR with word one
for movw. Replace suffix / GPR for orb.
* testsuite/gas/i386/inval.s: Add tests for movw with dword and
byte GPRs as well as ones for inb/outb with a word accumulator.
* testsuite/gas/i386/general.l, testsuite/gas/i386/intelbad.l,
testsuite/gas/i386/inval.l: Adjust expectations.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -44,10 +44,6 @@
#endif
#endif
-#ifndef REGISTER_WARNINGS
-#define REGISTER_WARNINGS 1
-#endif
-
#ifndef INFER_ADDR_PREFIX
#define INFER_ADDR_PREFIX 1
#endif
@@ -6637,31 +6633,10 @@ check_byte_reg (void)
&& i.tm.operand_types[op].bitfield.word)
continue;
- /* crc32 doesn't generate this warning. */
- if (i.tm.base_opcode == 0xf20f38f0)
+ /* crc32 only wants its source operand checked here. */
+ if (i.tm.base_opcode == 0xf20f38f0 && op)
continue;
- if ((i.types[op].bitfield.word
- || i.types[op].bitfield.dword
- || i.types[op].bitfield.qword)
- && i.op[op].regs->reg_num < 4
- /* Prohibit these changes in 64bit mode, since the lowering
- would be more complicated. */
- && flag_code != CODE_64BIT)
- {
-#if REGISTER_WARNINGS
- if (!quiet_warnings)
- as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
- register_prefix,
- (i.op[op].regs + (i.types[op].bitfield.word
- ? REGNAM_AL - REGNAM_AX
- : REGNAM_AL - REGNAM_EAX))->reg_name,
- register_prefix,
- i.op[op].regs->reg_name,
- i.suffix);
-#endif
- continue;
- }
/* Any other register is bad. */
if (i.types[op].bitfield.class == Reg
|| i.types[op].bitfield.class == RegMMX
@@ -6817,29 +6792,17 @@ check_word_reg (void)
i.suffix);
return 0;
}
- /* Warn if the e or r prefix on a general reg is present. */
- else if ((!quiet_warnings || flag_code == CODE_64BIT)
- && (i.types[op].bitfield.dword
+ /* Error if the e or r prefix on a general reg is present. */
+ else if ((i.types[op].bitfield.dword
|| i.types[op].bitfield.qword)
&& (i.tm.operand_types[op].bitfield.class == Reg
|| i.tm.operand_types[op].bitfield.instance == Accum)
&& i.tm.operand_types[op].bitfield.word)
{
- /* Prohibit these changes in the 64bit mode, since the
- lowering is more complicated. */
- if (flag_code == CODE_64BIT)
- {
- as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
- register_prefix, i.op[op].regs->reg_name,
- i.suffix);
- return 0;
- }
-#if REGISTER_WARNINGS
- as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
- register_prefix,
- (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
- register_prefix, i.op[op].regs->reg_name, i.suffix);
-#endif
+ as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
+ register_prefix, i.op[op].regs->reg_name,
+ i.suffix);
+ return 0;
}
return 1;
}
--- a/gas/testsuite/gas/i386/general.l
+++ b/gas/testsuite/gas/i386/general.l
@@ -9,12 +9,6 @@
.*:25: Warning:.*
.*:27: Warning:.*
.*:29: Warning:.*
-.*:48: Warning:.*
-.*:51: Warning:.*
-.*:124: Warning:.*
-.*:125: Warning:.*
-.*:126: Warning:.*
-.*:127: Warning:.*
.*:128: Warning:.*
.*:129: Warning:.*
.*:130: Warning:.*
@@ -90,12 +84,10 @@
45 008d 661F popw %ds
46 008f 668CD8 mov %ds,%ax
47 0092 668CD8 movw %ds,%ax
- 48 0095 668CD8 movw %ds,%eax
-.*Warning:.*
+ 48 0095 668CDF movw %ds,%di
49 0098 8ED8 mov %ax,%ds
50 009a 8ED8 movw %ax,%ds
- 51 009c 8ED8 movw %eax,%ds
-.*Warning:.*
+ 51 009c 8EDF movw %di,%ds
52
53 # test various pushes
54 009e 6A0A pushl \$10
@@ -167,15 +159,11 @@
120 012e 0F9303 setaeb \(%ebx\)
121 0131 0F93C0 setae %al
122
- 123 #these should give warnings
- 124 0134 0C01 orb \$1,%ax
-.*Warning:.*
- 125 0136 0C01 orb \$1,%eax
-.*Warning:.*
- 126 0138 80CB01 orb \$1,%bx
-.*Warning:.*
- 127 013b 80CB01 orb \$1,%ebx
-.*Warning:.*
+ 123 0134 0C01 orb \$1,%al
+ 124 0136 0D000100 00 orl \$0x100,%eax
+ 125 013b 80CB01 orb \$1,%bl
+ 126
+ 127 #these should give warnings
128 013e D9C1 fldl %st\(1\)
.*Warning:.*
129 0140 DDD2 fstl %st\(2\)
--- a/gas/testsuite/gas/i386/general.s
+++ b/gas/testsuite/gas/i386/general.s
@@ -45,10 +45,10 @@
popw %ds
mov %ds,%ax
movw %ds,%ax
- movw %ds,%eax
+ movw %ds,%di
mov %ax,%ds
movw %ax,%ds
- movw %eax,%ds
+ movw %di,%ds
# test various pushes
pushl $10
@@ -120,11 +120,11 @@
setaeb (%ebx)
setae %al
+ orb $1,%al
+ orl $0x100,%eax
+ orb $1,%bl
+
#these should give warnings
- orb $1,%ax
- orb $1,%eax
- orb $1,%bx
- orb $1,%ebx
fldl %st(1)
fstl %st(2)
fstpl %st(3)
--- a/gas/testsuite/gas/i386/intelbad.l
+++ b/gas/testsuite/gas/i386/intelbad.l
@@ -154,7 +154,7 @@
.*:172: Error: .*
.*:174: Error: .*
.*:175: Error: .*
-.*:176: Warning: .*
+.*:176: Error: .*
.*:177: Error: .*
.*:178: Error: .*
.*:180: Error: .*
--- a/gas/testsuite/gas/i386/inval.l
+++ b/gas/testsuite/gas/i386/inval.l
@@ -91,6 +91,12 @@
.*:104: Error: .*
.*:105: Error: .*
.*:106: Error: .*
+.*:108: Error: .*
+.*:109: Error: .*
+.*:110: Error: .*
+.*:112: Error: .*
+.*:113: Error: .*
+.*:114: Error: .*
GAS LISTING .*
@@ -203,3 +209,14 @@ GAS LISTING .*
[ ]*[1-9][0-9]*[ ]+movl %ds, %ax
[ ]*[1-9][0-9]*[ ]+movl %ax, %ds
[ ]*[1-9][0-9]*[ ]+movl %ax, %bx
+[ ]*[1-9][0-9]*[ ]+
+[ ]*[1-9][0-9]*[ ]+movw %ds, %eax
+[ ]*[1-9][0-9]*[ ]+movw %eax, %ds
+[ ]*[1-9][0-9]*[ ]+movw %eax, %ebx
+[ ]*[1-9][0-9]*[ ]+
+[ ]*[1-9][0-9]*[ ]+inb %dx, %ax
+[ ]*[1-9][0-9]*[ ]+outb %ax, %dx
+[ ]*[1-9][0-9]*[ ]+movb %ax, %bx
+\fGAS LISTING .*
+
+
--- a/gas/testsuite/gas/i386/inval.s
+++ b/gas/testsuite/gas/i386/inval.s
@@ -104,3 +104,11 @@ movnti word ptr [eax], ax
movl %ds, %ax
movl %ax, %ds
movl %ax, %bx
+
+ movw %ds, %eax
+ movw %eax, %ds
+ movw %eax, %ebx
+
+ inb %dx, %ax
+ outb %ax, %dx
+ movb %ax, %bx
next prev parent reply other threads:[~2020-02-11 10:25 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-11 10:23 [PATCH v5 0/5] x86: operand size handling improvements Jan Beulich
2020-02-11 10:25 ` [PATCH v5 2/5] x86: move certain MOVSX/MOVZX tests Jan Beulich
2020-02-11 11:43 ` H.J. Lu
2020-02-11 11:55 ` Jan Beulich
2020-02-11 12:20 ` H.J. Lu
2020-02-11 12:58 ` Jan Beulich
2020-02-11 13:02 ` H.J. Lu
2020-02-11 13:04 ` Jan Beulich
2020-02-11 13:07 ` H.J. Lu
2020-02-11 16:45 ` Jan Beulich
2020-02-11 17:04 ` H.J. Lu
2020-02-11 20:12 ` [PATCH] x86: Remove movsx/movzx with memory operand from AT&T syntax H.J. Lu
2020-02-11 23:34 ` H.J. Lu
2020-02-11 23:52 ` H.J. Lu
2020-02-12 3:19 ` [PATCH] x86: Remove movsx/movzx with 16/32-bit " H.J. Lu
2020-02-12 9:19 ` Jan Beulich
2020-02-11 10:25 ` [PATCH v5 3/5] x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX Jan Beulich
2020-02-11 10:25 ` Jan Beulich [this message]
2020-02-11 11:27 ` [PATCH v5 1/5] x86: also disallow non-byte/-word registers with byte/word suffix H.J. Lu
2020-02-11 10:26 ` [PATCH v5 4/5] x86: correct VFPCLASSP{S,D} operand size handling Jan Beulich
2020-02-11 11:50 ` H.J. Lu
2020-02-11 12:49 ` Jan Beulich
2020-02-11 12:56 ` H.J. Lu
2020-02-11 10:27 ` [PATCH v5 5/5] x86-64: Intel64 adjustments for insns dealing with far pointers Jan Beulich
2020-02-11 11:53 ` H.J. Lu
2020-02-12 8:11 ` Jan Beulich
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