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Lu" From: Jan Beulich Subject: [RFC] x86: proposal for a new .insn directive Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: FR2P281CA0019.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:14::6) To VE1PR04MB6560.eurprd04.prod.outlook.com (2603:10a6:803:122::25) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VE1PR04MB6560:EE_|DB9PR04MB9428:EE_ X-MS-Office365-Filtering-Correlation-Id: a94164ef-fb2f-4873-cdad-08daf55d75d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sDF3NQMB1+AZ68TGEJEda2lG3Wduake+C/7ClkfolJbsHF+c0+iM27Tjux1mKkxvMbrMtLsGE9zyG6VAlNrxt3zijNUQACZqn6QmzDTDFI2x6DV41vUeoABqzWd+xmBDApfAzW7L7VA3+oiKVCSFsZVaaN8xwdsQ0EzVSQdzIy9DvgYGY4JD4vTsVSieZRUAZcKZCEyP80bPoMTJCPHIqr8xVG6mQpTvJrSSpGE6B7TQZsvHBH/eFW1OsL8Adw3JbyGK5G5xnYf8lYPkpdvc0Zn7R7nKO1Bm2UEF0O1/Krq13Z0BG5gMeY3yR3ktWU6Y5EKMnnJH9lzsNN2vmFRnbZaZT/BfuJnHM6zLzMntNiOwm8i68CJMBid5/0mdUC5utMI90RsZTzuX1AqkL3yNLWCqZ6nRQ3aL7/1GY90ZyQLo+GSiAaBWGxetcVH79WTMUkFScSBD0naNNSq1G/SLlg6JbLB+lHhM72AjEwo9fqy1SyxFYgnbirGMJa79/Q/UQ7G4WGSNhKzeQ64jgDP1rxf/jbPq7xMYuSklfj/IxEP1BGd4kSuXsf/t9RIHZPOPynEGu5ZZ7grfAZg/MBIDgxYUmIfsQaqwldcGt5TkuXDzHrnzdEVuCzZG2a6KaqPV4h5+cJfhcIRwTsrPvwarcPUmUMdQ/hLEmijYsJ3hJTkJh6LWOg/bgW04DDVYYE19ZFi/0JOsdgmX7RW10Lwsedo8u2wSUn6oHsyMwJJlYbWqj3LVpS0BMqskiRZJjygW X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VE1PR04MB6560.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(136003)(366004)(376002)(346002)(39860400002)(396003)(451199015)(6512007)(86362001)(66899015)(31686004)(2906002)(4326008)(5660300002)(8936002)(36756003)(41300700001)(66556008)(66476007)(8676002)(66946007)(38100700002)(83380400001)(6916009)(31696002)(316002)(26005)(6506007)(2616005)(186003)(478600001)(6486002)(142923001)(43740500002)(45980500001);DIR:OUT;SFP:1101; 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This is in particular related to the building of the ModR/M and SIB bytes as well the VEX/XOP/EVEX prefixes. I would appreciate feedback on the proposal (in form of an assembly source file, providing examples at the same time). Besides pointing out issues / oversights, thoughts on the various TBDs would be helpful. Thanks, Jan .text insn: # .insn [] [] [+r|/] [,[,...]] # Legacy encoding prefixes altering encoding space (0x0f, 0x0f38, 0x0f3a) # have to be specified as high byte(s) of . This also extends # to certain FPU opcodes or sub-spaces like that of major opcode 0x0f01. # Legacy encoding prefixes altering meaning (0x66, 0xF2, 0xF3) may be # specified as high byte of (perhaps already including an # encoding space prefix). Other prefixes should be spelled out as usual # ahead of or, for segment overrides, with the memory # operand. # Operand order may not match that of the instruction actually being # expressed: While for a memory operand (of which there can be only one) it # is clear how to encode it in the resulting ModR/M byte, register operands # are encoded strictly in the order # - ModR/M.rm, ModR/M.reg for 2-operand insns, # - ModR/M.rm, {E,}VEX.vvvv, ModR/M.reg for 3-operand insns, and # - Imm{4,5}, ModR/M.rm, {E,}VEX.vvvv, ModR/M.reg for 4-operand insns, # obviously with the ModR/M.rm slot skipped when there is a memory operand, # and obviously with the ModR/M.reg slot skipped when there is an extension # opcode. (For Intel syntax of course all in the opposite order.) # Immediate operands (including immediate-like displacements, i.e. when not # part of ModR/M addressing) should be specified by separate .byte / .word / # .long / .quad (or alike) directives. # TBD: How to deal with this for RIP-relative addressing? # TBD: How to deal with this for 4-operand insns? # When register operand size varies for an actual insn (like e.g. for MOVZX or # VPMOVZX*), registers nevertheless need spelling out in a uniform manner, such # that any of them could be used to derive operand size attributes (e.g. # operand size prefix, REX.W, VEX.W, or VEX.L) as well as the EVEX Disp8 # scaling factor. # TBD: Could also go from largest operand size, albeit that may end up confusing # in AT&T mode, where memory operands don't have size, yet the memory # operand may have larger size than the register one(s) (and would hence be # the one which the attribute - see below - needs deriving from). # For VEX / XOP / EVEX is arranged like this: # {VEX,XOP,EVEX}[.][.][.][.] # where # - can be LIG, 128, 256, or (EVEX only) 512 as well as L0/L1 for # VEX / XOP and L0-L3 for EVEX, # - can be NP, 66, F3, or F2, # - can be # - 0f, 0f38, 0f3a, or M0...M31 for VEX, # - 08...3f (hex) for XOP, # - 0f, 0f38, 0f3a, or M0...M15 for EVEX, # - can be WIG, W0, or W1. # Omitted means "infer from operand size" if there is at least one # sized operand, or LIG otherwise. # Omitted means NP. # Omitted implies encoding is taken from . # Omitted means "infer from GPR operand size" if there is at least # one GPR operand, or WIG otherwise. # TBD: Is operand order being dependent on AT&T vs Intel syntax okay? .insn 0x90 # nop .insn 0xf390 # pause .insn rep 0x90 # pause .insn 0xd9c9 # fxch .insn 0xf30f01d9 # vmgexit .insn 0x89, %ecx, %eax # mov %ecx, %eax .insn 0x89, %ax, %cx # mov %ax, %cx .insn 0x8b, (%eax), %ecx # mov (%eax), %ecx .insn 0x0fc8+r, %edx # bswap %edx .insn lock 0x80/0, %fs:(%eax); .byte 1 # lock addb $1, %fs:(%eax) 1: .insn 0xe2; .byte 1b-.-1 # loop 1b .insn 0xc7f8; .long 1b-.-4 # xbegin 1b .insn 0x0fb6, %ax, %cx # movzx %al, %cx .insn 0x0fb7, %eax, %ecx # movzx %ax, %ecx .insn VEX.66.0F 0x58, %xmm0, %xmm1, %xmm2 # vaddpd %xmm0, %xmm1, %xmm2 .insn VEX.66 0x0f58, %ymm0, %ymm1, %ymm2 # vaddpd %ymm0, %ymm1, %ymm2 .insn VEX.LIG.F3.0F 0x58, %xmm0, %xmm1, %xmm2 # vaddss %xmm0, %xmm1, %xmm2 .insn VEX.66.0F3A.W0 0x68, %xmm0, %xmm1, (%edx), %xmm3 # vfmaddps %xmm0, %xmm1, (%edx), %xmm3 .insn VEX.66.0F3A.W1 0x68, %xmm0, %xmm1, (%edx), %xmm3 # vfmaddps %xmm0, %xmm1, %xmm3, (%edx) .insn VEX.66.0F3A.W1 0x68, %xmm0, %xmm1, %xmm2, (%ebx) # vfmaddps %xmm0, %xmm1, %xmm2, (%ebx) .insn VEX.66.0F3A.W0 0x48, $0, %xmm0, %xmm1, (%edx), %xmm3 # vpermil2ps $0, %xmm0, %xmm1, (%edx), %xmm3 .insn VEX.66.0F3A.W1 0x48, $1, %xmm0, %xmm1, (%edx), %xmm3 # vpermil2ps $1, %xmm0, %xmm1, %xmm3, (%edx) .insn VEX.66.0F3A.W1 0x48, $2, %xmm0, %xmm1, %xmm2, (%ebx) # vpermil2ps $2, %xmm0, %xmm1, %xmm2, (%ebx) .insn VEX.L0.0F.W0 0x93, %eax, %k0 # kmovw %eax, %k0 .insn VEX.256.0F.WIG 0x77 # vzeroall .insn EVEX.NP.0F.W0 0x58, {rn-sae}, %zmm0, %zmm1, %zmm2 # vaddps {rn-sae}, %zmm0, %zmm1, %zmm2 .insn EVEX.66.0F.W1 0x58, 8(%eax){1to8}, %zmm1, %zmm2{%k2}{z} # vaddpd 8(%eax){1to8}, %zmm0, %zmm1{%k2}{z} # TBD: How to specify the Disp8 scaling factor here? (In Intel syntax we can simply # use memory operand size.) .insn EVEX.66.0F38.W0 0x88, 4(%eax), %ymm1 # vexpandps 4(%eax), %ymm1