Re: [PATCH] [RISC-V] Optimize GP-relative addressing for linker.

[Jeff Law <jeffreyalaw@gmail.com>]

On 6/27/23 19:25, Palmer Dabbelt wrote:
> On Tue, 27 Jun 2023 08:43:42 PDT (-0700), kito.cheng@sifive.com wrote:
>> Testcase in your git commit has a base offset, but the testcase in the
>> code only contains a base with no offset?
>>
>> I am a little concerned about the case with an offset like "lui
>> a5,%hi(global_array+256) addi    a5,a5,%lo(global_array+256)" is still
>> right for this optimization?
> 
> Ya, I think there's probably a bug somewhere around there: maybe this, 
> or maybe reusing hi-parts, or something.  It's pretty close to the 
> release, so let's hold off on this one until we have time -- Nelson and 
> I are still trying to figure out this PC-relative GP SHN_ABS stuff...
My recollection from working in this space extensively on the PA is that 
when the highpart and lowpart have the same offset, you're always OK.

When the offsets differ, you have to worry about carries.  To deal with 
that HP defined "rounding" mode relocations.  Essentially they would 
round the component to an 8k boundary.

Then in the compiler we had code to rewrite the address to expose common 
bases to CSE:





>   For the PA, transform:
> 
>         memory(X + <large int>)
> 
>    into:
> 
>         if (<large int> & mask) >= 16
>           Y = (<large int> & ~mask) + mask + 1  Round up.
>         else
>           Y = (<large int> & ~mask)             Round down.
>         Z = X + Y
>         memory (Z + (<large int> - Y));
> 
>    This is for CSE to find several similar references, and only use one Z.
> 
>    X can either be a SYMBOL_REF or REG, but because combine cannot
>    perform a 4->2 combination we do nothing for SYMBOL_REF + D where
>    D will not fit in 14 bits.
> 
>    MODE_FLOAT references allow displacements which fit in 5 bits, so use
>    0x1f as the mask.
> 
>    MODE_INT references allow displacements which fit in 14 bits, so use
>    0x3fff as the mask.

I don't offhand remember where "16" above came from (it's been 25+ years 
since I wrote that code).  I kept wanting to think it came from the 
overlap between the bits set by the highpart instrution (21 bits) and 
the lowpart (14 bits).  But the math doesn't work and we do the same 
transformation for FP modes where we just have 5 bits of offset for the 
lowpart.  Hmmm.

The HP linker also had the ability to eliminate unnecessary highpart 
computations as well.  Though that was quite dicey as you had to do 
things like create bounds around jump tables which would inhibit the 
linker optimizer (jump tables were pure code and relied on each entry in 
the table being precisely 2 instructions).

This was all for static binaries.  PIC hadn't really taken hold at this 
point in the 90s.  Many of the concepts are probably still useful in the 
embedded world where static linking is still a common thing.

jeff