From: Sudakshina Das <Sudi.Das@arm.com>
To: "binutils@sourceware.org" <binutils@sourceware.org>
Cc: "nickc@redhat.com" <nickc@redhat.com>,
Richard Earnshaw <Richard.Earnshaw@arm.com>,
Ramana Radhakrishnan <Ramana.Radhakrishnan@arm.com>,
nd <nd@arm.com>
Subject: Re: [PATCH. BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions.
Date: Wed, 10 Apr 2019 09:36:00 -0000 [thread overview]
Message-ID: <7259c654-4843-b898-2370-e4ddb05043ba@arm.com> (raw)
In-Reply-To: <9b2a72a5-76d3-6dfd-7f47-a797e123bc29@arm.com>
Ping!
On 02/04/2019 17:09, Sudakshina Das wrote:
> Hi
>
> On 02/04/2019 17:06, Sudakshina Das wrote:
>> Hi
>>
>> This patch adds the new LDGM/STGM instructions of the
>> Armv8.5-A Memory Tagging Extension. This is part of the changes
>> that have been introduced recently in the 00bet10 release
>> https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools
>>
>>
>> The instructions are as follows:
>> LDGM Xt, [<Xn|SP>]
>> https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldgm-load-tag-multiple
>>
>>
>> STGM Xt, [<Xn|SP>]
>> https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/stgm-store-tag-multiple
>>
>>
>> For ease of review I have not added the regenerated files in the
>> patch. I will add those in my final commit.
>>
>> Builds and reg tests all pass on aarch64-none-elf.
>>
>> Is this ok for trunk? And for backport to 2.32?
>>
>> Thanks
>> Sudi
>>
>> *** gas/ChangeLog ***
>>
>> 2019-xx-xx Sudakshina Das <sudi.das@arm.com>
>>
>> * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm
>> and stgm.
>> * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
>> * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
>> * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
>>
>> *** opcodes/ChangeLog ***
>>
>> 2019-xx-xx Sudakshina Das <sudi.das@arm.com>
>>
>> * aarch64-asm-2.c: Regenerated.
>> * aarch64-dis-2.c: Likewise.
>> * aarch64-opc-2.c: Likewise.
>> * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
>
> Hi
>
> This patch updates the Store allocation tags instructions in
> Armv8.5-A Memory Tagging Extension. This is part of the changes
> that have been introduced recently in the 00bet10 release
> https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools
>
>
> All of these instructions have an updated register operand (Xt -> <Xt|SP>)
>
> - STG <Xt|SP>, [<Xn|SP>, #<simm>]
> - STG <Xt|SP>, [<Xn|SP>, #<simm>]!
> - STG <Xt|SP>, [<Xn|SP>], #<simm>
> - STZG <Xt|SP>, [<Xn|SP>, #<simm>]
> - STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
> - STZG <Xt|SP>, [<Xn|SP>], #<simm>
> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
> - ST2G <Xt|SP>, [<Xn|SP>], #<simm>
> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
> - STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
>
> https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order
>
>
> In order to accept <Rt|SP> a new operand type Rt_SP is introduced which
> has the same field as FLD_Rt but follows other semantics of Rn_SP.
>
> For ease of review I have not added the regenerated files in the patch.
> I will add those in my final commit.
>
> Builds and reg tests all pass on aarch64-none-elf.
>
> Is this ok for trunk? And for backport to 2.32?
>
> Thanks
> Sudi
>
> *** gas/ChangeLog ***
>
> 2019-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * config/tc-aarch64.c (process_omitted_operand): Add case for
> AARCH64_OPND_Rt_SP.
> (parse_operands): Likewise.
> * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
> * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
> * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
> * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
>
> *** include/ChangeLog ***
>
> 2019-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
>
> *** opcodes/ChangeLog ***
>
> 2019-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * aarch64-opc.c (aarch64_print_operand): Add case for
> AARCH64_OPND_Rt_SP.
> (verify_constraints): Likewise.
> * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
> (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
> to accept Rt|SP as first operand.
> (AARCH64_OPERANDS): Add new Rt_SP.
> * aarch64-asm-2.c: Regenerated.
> * aarch64-dis-2.c: Regenerated.
> * aarch64-opc-2.c: Regenerated.
next prev parent reply other threads:[~2019-04-10 9:36 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-02 16:06 [PATCH, BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction Sudakshina Das
2019-04-02 16:09 ` [PATCH. BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions Sudakshina Das
2019-04-10 9:36 ` Sudakshina Das [this message]
2019-04-10 16:02 ` Nick Clifton
2019-04-11 9:24 ` Sudakshina Das
2019-04-10 16:01 ` [PATCH, BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction Nick Clifton
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