From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: binutils@sourceware.org
Subject: [PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint
Date: Wed, 01 May 2019 17:43:00 -0000 [thread overview]
Message-ID: <737693dc-2e33-431d-e313-75aeb03c05a1@arm.com> (raw)
In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com>
[-- Attachment #1: Type: text/plain, Size: 663 bytes --]
Hi,
This patch adds support for MVE instructions VCVT and VRINT.
opcodes/ChangeLog:
2019-05-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
* arm-dis.c (enum mve_instructions): Add new instructions.
(enum mve_unpredictable): Add new reasons.
(enum mve_undefined): Likewise.
(is_mve_encoding_conflict): Handle new instructions.
(is_mve_undefined): Likewise.
(is_mve_unpredictable): Likewise.
(print_mve_undefined): Likewise.
(print_mve_unpredictable): Likewise.
(print_mve_rounding_mode): Likewise.
(print_mve_vcvt_size): Likewise.
(print_mve_size): Likewise.
(print_insn_mve): Likewise.
[-- Attachment #2: 44.patch --]
[-- Type: text/x-patch, Size: 11836 bytes --]
diff --git a/gas/testsuite/gas/arm/mve-vrint-bad.l b/gas/testsuite/gas/arm/mve-vrint-bad.l
index 1d68a82badabae2a56559f476b356fdec9713c48..39fca355f6be2f7b8650867d20d590a4a992a18c 100644
--- a/gas/testsuite/gas/arm/mve-vrint-bad.l
+++ b/gas/testsuite/gas/arm/mve-vrint-bad.l
@@ -11,7 +11,7 @@
[^:]*:13: Error: bad type in SIMD instruction -- `vrintm.f64 q0,q1'
[^:]*:13: Error: bad type in SIMD instruction -- `vrintp.i16 q0,q1'
[^:]*:13: Error: bad type in SIMD instruction -- `vrintp.f64 q0,q1'
-[^:]*:14: Error: invalid rounding mode -- `vrintr.f16 q0,q1'
+[^:]*:14: Error: VFP single, double or Neon quad precision register expected -- `vrintr.f16 q0,q1'
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index e10a5d7bba690f0749885e7839ee1772f0b44e09..c20a175f67a61532a692d185b5afd92ed9fe6563 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -124,6 +124,11 @@ enum mve_instructions
MVE_VSTRD_SCATTER_T4,
MVE_VSTRW_SCATTER_T5,
MVE_VSTRD_SCATTER_T6,
+ MVE_VCVT_FP_FIX_VEC,
+ MVE_VCVT_BETWEEN_FP_INT,
+ MVE_VCVT_FP_HALF_FP,
+ MVE_VCVT_FROM_FP_TO_INT,
+ MVE_VRINT_FP,
MVE_NONE
};
@@ -145,12 +150,14 @@ enum mve_unpredictable
UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
equal. */
UNPRED_OS, /* Unpredictable because offset scaled == 1. */
+ UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
+ same. */
UNPRED_NONE /* No unpredictable behavior. */
};
enum mve_undefined
{
- UNDEF_SIZE_3, /* undefined because size == 3. */
+ UNDEF_SIZE_0, /* undefined because size == 0. */
UNDEF_SIZE_3, /* undefined because size == 3. */
UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
@@ -160,6 +167,8 @@ enum mve_undefined
UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
size == 1. */
UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
+ UNDEF_VCVT_IMM6, /* imm6 < 32. */
+ UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
UNDEF_NONE /* no undefined behavior. */
};
@@ -1868,7 +1877,9 @@ static const struct opcode32 neon_opcodes[] =
%d print addr mode of MVE vldr[bhw] and vstr[bhw]
%u print 'U' (unsigned) or 'S' for various mve instructions
%i print MVE predicate(s) for vpt and vpst
+ %m print rounding mode for vcvt and vrint
%n print vector comparison code for predicated instruction
+ %s print size for various vcvt instructions
%v print vector predicate for instruction in predicated
block
%o print offset scaled for vldr[hwd] and vstr[hwd]
@@ -1882,7 +1893,8 @@ static const struct opcode32 neon_opcodes[] =
UNPREDICTABLE
%<bitfield>s print size for vector predicate & non VMOV instructions
%<bitfield>i print immediate for vstr/vldr reg +/- imm
- */
+ %<bitfield>k print immediate for vector conversion instruction
+ */
static const struct mopcode32 mve_opcodes[] =
{
@@ -2051,6 +2063,36 @@ static const struct mopcode32 mve_opcodes[] =
0xef000140, 0xef811f51,
"vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+ /* Vector VCVT. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VCVT_FP_FIX_VEC,
+ 0xef800c50, 0xef801cd1,
+ "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
+
+ /* Vector VCVT. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VCVT_BETWEEN_FP_INT,
+ 0xffb30640, 0xffb31e51,
+ "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VCVT between single and half-precision float, bottom half. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VCVT_FP_HALF_FP,
+ 0xee3f0e01, 0xefbf1fd1,
+ "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VCVT between single and half-precision float, top half. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VCVT_FP_HALF_FP,
+ 0xee3f1e01, 0xefbf1fd1,
+ "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
+
+ /* Vector VCVT. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VCVT_FROM_FP_TO_INT,
+ 0xffb30040, 0xffb31c51,
+ "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
+
/* Vector VLD2. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VLD2,
@@ -2129,6 +2171,12 @@ static const struct mopcode32 mve_opcodes[] =
0xec101f00, 0xfe101f80,
"vldrw%v.u32\t%13-15,22Q, %d"},
+ /* Vector VRINT floating point. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VRINT_FP,
+ 0xffb20440, 0xffb31c51,
+ "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
+
/* Vector VST2 no writeback. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VST2,
@@ -4269,6 +4317,9 @@ is_mve_encoding_conflict (unsigned long given,
else
return FALSE;
+ case MVE_VCVT_FP_FIX_VEC:
+ return (arm_decode_field (given, 16, 21) & 0x38) == 0;
+
default:
return FALSE;
@@ -4524,6 +4575,43 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
else
return FALSE;
+ case MVE_VCVT_FP_FIX_VEC:
+ {
+ unsigned long imm6 = arm_decode_field (given, 16, 21);
+ if ((imm6 & 0x20) == 0)
+ {
+ *undefined_code = UNDEF_VCVT_IMM6;
+ return TRUE;
+ }
+
+ if ((arm_decode_field (given, 9, 9) == 0)
+ && ((imm6 & 0x30) == 2))
+ {
+ *undefined_code = UNDEF_VCVT_FSI_IMM6;
+ return TRUE;
+ }
+
+ return FALSE;
+ }
+
+ case MVE_VCVT_BETWEEN_FP_INT:
+ case MVE_VCVT_FROM_FP_TO_INT:
+ {
+ unsigned long size = arm_decode_field (given, 18, 19);
+ if (size == 0)
+ {
+ *undefined_code = UNDEF_SIZE_0;
+ return TRUE;
+ }
+ else if (size == 3)
+ {
+ *undefined_code = UNDEF_SIZE_3;
+ return TRUE;
+ }
+ else
+ return FALSE;
+ }
+
default:
return FALSE;
}
@@ -4749,6 +4837,31 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
else
return FALSE;
+ case MVE_VCVT_BETWEEN_FP_INT:
+ case MVE_VCVT_FROM_FP_TO_INT:
+ {
+ unsigned long rt = arm_decode_field (given, 0, 3);
+ unsigned long rt2 = arm_decode_field (given, 16, 19);
+
+ if ((rt == 0xd) || (rt2 == 0xd))
+ {
+ *unpredictable_code = UNPRED_R13;
+ return TRUE;
+ }
+ else if ((rt == 0xf) || (rt2 == 0xf))
+ {
+ *unpredictable_code = UNPRED_R15;
+ return TRUE;
+ }
+ else if (rt == rt2)
+ {
+ *unpredictable_code = UNPRED_GP_REGS_EQUAL;
+ return TRUE;
+ }
+
+ return FALSE;
+ }
+
default:
return FALSE;
}
@@ -4797,6 +4910,14 @@ print_mve_undefined (struct disassemble_info *info,
func (stream, "not unsigned");
break;
+ case UNDEF_VCVT_IMM6:
+ func (stream, "invalid imm6");
+ break;
+
+ case UNDEF_VCVT_FSI_IMM6:
+ func (stream, "fsi = 0 and invalid imm6");
+ break;
+
case UNDEF_NONE:
break;
}
@@ -4851,6 +4972,10 @@ print_mve_unpredictable (struct disassemble_info *info,
func (stream, "use of offset scaled");
break;
+ case UNPRED_GP_REGS_EQUAL:
+ func (stream, "same general-purpose register used for both operands");
+ break;
+
case UNPRED_NONE:
break;
}
@@ -4894,6 +5019,234 @@ print_mve_register_blocks (struct disassemble_info *info,
}
}
+static void
+print_mve_rounding_mode (struct disassemble_info *info,
+ unsigned long given,
+ enum mve_instructions matched_insn)
+{
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+
+ switch (matched_insn)
+ {
+ case MVE_VCVT_FROM_FP_TO_INT:
+ {
+ switch (arm_decode_field (given, 8, 9))
+ {
+ case 0:
+ func (stream, "a");
+ break;
+
+ case 1:
+ func (stream, "n");
+ break;
+
+ case 2:
+ func (stream, "p");
+ break;
+
+ case 3:
+ func (stream, "m");
+ break;
+
+ default:
+ break;
+ }
+ }
+ break;
+
+ case MVE_VRINT_FP:
+ {
+ switch (arm_decode_field (given, 7, 9))
+ {
+ case 0:
+ func (stream, "n");
+ break;
+
+ case 1:
+ func (stream, "x");
+ break;
+
+ case 2:
+ func (stream, "a");
+ break;
+
+ case 3:
+ func (stream, "z");
+ break;
+
+ case 5:
+ func (stream, "m");
+ break;
+
+ case 7:
+ func (stream, "p");
+
+ case 4:
+ case 6:
+ default:
+ break;
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+static void
+print_mve_vcvt_size (struct disassemble_info *info,
+ unsigned long given,
+ enum mve_instructions matched_insn)
+{
+ unsigned long mode = 0;
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+
+ switch (matched_insn)
+ {
+ case MVE_VCVT_FP_FIX_VEC:
+ {
+ mode = (((given & 0x200) >> 7)
+ | ((given & 0x10000000) >> 27)
+ | ((given & 0x100) >> 8));
+
+ switch (mode)
+ {
+ case 0:
+ func (stream, "f16.s16");
+ break;
+
+ case 1:
+ func (stream, "s16.f16");
+ break;
+
+ case 2:
+ func (stream, "f16.u16");
+ break;
+
+ case 3:
+ func (stream, "u16.f16");
+ break;
+
+ case 4:
+ func (stream, "f32.s32");
+ break;
+
+ case 5:
+ func (stream, "s32.f32");
+ break;
+
+ case 6:
+ func (stream, "f32.u32");
+ break;
+
+ case 7:
+ func (stream, "u32.f32");
+ break;
+
+ default:
+ break;
+ }
+ break;
+ }
+ case MVE_VCVT_BETWEEN_FP_INT:
+ {
+ unsigned long size = arm_decode_field (given, 18, 19);
+ unsigned long op = arm_decode_field (given, 7, 8);
+
+ if (size == 1)
+ {
+ switch (op)
+ {
+ case 0:
+ func (stream, "f16.s16");
+ break;
+
+ case 1:
+ func (stream, "f16.u16");
+ break;
+
+ case 2:
+ func (stream, "s16.f16");
+ break;
+
+ case 3:
+ func (stream, "u16.f16");
+ break;
+
+ default:
+ break;
+ }
+ }
+ else if (size == 2)
+ {
+ switch (op)
+ {
+ case 0:
+ func (stream, "f32.s32");
+ break;
+
+ case 1:
+ func (stream, "f32.u32");
+ break;
+
+ case 2:
+ func (stream, "s32.f32");
+ break;
+
+ case 3:
+ func (stream, "u32.f32");
+ break;
+ }
+ }
+ }
+ break;
+
+ case MVE_VCVT_FP_HALF_FP:
+ {
+ unsigned long op = arm_decode_field (given, 28, 28);
+ if (op == 0)
+ func (stream, "f16.f32");
+ else if (op == 1)
+ func (stream, "f32.f16");
+ }
+ break;
+
+ case MVE_VCVT_FROM_FP_TO_INT:
+ {
+ unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
+
+ switch (size)
+ {
+ case 2:
+ func (stream, "s16.f16");
+ break;
+
+ case 3:
+ func (stream, "u16.f16");
+ break;
+
+ case 4:
+ func (stream, "s32.f32");
+ break;
+
+ case 5:
+ func (stream, "u32.f32");
+ break;
+
+ default:
+ break;
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
static void
print_instruction_predicate (struct disassemble_info *info)
{
@@ -4941,6 +5294,7 @@ print_mve_size (struct disassemble_info *info,
case MVE_VPT_VEC_T5:
case MVE_VPT_VEC_T6:
case MVE_VRHADD:
+ case MVE_VRINT_FP:
case MVE_VST2:
case MVE_VST4:
case MVE_VSTRB_SCATTER_T1:
@@ -6466,6 +6820,14 @@ print_insn_mve (struct disassemble_info *info, long given)
}
break;
+ case 'm':
+ print_mve_rounding_mode (info, given, insn->mve_op);
+ break;
+
+ case 's':
+ print_mve_vcvt_size (info, given, insn->mve_op);
+ break;
+
case 'u':
{
if (arm_decode_field (given, 28, 28) == 0)
@@ -6535,6 +6897,9 @@ print_insn_mve (struct disassemble_info *info, long given)
func (stream, "%lu", mod_imm);
}
break;
+ case 'k':
+ func (stream, "%lu", 64 - value);
+ break;
case 'r':
func (stream, "%s", arm_regnames[value]);
break;
next prev parent reply other threads:[~2019-05-01 17:43 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-01 16:51 [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 16:53 ` [PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp Andre Vieira (lists)
2019-05-01 16:55 ` [PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub and vabd Andre Vieira (lists)
2019-05-02 10:56 ` Nick Clifton
2019-05-13 13:42 ` Andre Vieira (lists)
[not found] ` <98e50dc4-7b0e-d727-0c20-34711be86533@redhat.com>
[not found] ` <4e56a5f3-bcde-f4cd-21d4-35cc3f11b5e8@arm.com>
2019-05-14 16:53 ` Nick Clifton
2019-05-14 16:54 ` Nick Clifton
2019-05-01 16:56 ` [PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg Andre Vieira (lists)
2019-05-01 16:57 ` [PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav Andre Vieira (lists)
2019-05-01 16:59 ` [PATCH 5/57][Arm][GAS] Add support for MVE instructions: vmull{b,t} Andre Vieira (lists)
2019-05-01 17:00 ` [PATCH 6/57][Arm][GAS] Add support for MVE instructions: vst/vld{2,4} Andre Vieira (lists)
2019-05-01 17:01 ` [PATCH 7/57][Arm][GAS] Add support for MVE instructions: vstr/vldr Andre Vieira (lists)
2019-05-01 17:02 ` [PATCH 8/57][Arm][GAS] Add support for MVE instructions: vcvt Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 9/57][Arm][GAS] Add support for MVE instructions: vmov Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 10/57][Arm][GAS] Add support for MVE instructions: vcmp and vpt Andre Vieira (lists)
2019-05-01 17:05 ` [PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsr Andre Vieira (lists)
2019-05-01 17:06 ` [PATCH 12/57][Arm][GAS] Add support for MVE instructions: vaddlv and vaddv Andre Vieira (lists)
2019-05-01 17:07 ` [PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor Andre Vieira (lists)
2019-05-01 17:08 ` [PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul Andre Vieira (lists)
2019-05-01 17:09 ` [PATCH 16/57][Arm][GAS] Add support for MVE instructions: vdup, vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:09 ` [PATCH 15/57][Arm][GAS] Add support for MVE instructions: vcls, vclz and vfmas Andre Vieira (lists)
2019-05-01 17:11 ` [PATCH 17/57][Arm][GAS] Add support for MVE instructions: vfma and vfms Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 18/57][Arm][GAS] Add support for MVE instructions: vhcadd, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 19/57][Arm][GAS] Add support for MVE instructions: vmax[nm][a] and vmin[nm][a] Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 20/57][Arm][GAS] Add support for MVE instructions: vmaxnmv, vmaxnmav, vminnmv and vminnmav Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 21/57][Arm][GAS] Add support for MVE instructions: vmaxv, vmaxav, vminv and vminav Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav, vrmlaldavh, vrmlalvh and vrmlsldavh Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 23/57][Arm][GAS] Add support for MVE instructions: vmla, vmul, vqadd and vqsub Andre Vieira (lists)
2019-05-01 17:16 ` [PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 26/57][Arm][GAS] Add support for MVE instructions: vpnot and vpsel Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 25/57][Arm][GAS] Add support for MVE instruction: vmvn, vqabs and vqneg Andre Vieira (lists)
2019-05-01 17:18 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:19 ` [PATCH 28/57][Arm][GAS] Add support for MVE instructions: vqdmlah, vqrdmlah, vqdmlash, vqrdmlash, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:30 ` [PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmlsdh and vqrdmlsdh Andre Vieira (lists)
2019-05-01 17:31 ` [PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb] Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, vqmovunt, vqmovunb, vqrshl and vrshl Andre Vieira (lists)
2019-05-01 17:33 ` [PATCH 32/57][Arm][GAS] Add support for MVE instructions: vrintn, vrintx, vrinta, vrintz, vrintm and vrintp Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 34/57][Arm][GAS] Add support for MVE instructions: vshl and vqshl Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 33/57][Arm][GAS] Add support for MVE instructions: vshr, vrshr, vsli, vsri, vrev16, vrev32 and vrev64 Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 35/57][Arm][GAS] Add support for MVE instructions: vshlc and vshll Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 36/57][Arm][GAS] Add support for MVE instructions: wlstp, dlstp, letp and lctp Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 37/57][Arm][OBJDUMP] Add framework for MVE instructions Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 38/57][Arm][OBJDUMP] Disable the use of MVE reserved coproc numbers in coprocessor instructions Andre Vieira (lists)
2019-05-01 17:39 ` [PATCH 39/57][Arm][OBJDUMP] Add support for MVE instructions: vpt, vpst and vcmp Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 40/57][Arm][OBJDUMP] Add support for MVE instructions: vdup, veor, vfma, vfms, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 41/57][Arm][OBJDUMP] Add support for MVE instructions: vld[24] and vst[24] Andre Vieira (lists)
2019-05-01 17:41 ` [PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and vstr[bhw] Andre Vieira (lists)
2019-05-01 17:42 ` [PATCH 43/57][Arm][OBJDUMP] Add support for MVE instructions: scatter stores and gather loads Andre Vieira (lists)
2019-05-01 17:43 ` Andre Vieira (lists) [this message]
2019-05-02 9:54 ` [PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint Nick Clifton
2019-05-13 13:38 ` Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 46/57][Arm][OBJDUMP] Add support for MVE instructions: vmovl, vmull, vqdmull, vqmovn, vqmovun and vmovn Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 45/57][Arm][OBJDUMP] Add support for MVE instructions: vmov, vmvn, vorr, vorn, vmovx and vbic Andre Vieira (lists)
2019-05-01 17:45 ` [PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmladav, vmlas, vrmlsldavh, vmlsldav, vmlsdav, vrmlaldavh, vqdmlah, vqrdmlash, vqrdmlash, vqdmlsdh, vqrdmlsdh, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 49/57][Arm][OBJDUMP] Add support for MVE complex number instructions Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 48/57][Arm][OBJDUMP] Add support for MVE instructions: vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:47 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 52/57][Arm][OBJDUMP] Add support for MVE instructions: vadc, vabav, vabd, vabs, vadd, vsbc and vsub Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp Andre Vieira (lists)
2019-05-01 17:49 ` [PATCH 53/57][Arm][OBJDUMP] Add support for MVE instructions: vand, vbrsr, vcls, vclz and vctp Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 54/57][Arm][OBJDUMP] Add support for MVE instructions: vmax(a), vmax(a)v, vmaxnm(a), vmaxnm(a)v, vmin(a), vmin(a)v, vminnm(a), vminnm(a)v and vmla Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 55/57][Arm][OBJDUMP] Add support for MVE instructions: vmul, vmulh, vrmulh and vneg Andre Vieira (lists)
2019-05-01 17:51 ` [PATCH 56/57][Arm][OBJDUMP] Add support for MVE instructions: vpnot, vpsel, vqabs, vqadd, vqsub, vqneg and vrev Andre Vieira (lists)
2019-05-01 18:23 ` [PATCH 57/57][Arm][GAS] MVE Tests Andre Vieira (lists)
2019-05-01 18:24 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-02 10:03 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
2019-05-02 10:18 ` Nick Clifton
2019-05-13 13:39 ` [PATCH, binutils, Arm] Add Armv8.1-M Mainline and MVE enablement to NEWS Andre Vieira (lists)
2019-05-02 13:39 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
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