Hi,

=== Context ===

This patch is part of a patch series to add support for Armv8.1-M
Mainline architecture. Its purpose is to add support for the new
VLDR (system register) and VSTR (system register) instructions.

=== Patch description ===

GNU as' Arm backend assumes each mnemonic has a single entry in the
instruction table but VLDR (system register) and VSTR (system register)
are different instructions than VLDR and VSTR. It is thus necessary to
add some form of demultiplexing in the parser. It starts by creating a
new operand type OP_VLDR which indicate that the operand is either the
existing OP_RVSD operand or a system register. The function
parse_operands () then tries these two cases in order, calling the new
parse_sys_vldr_vstr for the second case.

Since the encoding function is specified in the instruction table entry,
it also need to have some sort of demultiplexing. This is done in
do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls
the new do_t_vldr_vstr_sysreg ().

A new internal relocation is needed as well since the offset has a
shorter range than in other Thumb coprocessor instructions. Disassembly
also requires special care since VSTR (system register) reuse the STC
encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual
states that coprocessor 8, 14 and 15 are reserved for floating-point and
MVE instructions a feature bit check is added if the coprocessor number
is one of this value and we are trying to match a coprocessor
instruction (eg. STC) to forbid the match.

ChangeLog entries are as follows:

*** bfd/ChangeLog ***

2019-04-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal
	relocation.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.

*** gas/ChangeLog ***

2019-04-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* config/tc-arm.c (parse_sys_vldr_vstr): New function.
	(OP_VLDR): New enum operand_parse_code enumerator.
	(parse_operands): Add logic for OP_VLDR.
	(do_t_vldr_vstr_sysreg): New function.
	(do_vldr_vstr): Likewise.
	(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
	(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
	Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
	* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
	uses of VLDR and VSTR.
	* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
	above bad uses.
	* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
	VSTR valid uses.
	* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
	above examples.

*** opcodes/ChangeLog ***

2019-04-04  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
	specifier.  Add entries for VLDR and VSTR of system registers.
	(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
	coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
	of %J and %K format specifier.