From: Jan Beulich <jbeulich@suse.com>
To: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Jingtao Cai <caijingtao@huawei.com>, Bo Dong <dongbo4@huawei.com>,
binutils@sourceware.org
Subject: Re: [PATCH RESEND v2] Aarch64: Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}
Date: Mon, 21 Feb 2022 14:13:27 +0100 [thread overview]
Message-ID: <7435dbfd-5b5d-60d0-7376-83c209c77541@suse.com> (raw)
In-Reply-To: <20220216005311.26184-1-zhangshaokun@hisilicon.com>
On 16.02.2022 01:53, Shaokun Zhang wrote:
> --- a/gas/testsuite/gas/aarch64/sve-movprfx_23.d
> +++ b/gas/testsuite/gas/aarch64/sve-movprfx_23.d
> @@ -9,29 +9,29 @@ Disassembly of section .*:
>
> 0+ <.*>:
> [^:]+: 04512461 movprfx z1.h, p1/m, z3.h
> -[^:]+: 256c8021 incp z1.h, p1 // note: merging predicate expected due to preceding `movprfx' at operand 2
> +[^:]+: 256c8021 incp z1.h, p1.h // note: merging predicate expected due to preceding `movprfx' at operand 2
I have a more general question here: Couldn't the spec make optional the
use of all the same size specifiers when there are multiple, same element
size operands? One such suffix of course needs to be there to disambiguate
different element size forms of the same insn, but the redundancy merely
adds clutter imo.
Jan
next prev parent reply other threads:[~2022-02-21 13:13 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-16 0:53 Shaokun Zhang
2022-02-21 13:13 ` Jan Beulich [this message]
2022-03-02 7:36 ` Shaokun Zhang
2022-03-10 9:38 ` Shaokun Zhang
2022-03-10 10:38 ` Jan Beulich
2022-03-10 11:33 ` Shaokun Zhang
2022-03-10 11:50 ` Jan Beulich
2022-03-10 12:24 ` Shaokun Zhang
2022-03-10 12:27 ` Shaokun Zhang
2022-09-12 8:17 ` Richard Sandiford
2022-09-12 8:27 ` Jan Beulich
2022-09-12 9:38 ` Richard Sandiford
2022-09-28 2:19 ` dongbo (E)
2022-09-30 14:54 ` Richard Sandiford
2022-10-09 1:31 ` dongbo (E)
2022-10-10 10:25 ` Richard Sandiford
2022-10-11 2:19 ` dongbo (E)
2022-10-17 9:33 ` Richard Sandiford
2022-10-18 5:57 ` dongbo (E)
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