From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 7EBC3396DC35 for ; Thu, 2 Jun 2022 14:06:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7EBC3396DC35 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id AB2D8300089; Thu, 2 Jun 2022 14:06:26 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Weiwei Li , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org Subject: [PATCH 2/9] RISC-V: Refactor Zfh/Zhinx-related constants Date: Thu, 2 Jun 2022 23:05:59 +0900 Message-Id: <75dbb66aa626b036da599022173c16aff8f2e11b.1654178756.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Jun 2022 14:06:30 -0000 This commit just moves Zfh/Zhinx-related constants for better integration with other instructions, macros and constants. gas/ChangeLog: * config/tc-riscv.c (macro): Move M_FLH and M_FSH handlings. include/ChangeLog: * opcode/riscv.h (M_FLH, M_FSH): Move around. * opcode/riscv-opc.h (MATCH_FADD_H, MASK_FADD_H, MATCH_FSUB_H, MASK_FSUB_H, MATCH_FMUL_H, MASK_FMUL_H, MATCH_FDIV_H, MASK_FDIV_H, MATCH_FSGNJ_H, MASK_FSGNJ_H, MATCH_FSGNJN_H, MASK_FSGNJN_H, MATCH_FSGNJX_H, MASK_FSGNJX_H, MATCH_FMIN_H, MASK_FMIN_H, MATCH_FMAX_H, MASK_FMAX_H, MATCH_FCVT_H_S, MASK_FCVT_H_S, MATCH_FCVT_S_H, MASK_FCVT_S_H, MATCH_FCVT_H_D, MASK_FCVT_H_D, MATCH_FCVT_D_H, MASK_FCVT_D_H, MATCH_FCVT_H_Q, MASK_FCVT_H_Q, MATCH_FCVT_Q_H, MASK_FCVT_Q_H, MATCH_FSQRT_H, MASK_FSQRT_H, MATCH_FLE_H, MASK_FLE_H, MATCH_FLT_H, MASK_FLT_H, MATCH_FEQ_H, MASK_FEQ_H, MATCH_FCVT_W_H, MASK_FCVT_W_H, MATCH_FCVT_WU_H, MASK_FCVT_WU_H, MATCH_FCVT_L_H, MASK_FCVT_L_H, MATCH_FCVT_LU_H, MASK_FCVT_LU_H, MATCH_FMV_X_H, MASK_FMV_X_H, MATCH_FCLASS_H, MASK_FCLASS_H, MATCH_FCVT_H_W, MASK_FCVT_H_W, MATCH_FCVT_H_WU, MASK_FCVT_H_WU, MATCH_FCVT_H_L, MASK_FCVT_H_L, MATCH_FCVT_H_LU, MASK_FCVT_H_LU, MATCH_FMV_H_X, MASK_FMV_H_X, MATCH_FLH, MASK_FLH, MATCH_FSH, MASK_FSH, MATCH_FMADD_H, MASK_FMADD_H, MATCH_FMSUB_H, MASK_FMSUB_H, MATCH_FNMSUB_H, MASK_FNMSUB_H, MATCH_FNMADD_H, MASK_FNMADD_H): Move around for better integration with other instructions. --- gas/config/tc-riscv.c | 19 ++--- include/opcode/riscv-opc.h | 144 ++++++++++++++++++------------------- include/opcode/riscv.h | 4 +- 3 files changed, 84 insertions(+), 83 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 1b730b4be36..61cf383a9fb 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1843,6 +1843,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); break; + case M_FLH: + pcrel_load (rd, rs1, imm_expr, "flh", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + case M_FLW: pcrel_load (rd, rs1, imm_expr, "flw", BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); @@ -1873,6 +1878,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); break; + case M_FSH: + pcrel_store (rs2, rs1, imm_expr, "fsh", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); + break; + case M_FSW: pcrel_store (rs2, rs1, imm_expr, "fsw", BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); @@ -1908,15 +1918,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, vector_macro (ip); break; - case M_FLH: - pcrel_load (rd, rs1, imm_expr, "flh", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); - break; - case M_FSH: - pcrel_store (rs2, rs1, imm_expr, "fsh", - BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); - break; - default: as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name); break; diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 2e867965e12..80e0b44a096 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -267,6 +267,38 @@ #define MASK_CSRRSI 0x707f #define MATCH_CSRRCI 0x7073 #define MASK_CSRRCI 0x707f +#define MATCH_FADD_H 0x4000053 +#define MASK_FADD_H 0xfe00007f +#define MATCH_FSUB_H 0xc000053 +#define MASK_FSUB_H 0xfe00007f +#define MATCH_FMUL_H 0x14000053 +#define MASK_FMUL_H 0xfe00007f +#define MATCH_FDIV_H 0x1c000053 +#define MASK_FDIV_H 0xfe00007f +#define MATCH_FSGNJ_H 0x24000053 +#define MASK_FSGNJ_H 0xfe00707f +#define MATCH_FSGNJN_H 0x24001053 +#define MASK_FSGNJN_H 0xfe00707f +#define MATCH_FSGNJX_H 0x24002053 +#define MASK_FSGNJX_H 0xfe00707f +#define MATCH_FMIN_H 0x2c000053 +#define MASK_FMIN_H 0xfe00707f +#define MATCH_FMAX_H 0x2c001053 +#define MASK_FMAX_H 0xfe00707f +#define MATCH_FCVT_H_S 0x44000053 +#define MASK_FCVT_H_S 0xfff0007f +#define MATCH_FCVT_S_H 0x40200053 +#define MASK_FCVT_S_H 0xfff0007f +#define MATCH_FCVT_H_D 0x44100053 +#define MASK_FCVT_H_D 0xfff0007f +#define MATCH_FCVT_D_H 0x42200053 +#define MASK_FCVT_D_H 0xfff0007f +#define MATCH_FCVT_H_Q 0x44300053 +#define MASK_FCVT_H_Q 0xfff0007f +#define MATCH_FCVT_Q_H 0x46200053 +#define MASK_FCVT_Q_H 0xfff0007f +#define MATCH_FSQRT_H 0x5c000053 +#define MASK_FSQRT_H 0xfff0007f #define MATCH_FADD_S 0x53 #define MASK_FADD_S 0xfe00007f #define MATCH_FSUB_S 0x8000053 @@ -339,6 +371,12 @@ #define MASK_FCVT_Q_D 0xfff0007f #define MATCH_FSQRT_Q 0x5e000053 #define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_H 0xa4000053 +#define MASK_FLE_H 0xfe00707f +#define MATCH_FLT_H 0xa4001053 +#define MASK_FLT_H 0xfe00707f +#define MATCH_FEQ_H 0xa4002053 +#define MASK_FEQ_H 0xfe00707f #define MATCH_FLE_S 0xa0000053 #define MASK_FLE_S 0xfe00707f #define MATCH_FLT_S 0xa0001053 @@ -357,6 +395,18 @@ #define MASK_FLT_Q 0xfe00707f #define MATCH_FEQ_Q 0xa6002053 #define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_H 0xc4000053 +#define MASK_FCVT_W_H 0xfff0007f +#define MATCH_FCVT_WU_H 0xc4100053 +#define MASK_FCVT_WU_H 0xfff0007f +#define MATCH_FCVT_L_H 0xc4200053 +#define MASK_FCVT_L_H 0xfff0007f +#define MATCH_FCVT_LU_H 0xc4300053 +#define MASK_FCVT_LU_H 0xfff0007f +#define MATCH_FMV_X_H 0xe4000053 +#define MASK_FMV_X_H 0xfff0707f +#define MATCH_FCLASS_H 0xe4001053 +#define MASK_FCLASS_H 0xfff0707f #define MATCH_FCVT_W_S 0xc0000053 #define MASK_FCVT_W_S 0xfff0007f #define MATCH_FCVT_WU_S 0xc0100053 @@ -391,6 +441,16 @@ #define MASK_FCVT_LU_Q 0xfff0007f #define MATCH_FCLASS_Q 0xe6001053 #define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_H_W 0xd4000053 +#define MASK_FCVT_H_W 0xfff0007f +#define MATCH_FCVT_H_WU 0xd4100053 +#define MASK_FCVT_H_WU 0xfff0007f +#define MATCH_FCVT_H_L 0xd4200053 +#define MASK_FCVT_H_L 0xfff0007f +#define MATCH_FCVT_H_LU 0xd4300053 +#define MASK_FCVT_H_LU 0xfff0007f +#define MATCH_FMV_H_X 0xf4000053 +#define MASK_FMV_H_X 0xfff0707f #define MATCH_FCVT_S_W 0xd0000053 #define MASK_FCVT_S_W 0xfff0007f #define MATCH_FCVT_S_WU 0xd0100053 @@ -517,18 +577,30 @@ #define MASK_BINV 0xfe00707f #define MATCH_BEXT 0x48005033 #define MASK_BEXT 0xfe00707f +#define MATCH_FLH 0x1007 +#define MASK_FLH 0x707f #define MATCH_FLW 0x2007 #define MASK_FLW 0x707f #define MATCH_FLD 0x3007 #define MASK_FLD 0x707f #define MATCH_FLQ 0x4007 #define MASK_FLQ 0x707f +#define MATCH_FSH 0x1027 +#define MASK_FSH 0x707f #define MATCH_FSW 0x2027 #define MASK_FSW 0x707f #define MATCH_FSD 0x3027 #define MASK_FSD 0x707f #define MATCH_FSQ 0x4027 #define MASK_FSQ 0x707f +#define MATCH_FMADD_H 0x4000043 +#define MASK_FMADD_H 0x600007f +#define MATCH_FMSUB_H 0x4000047 +#define MASK_FMSUB_H 0x600007f +#define MATCH_FNMSUB_H 0x400004b +#define MASK_FNMSUB_H 0x600007f +#define MATCH_FNMADD_H 0x400004f +#define MASK_FNMADD_H 0x600007f #define MATCH_FMADD_S 0x43 #define MASK_FMADD_S 0x600007f #define MATCH_FMSUB_S 0x47 @@ -701,78 +773,6 @@ #define MASK_AES64DSM 0xfe00707f #define MATCH_AES64DS 0x3a000033 #define MASK_AES64DS 0xfe00707f -#define MATCH_FADD_H 0x4000053 -#define MASK_FADD_H 0xfe00007f -#define MATCH_FSUB_H 0xc000053 -#define MASK_FSUB_H 0xfe00007f -#define MATCH_FMUL_H 0x14000053 -#define MASK_FMUL_H 0xfe00007f -#define MATCH_FDIV_H 0x1c000053 -#define MASK_FDIV_H 0xfe00007f -#define MATCH_FSGNJ_H 0x24000053 -#define MASK_FSGNJ_H 0xfe00707f -#define MATCH_FSGNJN_H 0x24001053 -#define MASK_FSGNJN_H 0xfe00707f -#define MATCH_FSGNJX_H 0x24002053 -#define MASK_FSGNJX_H 0xfe00707f -#define MATCH_FMIN_H 0x2c000053 -#define MASK_FMIN_H 0xfe00707f -#define MATCH_FMAX_H 0x2c001053 -#define MASK_FMAX_H 0xfe00707f -#define MATCH_FCVT_H_S 0x44000053 -#define MASK_FCVT_H_S 0xfff0007f -#define MATCH_FCVT_S_H 0x40200053 -#define MASK_FCVT_S_H 0xfff0007f -#define MATCH_FSQRT_H 0x5c000053 -#define MASK_FSQRT_H 0xfff0007f -#define MATCH_FLE_H 0xa4000053 -#define MASK_FLE_H 0xfe00707f -#define MATCH_FLT_H 0xa4001053 -#define MASK_FLT_H 0xfe00707f -#define MATCH_FEQ_H 0xa4002053 -#define MASK_FEQ_H 0xfe00707f -#define MATCH_FCVT_W_H 0xc4000053 -#define MASK_FCVT_W_H 0xfff0007f -#define MATCH_FCVT_WU_H 0xc4100053 -#define MASK_FCVT_WU_H 0xfff0007f -#define MATCH_FMV_X_H 0xe4000053 -#define MASK_FMV_X_H 0xfff0707f -#define MATCH_FCLASS_H 0xe4001053 -#define MASK_FCLASS_H 0xfff0707f -#define MATCH_FCVT_H_W 0xd4000053 -#define MASK_FCVT_H_W 0xfff0007f -#define MATCH_FCVT_H_WU 0xd4100053 -#define MASK_FCVT_H_WU 0xfff0007f -#define MATCH_FMV_H_X 0xf4000053 -#define MASK_FMV_H_X 0xfff0707f -#define MATCH_FLH 0x1007 -#define MASK_FLH 0x707f -#define MATCH_FSH 0x1027 -#define MASK_FSH 0x707f -#define MATCH_FMADD_H 0x4000043 -#define MASK_FMADD_H 0x600007f -#define MATCH_FMSUB_H 0x4000047 -#define MASK_FMSUB_H 0x600007f -#define MATCH_FNMSUB_H 0x400004b -#define MASK_FNMSUB_H 0x600007f -#define MATCH_FNMADD_H 0x400004f -#define MASK_FNMADD_H 0x600007f -#define MATCH_FCVT_H_D 0x44100053 -#define MASK_FCVT_H_D 0xfff0007f -#define MATCH_FCVT_D_H 0x42200053 -#define MASK_FCVT_D_H 0xfff0007f -#define MATCH_FCVT_H_Q 0x44300053 -#define MASK_FCVT_H_Q 0xfff0007f -#define MATCH_FCVT_Q_H 0x46200053 -#define MASK_FCVT_Q_H 0xfff0007f -#define MATCH_FCVT_L_H 0xc4200053 -#define MASK_FCVT_L_H 0xfff0007f -#define MATCH_FCVT_LU_H 0xc4300053 -#define MASK_FCVT_LU_H 0xfff0007f -#define MATCH_FCVT_H_L 0xd4200053 -#define MASK_FCVT_H_L 0xfff0007f -#define MATCH_FCVT_H_LU 0xd4300053 -#define MASK_FCVT_H_LU 0xfff0007f #define MATCH_VSETVL 0x80007057 #define MASK_VSETVL 0xfe00707f #define MATCH_VSETIVLI 0xc0007057 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f0beceaec44..1226837be90 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -487,9 +487,11 @@ enum M_SH, M_SW, M_SD, + M_FLH, M_FLW, M_FLD, M_FLQ, + M_FSH, M_FSW, M_FSD, M_FSQ, @@ -502,8 +504,6 @@ enum M_SEXTH, M_VMSGE, M_VMSGEU, - M_FLH, - M_FSH, M_NUM_MACROS }; -- 2.34.1