From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id A0EE0385B505 for ; Mon, 28 Nov 2022 04:44:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A0EE0385B505 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id DDED2300089; Mon, 28 Nov 2022 04:44:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1669610666; bh=+PMiStZLbu0tI3NfhVKkbOIv25tSm15twhC6XZyPUrg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=b95StNkUzciM4+A5wRUd7lDVQVIo88S9ZHpz96to1aDv/vy49tAsmOWkT0jkqZ7Jc jW/gxPOmRJzQCT7n+1DQlVaJ4v3RQn4dM1UI26je92+TfjuFC0k5DboZgNu7Y9AUTx MaTqATzDK9ED+bSgm4K3ApJlAaM/iDSUcx05lu8I= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v2 02/11] RISC-V: Add test for 'Zfinx' register switching Date: Mon, 28 Nov 2022 04:43:37 +0000 Message-Id: <761a39a87ef882c6d99d135988d251d18c2bf096.1669610611.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Tsukasa OI Because the author is going to reorganize core RISC-V disassembler, we have to make sure that nothing is broken when disassembling with mapping symbols with ISA string. This commit adds a testcase for 'F' and 'Zfinx' instructions to make sure that "FPR" register names are correctly switched when necessary. gas/ChangeLog: * testsuite/gas/riscv/mapping.s: Add 'F' and 'Zfinx' testcase. * testsuite/gas/riscv/mapping-dis.d: Likewise. * testsuite/gas/riscv/mapping-symbols.d: Likewise. --- gas/testsuite/gas/riscv/mapping-dis.d | 7 +++++++ gas/testsuite/gas/riscv/mapping-symbols.d | 4 ++++ gas/testsuite/gas/riscv/mapping.s | 10 ++++++++++ 3 files changed, 21 insertions(+) diff --git a/gas/testsuite/gas/riscv/mapping-dis.d b/gas/testsuite/gas/riscv/mapping-dis.d index b1a26fbd151b..f0508499b726 100644 --- a/gas/testsuite/gas/riscv/mapping-dis.d +++ b/gas/testsuite/gas/riscv/mapping-dis.d @@ -91,3 +91,10 @@ Disassembly of section .text.relax.align: [ ]+[0-9a-f]+:[ ]+00000013[ ]+nop [ ]+[0-9a-f]+:[ ]+00200513[ ]+li[ ]+a0,2 [ ]+[0-9a-f]+:[ ]+00000013[ ]+nop + +Disassembly of section .text.dis.zfinx: + +0+000 <.text.dis.zfinx>: +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2 +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2 diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d b/gas/testsuite/gas/riscv/mapping-symbols.d index 40df34097369..b28e3306b1b4 100644 --- a/gas/testsuite/gas/riscv/mapping-symbols.d +++ b/gas/testsuite/gas/riscv/mapping-symbols.d @@ -42,6 +42,10 @@ SYMBOL TABLE: 0+00 l d .text.relax.align 0+00 .text.relax.align 0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0 0+08 l .text.relax.align 0+00 \$xrv32i2p1 +0+00 l d .text.dis.zfinx 0+00 .text.dis.zfinx +0+00 l .text.dis.zfinx 0+00 \$xrv32i2p1_f2p2_zicsr2p0 +0+04 l .text.dis.zfinx 0+00 \$xrv32i2p1_zicsr2p0_zfinx1p0 +0+08 l .text.dis.zfinx 0+00 \$xrv32i2p1_f2p2_zicsr2p0 0+0a l .text.section.padding 0+00 \$x 0+03 l .text.odd.align.start.insn 0+00 \$d 0+04 l .text.odd.align.start.insn 0+00 \$x diff --git a/gas/testsuite/gas/riscv/mapping.s b/gas/testsuite/gas/riscv/mapping.s index 3014a69e7920..4fee2b420f0c 100644 --- a/gas/testsuite/gas/riscv/mapping.s +++ b/gas/testsuite/gas/riscv/mapping.s @@ -119,3 +119,13 @@ addi a0, zero, 1 # $x, won't added .align 3 # $x, won't added addi a0, zero, 2 # $xrv32i .option pop + +.section .text.dis.zfinx, "ax" +.option push +.option arch, rv32if +fadd.s fa0, fa1, fa2 # $xrv32if +.option arch, rv32i_zfinx +fadd.s a0, a1, a2 # $xrv32i_zfinx +.option arch, rv32if +fadd.s fa0, fa1, fa2 # $xrv32if +.option pop -- 2.38.1