From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5809 invoked by alias); 15 Jan 2020 14:57:04 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 5042 invoked by uid 89); 15 Jan 2020 14:57:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-4.9 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 spammy=Andre, andre X-HELO: us-smtp-1.mimecast.com Received: from us-smtp-delivery-1.mimecast.com (HELO us-smtp-1.mimecast.com) (205.139.110.120) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 15 Jan 2020 14:56:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1579100212; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:autocrypt:autocrypt; bh=z46/3md9kJC09YYja1TtUln4dwhgmiQOhN4qNhNUDuc=; b=i9GHz4p64zfIfy8d84NhloUKeDwGgX5jA3dZNUXb0FQ+9L2FFeVJnAog3szz3iUNZTImh0 fWtOGI+mKqJanKCqBNx4rRGYfdyoJua7YCkfZPs1XLEh23sz6PRkKbQceRfWo3WlIRCc1R QHh4aTVNDwTreMc2LXdfuUGf1eur0nw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-44-5KnXqcCbOMaW7hA39wPudQ-1; Wed, 15 Jan 2020 09:56:49 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id D7A061856A66; Wed, 15 Jan 2020 14:56:47 +0000 (UTC) Received: from [10.36.117.76] (ovpn-117-76.ams2.redhat.com [10.36.117.76]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 0B25210841A2; Wed, 15 Jan 2020 14:56:46 +0000 (UTC) Subject: Re: [PATCH][binutils][arm] PR25376 Change MVE into a CORE_HIGH feature To: "Andre Vieira (lists)" , "binutils@sourceware.org" Cc: Richard Earnshaw References: <8e5b74b6-1d6f-b7cb-5271-c204a4f6a500@arm.com> From: Nick Clifton Message-ID: <784dceea-11f3-371b-5d4e-03b7114bcdab@redhat.com> Date: Wed, 15 Jan 2020 14:57:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <8e5b74b6-1d6f-b7cb-5271-c204a4f6a500@arm.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2020-01/txt/msg00175.txt.bz2 Hi Andre, > gas/ChangeLog: > 2020-01-13=C2=A0 Andre Vieira=C2=A0 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 PR 25376 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * config/tc-arm.c (mve_ext, mv= e_fp_ext): Use CORE_HIGH. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (armv8_1m_main_ext_table): Use= CORE_HIGH for mve. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * testsuite/arm/armv8_1-m-fpu-= mve-1.s: New. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * testsuite/arm/armv8_1-m-fpu-= mve-1.d: New. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * testsuite/arm/armv8_1-m-fpu-= mve-2.s: New. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * testsuite/arm/armv8_1-m-fpu-= mve-2.d: New. >=20 >=20 > include/ChangeLog: > 2020-01-13=C2=A0 Andre Vieira=C2=A0 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 PR 25376 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * opcodes/arm.h (FPU_MVE, FPU_= MVE_FPU): Move these features to... > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (ARM_EXT2_MVE, ARM_EXT2_MVE_FP= ): ... the CORE_HIGH space. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (ARM_ANY): Redefine to not inc= lude any MVE bits. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (ARM_FEATURE_ALL): Removed. >=20 > opcodes/ChangeLog: > 2020-01-13=C2=A0 Andre Vieira=C2=A0 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 PR 25376 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * opcodes/arm-dis.c (coprocess= or_opcodes): Use CORE_HIGH for > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 MVE bits. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (neon_opcodes): Likewise. > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (select_arm_features): Make su= re we enable MVE bits when > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 selecting armv8.1-m.main. Make= sure we do not enable MVE > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bits when not selecting any ar= chitecture. Approved - please apply. Cheers Nick