From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id EEC653858D1E for ; Mon, 20 May 2024 13:05:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EEC653858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EEC653858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716210327; cv=none; b=IrhKs4oUCvz7JLhnKyARDwztolMJJ/tC0digjBJNg0ILaHVrBc+kpd4dcFzMb/zsdQwNki+DPihijog35X8J99ssxQHk0El00dlO44YTqsuJt+uWoh9I/Ea29ZAPoAndTFbGlNlYRlZNCZeER2R89wzhxoH0oj6z2xHkQjy2ZFo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716210327; c=relaxed/simple; bh=7vGc9CvBF4Tljh8fpkPXllezBKryo1PdZJFy26+P0cY=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=K4n2fCGXRzFIHN/67ShUV+hQ9GGlaWWtNpnBRZE5GhbsK4G7WB5zq4mhezXHlfIfdQ+F9Fjj8DwP+aIf7KBtpTl6p6AYgEXC14+bReiFeCpkDjiHT+ikXT8tJIW9VQMfQllb/FnOqGcnsfyMTUMmNCpLVlzDKtUkgRKQ9NBXikU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 95F01DA7; Mon, 20 May 2024 06:05:49 -0700 (PDT) Received: from [10.2.78.57] (e120077-lin.cambridge.arm.com [10.2.78.57]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2C9DC3F641; Mon, 20 May 2024 06:05:25 -0700 (PDT) Message-ID: <7886872b-8b83-4081-af0c-951de8bb6619@arm.com> Date: Mon, 20 May 2024 14:05:23 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] gas, aarch64: Add AdvSIMD lut extension To: Saurabh Jha , binutils@sourceware.org References: From: "Richard Earnshaw (lists)" Content-Language: en-GB In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3491.3 required=5.0 tests=BAYES_00,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 16/05/2024 11:35, Saurabh Jha wrote: > Introduces instructions for the Advanced SIMD lut extension for AArch64. They are documented in the following links: > * luti2: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI2--Lookup-table-read-with-2-bit-indices-?lang=en > * luti4: https://developer.arm.com/documentation/ddi0602/2024-03/SIMD-FP-Instructions/LUTI4--Lookup-table-read-with-4-bit-indices-?lang=en > > These instructions needed definition of some new operands. We will first > discuss operands for the third operand of the instructions and then > discuss a vector register list operand needed for the second operand. > > The third operands are vectors with bit indices and without type > qualifiers. They are called Em_INDEX1_14, Em_INDEX2_13, and Em_INDEX3_12 > and they have 1 bit, 2 bit, and 3 bit indices respectively. For these > new operands, we defined new parsing case branch and a new instruction > class. We also modified the existing reglane inserters and extractors > to handle the new operands. The lsb and width of these operands are > the same as many existing operands but the convention is to give > different names to fields that serve different purpose so we > introduced new fields in aarch64-opc.c and aarch64-opc.h for these > operands. > > For the second operand of these instructions, we introduced a new > operand called LVn_LUT. This represents a vector register list with > stride 1. We defined new inserter and extractor for this new operand and > it is encoded in FLD_Rn. We are enforcing the number of registers in the > reglist using opcode flag rather than operand flag as this is what other > SIMD vector register list operands are doing. The disassembly also uses > opcode flag to print the correct number of registers. > --- > Hi, > > Regression tested for aarch64-none-elf and found no regressions. > > Ok for binutils-master? I don't have commit access so can someone please commit on my behalf? > > Regards, > Saurabh A couple of minor nits: +++ b/gas/testsuite/gas/aarch64/advsimd-lut-illegal.s @@ -0,0 +1,128 @@ +// Operand mismatch +luti2 v2.16b, { v4.8h }, v8[1] +luti2 v2.8h, { v4.16b }, v8[1] ... In assembly files the convention is that labels start in column 0, while instructions start in column 8 (1 tab stop). +++ b/gas/testsuite/gas/aarch64/advsimd-lut.d @@ -0,0 +1,32 @@ +#objdump: -dr +#as: -march=armv8-a+lut + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: 4e801000 luti2 v0.16b, \{v0.16b\}, v0\[0\] + 4: 4e80101f luti2 v31.16b, \{v0.16b\}, v0\[0\] + 8: 4e8013e0 luti2 v0.16b, \{v31.16b\}, v0\[0\] ... ^^ We normally remove the address component from the dump files (use a regexp), so that inserting (or removing) lines does not cause churn on the testsuite. Otherwise this looks OK.