From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id BFCDF385735D for ; Tue, 25 Oct 2022 13:55:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BFCDF385735D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 35AF5300089 for ; Tue, 25 Oct 2022 13:55:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1666706156; bh=pa8MLmRWzm18x7ySbcUHZ3qLXP1kT+DtcAbcsTm5pKs=; h=Message-ID:Date:Mime-Version:Subject:To:References:From: In-Reply-To:Content-Type:Content-Transfer-Encoding; b=n6F8NCDdE5rbivNmumIt6SBBhtsNUemffD7tfR1G85Izh2AwHR/RFSgHKPtIcJQyw CHLJMSyLHiXOYMEZ0SndNMtaMZtnr00dH+fCJQccP+TvfXO5ChxZ3lFcnWO6Et6AXl hcu7avgF2RDaml8DF/vDxUoBq5qCqiXyCTAVANeY= Message-ID: <7c6dc64d-071e-25d9-9ded-c3991780f1a3@irq.a4lg.com> Date: Tue, 25 Oct 2022 22:55:55 +0900 Mime-Version: 1.0 Subject: Re: [RFC PATCH] RISC-V: Allocate "various" operand type To: binutils@sourceware.org References: <6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com> Content-Language: en-US From: Tsukasa OI In-Reply-To: <6a8e7a71acccd0efb9789dfb3edfa307e83bdaa1.1666702934.git.research_trasio@irq.a4lg.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: RFC PATCH v2 candidate changes (if v1 is approved, will merge as obvious changes): On 2022/10/25 22:04, Tsukasa OI wrote: > This commit intends to move operands that require very special handling or > operand types that are so minor (e.g. only useful on a few instructions) > under "W". I also intend this "W" to be "temporary" operand storage until > we can find good two character (or less) operand type. > > In this commit, prefetch offset operand "f" for 'Zicbop' extension is moved > to "Wif" because of its special handling (and allocating single character > "f" for this operand type seemed too much). > > Current expected allocation guideline is as follows: > > 1. 'W' > 2. The most closely related single-letter extension in lowercase > (strongly recommended but not mandatory) > 3. Identify operand type > > The author currently plans to allocate following three-character operand > types (for operands including instructions from unratified extensions). > > 1. "Wif" ('Zicbop': fetch offset) > 2. "Wfv" (unratified 'Zfa': value operand from FLI.[HSDQ] instructions) > 3. "Wfm" / "WfM" > 'Zfh', 'F', 'D', 'Q': rounding modes "m" with special handling > solely for widening conversion instructions. > > gas/ChangeLog: > > * config/tc-riscv.c (validate_riscv_insn, riscv_ip): Move from > "f" to "Wif". > > opcodes/ChangeLog: > > * riscv-dis.c (print_insn_args): Move from "f" to "Wif". > * riscv-opc.c (riscv_opcodes): Reflect new operand type. > --- > gas/config/tc-riscv.c | 64 +++++++++++++++++++++++++++++++------------ > opcodes/riscv-dis.c | 26 ++++++++++++++---- > opcodes/riscv-opc.c | 6 ++-- > 3 files changed, 71 insertions(+), 25 deletions(-) > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 22385d1baa0..c3ac1d0bf60 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -1243,7 +1243,6 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) > case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; > case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break; > case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break; > - case 'f': /* Fall through. */ > case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; > case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; > case 'z': break; /* Zero immediate. */ > @@ -1270,6 +1269,21 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) > goto unknown_validate_operand; > } > break; > + case 'W': /* RVI various operands. */ s/RVI various operands/Various operands/ > + switch (*++oparg) > + { > + case 'i': > + switch (*++oparg) > + { > + case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break; > + default: > + goto unknown_validate_operand; > + } > + break; > + default: > + goto unknown_validate_operand; > + } > + break; > case 'X': /* Integer immediate. */ > { > size_t n; > @@ -3285,22 +3299,37 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, > imm_expr->X_op = O_absent; > continue; > > - case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */ > - if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) > - continue; > - my_getExpression (imm_expr, asarg); > - check_absolute_expr (ip, imm_expr, false); > - if (((unsigned) (imm_expr->X_add_number) & 0x1fU) > - || imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2 > - || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2) > - as_bad (_("improper prefetch offset (%ld)"), > - (long) imm_expr->X_add_number); > - ip->insn_opcode |= > - ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) & > - ~ 0x1fU); > - imm_expr->X_op = O_absent; > - asarg = expr_end; > - continue; > + case 'W': /* RVI various operands. */ Likewise. > + switch (*++oparg) > + { > + case 'i': > + switch (*++oparg) > + { > + case 'f': > + /* Prefetch offset for 'Zicbop' extension. > + pseudo S-type but lower 5-bits zero. */ > + if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) > + continue; > + my_getExpression (imm_expr, asarg); > + check_absolute_expr (ip, imm_expr, false); > + if (((unsigned) (imm_expr->X_add_number) & 0x1fU) > + || imm_expr->X_add_number >= RISCV_IMM_REACH / 2 > + || imm_expr->X_add_number < -RISCV_IMM_REACH / 2) > + as_bad (_ ("improper prefetch offset (%ld)"), > + (long) imm_expr->X_add_number); > + ip->insn_opcode |= ENCODE_STYPE_IMM ( > + (unsigned) (imm_expr->X_add_number) & ~0x1fU); > + imm_expr->X_op = O_absent; > + asarg = expr_end; > + continue; > + default: > + goto unknown_riscv_ip_operand; > + } > + break; > + default: > + goto unknown_riscv_ip_operand; > + } > + break; > > case 'X': /* Integer immediate. */ > { > @@ -3353,6 +3382,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, > } > } > break; > + > default: > unknown_riscv_ip_operand: > as_fatal (_("internal: unknown argument type `%s'"), > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index daeb1b5fd15..b851bcaa8af 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -473,11 +473,6 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info > (int)EXTRACT_STYPE_IMM (l)); > break; > > - case 'f': > - print (info->stream, dis_style_address_offset, "%d", > - (int)EXTRACT_STYPE_IMM (l)); > - break; > - > case 'a': > info->target = EXTRACT_JTYPE_IMM (l) + pc; > (*info->print_address_func) (info->target, info); > @@ -582,6 +577,27 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info > print (info->stream, dis_style_immediate, "%d", rs1); > break; > > + case 'W': /* RVI various operands. */ Likewise. > + { > + switch (*++oparg) > + { > + case 'i': > + switch (*++oparg) > + { > + case 'f': > + print (info->stream, dis_style_address_offset, "%d", > + (int) EXTRACT_STYPE_IMM (l)); > + break; > + default: > + goto undefined_modifier; > + } > + break; > + default: > + goto undefined_modifier; > + } > + } > + break; > + > case 'X': /* Integer immediate. */ > { > size_t n; > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 4029c1881b8..f3b6ca819bb 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -313,9 +313,9 @@ const struct riscv_opcode riscv_opcodes[] = > /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ > > /* Standard hints. */ > -{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, > -{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, > -{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, > +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, > +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, > +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, > {"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, > > /* Basic RVI instructions and aliases. */ > > base-commit: 0f2cd53cf4f730136e2b275e8279d8bc348a9a88