From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 84093 invoked by alias); 1 May 2019 17:48:22 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 72127 invoked by uid 89); 1 May 2019 17:48:13 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 May 2019 17:48:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 972CC80D for ; Wed, 1 May 2019 10:48:02 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3EC693F719 for ; Wed, 1 May 2019 10:48:02 -0700 (PDT) Subject: [PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp To: binutils@sourceware.org References: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> From: "Andre Vieira (lists)" Message-ID: <7c85111c-1e25-a51c-052b-8f7e1bfdd26a@arm.com> Date: Wed, 01 May 2019 17:48:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> Content-Type: multipart/mixed; boundary="------------B4038277A2820C2B0532E664" X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00081.txt.bz2 This is a multi-part message in MIME format. --------------B4038277A2820C2B0532E664 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 367 Hello, This patch adds support for MVE low-overhead loop tail predicated instructions: LCTP, LETP, WLSTP, and DLSTP. opcodes/ChangeLog: 2019-05-01 Andre Vieira Michael Collison * arm-dis.c (thumb32_opcodes): Add new instructions. (print_insn_thumb32): Handle new instructions. --------------B4038277A2820C2B0532E664 Content-Type: text/x-patch; name="51.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="51.patch" Content-length: 1769 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 6564e41f8d479f5146c040830056cf21e1b0d1db..a2051a9b738237b80cc9044f883ed6a77b734807 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -3949,13 +3949,21 @@ static const struct opcode32 thumb32_opcodes[] = /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), - 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"}, - {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), - 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"}, + 0xf00fe001, 0xffffffff, "lctp%c"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 0xf02fc001, 0xfffff001, "le\t%P"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 0xf00fc001, 0xfffff001, "le\tlr, %P"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf01fc001, 0xfffff001, "letp\tlr, %P"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 0xf040e001, 0xf860f001, "bf%c\t%G, %W"}, @@ -10171,6 +10179,13 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) switch (*c) { + case 's': + if (val <= 3) + func (stream, "%s", mve_vec_sizename[val]); + else + func (stream, ""); + break; + case 'd': func (stream, "%lu", val); value_in_comment = val; --------------B4038277A2820C2B0532E664--